Abstract: An array of heat-sinked power semiconductors that includes a power semiconductor and a heat sink. The power semiconductor has a power semiconductor die, a plurality of first terminals and a second terminal. The power semiconductor die has a plurality of semiconductor terminals. Each of the first terminals is electrically coupled to an associated one of the semiconductor terminals. The second terminal is a surface mount terminal and is electrically coupled to one of the first terminals. The heat sink has a heat sink body and a plurality of fins. The heat sink body has a base and an exterior surface. The base is fixedly coupled directly to the surface mount terminal. The exterior surface has a fin mount portion to which the fins extend. At least a portion of the fin-mount portion is oriented non-parallel to base.

Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.

Abstract: A power electronics module includes a heat sink structurally configured to dissipate thermal energy, an electrically-insulating layer directly contacting the heat sink, a conductive substrate positioned on and in direct contact with the electrically-insulating layer, a power electronics device positioned on and in direct contact with the conductive substrate, a printed circuit board layer that at least partially encapsulates the conductive substrate and the power electronics device, and a driver circuit component positioned on a surface of the printed circuit board layer.

Abstract: A first electronic device may comprise a chassis and first fins. The chassis may be configured to removably couple with a second electronic device. The first fins are configured to interleave with second fins of the second electronic device in a coupled state of the first and second electronic devices. A corrugated thermal interface device comprises folded fins. The folded fins are coupled to the first fins and are also removably couplable to the second fins in the coupled state of the first and second electronic devices. Each folded fin comprises one or more lateral walls, and the corrugated thermal interface device further comprises a plurality of spring fingers coupled to and extending at least partially in a lateral direction from the lateral walls. The spring finger contacts may be contacted and displaced by the second fins in the coupled state of the first and second electronic devices.

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure over the wiring substrate. The chip package structure includes a heat-spreading lid over the wiring substrate and covering the first chip structure. The heat-spreading lid includes a ring structure and a top plate. The ring structure surrounds the first chip structure. The top plate covers the ring structure and the first chip structure. The first chip structure has a first sidewall and a second sidewall opposite to the first sidewall, a first distance between the first sidewall and the ring structure is less than a second distance between the second sidewall and the ring structure, the top plate has a first opening, the first opening has a first inner wall and a second inner wall facing each other.

Abstract: An electronics module (100), especially a power electronics module, comprising a metal-ceramic substrate (1) serving as a carrier and having a ceramic element (10) and a primary component metallization (21), an insulation layer (40) directly or indirectly connected to the primary component metallization (21), and a secondary component metallization (22) which is connected to the side of the insulation layer (40) facing away from the metal-ceramic substrate (1) and is especially isolated from the primary component metallization (21) using the insulation layer (40), wherein the ceramic element (10) has a first size (L1, D1) and the insulation layer (40) has a second size (L2, D2) and a ratio of the second size (L2, D2) to the first size (L1, D1) has a value smaller than 0.8, to form an island-like insulation layer (40) on the primary component metallization (21).

Abstract: A semiconductor product in the form of a stack chip package and a method of manufacturing the same, where a plurality of semiconductor chips are stacked one on another so as to enable the exchange of electrical signals between the semiconductor chips, and where a conductive layer is included for inputting and outputting signals to and from individual chips. A stack chip package having a compact size may, for example, be manufactured by stacking, on a first semiconductor chip, a second semiconductor chip having a smaller surface area by means of interconnection structures so as to enable the exchange of electrical signals between the first and second semiconductor chips, and by using a conductive layer for inputting and outputting signals to and from individual semiconductor chips, in lieu of a thick substrate. Furthermore, heat dissipation effects can be enhanced by the addition of a heat dissipation unit.

Abstract: An electronic device includes: a circuit board having a mounting face, on which an electronic component is mounted; a heat receiver including a heat receiving plate opposed to the electronic component; and a fastening mechanism that fixes the heat receiver to the circuit board. The fastening mechanism includes a receiver having a proximal end and a distal end, the receiver having a mounting hole penetrating from the proximal end to the distal end; and a fastener that is inserted into the mounting hole for fastening to the receiver to press the heat receiver. The receiver is surface-mounted on the mounting face by soldering with the proximal end facing the mounting face.

Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.

Abstract: A semiconductor package including a lid having one or more heat pipes located on and/or within the lid to provide improved thermal management. A lid for a semiconductor package having one or more heat pipes thermally integrated with the lid may provide more uniform heat loss from the semiconductor package, reduce the risk of damage to the package due to excessive heat accumulation, and may enable the lid to be fabricated using less expensive materials, thereby reducing the costs of a semiconductor package.

Abstract: An integrated radiator having a temperature gradient is disposed between a high-temperature device and a low-temperature device. The integrated radiator includes a first heat dissipation unit and a second heat dissipation unit which are integrally fixed. The first heat dissipation unit is configured to maintain the high-temperature device within a first temperature range, and the second heat dissipation unit is configured to maintain the low-temperature device within a second temperature range. A thermal conductive path of the first heat dissipation unit is isolated from a thermal conductive path of the second heat dissipation unit, and the first heat dissipation unit is physically connected to but thermally separated from the second heat dissipation unit.

Abstract: A pluggable processor module includes a microprocessor package, a voltage regulator including a capacitor board, and contacts that each include a first side in contact with the microprocessor package and a second side in contact with the capacitor board. An assembly includes the pluggable processor module and a printed circuit board assembly (“PCBA”) including a module aperture that is large enough to receive the power board and narrower than the capacitor board.

Abstract: Various embodiments described herein provide a label configured for thermal conductivity and configured to pass over an edge of a printed circuit board (PCB) and attached to both sides of the printed circuit board. The label can be used with a printed circuit board that is associated with a memory sub-system, such as a memory module (e.g., solid state drive, SSD module).

Abstract: The disclosure relates to a device for transferring heat between a second module, for example an optical transceiver module, and a first module, for example a heat sink. The device comprises a holder for holding the second module, a first unit configured to be thermally coupled to the first module, and a second unit which is urged against the second module placed in the holder by a biasing apparatus. The first and second units are thermally coupled to one another through a plurality of protrusions of the first or second unit and a plurality of complementary cavities of the other of the first and second unit.

Abstract: A system is including: an overmolded layer that is placed above a top surface and below a bottom surface of a circuit board, wherein the overmolded layer exposes at least communication interfaces on the circuit board and surrounds a heat generating component on the circuit board; a conductive layer that is placed over the overmolded layer on the top surface of the circuit board, wherein the conductive layer exposes the communication interfaces of the circuit board and covers the heat generating component on the circuit board; and wherein heat from the heat generating component is transferred into the conductive layer.

Abstract: A miniaturized and high-power semiconductor package device with its own heat-dissipating ability includes a thermal conductor, a redistribution layer, an electronic device, a molding layer, and a solder ball. The redistribution layer includes a first surface defining an opening, a second surface opposite to the first surface, and a circuit layer. The thermal conductor is disposed in the opening. The electronic device is disposed on the first surface of the redistribution layer above the thermal conductor. The molding layer is formed on the first surface and surrounding the electronic device. The solder balls are disposed on the second surface of the redistribution layer and can form electrical connections to the circuit layer.

Abstract: A circuit board cooling apparatus is disclosed having a heat spreader device to be thermally coupled with a surface of the circuit board to be cooled. Also, a conforming heat transfer device is disclosed that is thermally and physically coupled with the heat spreader device to conform to a surface contour of the heat spreader device on a first side of the heat transfer device. The cooling apparatus also includes a heat transport device physically attached and thermally coupled with a second side of the heat transfer device.

Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.

Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, a system board configured to be electrically connected to the casing, and upper and lower cards connected to the casing for electrically connecting the casing to the system board.

Abstract: A liquid-submersible thermal management system includes a shell, a heat-generating component, a working fluid, and at least one heat-dispersing element. The shell defines an immersion chamber where the heat-generating component is located in the immersion chamber. The working fluid is positioned in the immersion chamber and at least partially surrounds the heat-generating component so the working fluid receives heat from the heat-generating component. The at least one heat-dispersing element is positioned on exterior surface of the shell to conduct heat from the shell into the heat-dispersing element.

Abstract: An image sensor unit is disclosed that includes an array of image sensing pixels, arranged in a plurality of rows and a plurality of columns, wherein each pixel is individually addressable. Each row of pixels is controlled via a row control in communication with the row of pixels in the array via a row addressing line, and capable of selectively addressing one or more of the plurality of rows. Each column of pixels is controlled by a column control in communication with each column of pixels in the array via a column addressing line, and capable of selectively addressing one or more of the plurality of columns. A unit controller is configured to specify selective readout of one or more pixel readout signals by instructing the row and column control to address one or more specific rows and columns of the array.

Abstract: An apparatus including first and second substrates. The first and second substrates each include a base and at least one peripheral wall extending from the base. One of the at least one peripheral walls of the first or second substrates includes at least one well, and the other of the at least one peripheral walls of the first or the seconds substrate that does not include a well is mechanically anchored to the well. The apparatus includes a stack having a first and second end, and the stack is disposed on the base of the first and/or the second substrates at the first and/or second ends. The stack includes at least one element configured to generate energy. A method of assembling the apparatus by contacting the substrates.

Abstract: A power electronics module includes at least one first substrate having on a first side one or more first semiconductor dies, the one or more first semiconductor dies and the at least one first substrate providing a higher power part of the power electronics module, at least one second substrate having on a first side one or more second semiconductor dies, the one or more second semiconductor dies and the at least one second substrate providing a lower power part of the power electronics module, and a common frame at least partially encasing the first and second substrates and being a monobloc part, the higher power part being configured for direct liquid cooling and the lower power part being configured for indirect cooling.

Abstract: An apparatus includes a photonic integrated circuit, which includes at least one splitter configured to split at least one input beam into multiple input beamlets and multiple phase modulators configured to phase-shift at least some of the input beamlets. The apparatus also includes an array of optical amplifiers configured to amplify the phase-shifted input beamlets and generate amplified beamlets. The apparatus further incudes a beam combiner configured to combine the amplified beamlets and generate an output beam. In addition, the apparatus includes a controller configured to control the phase modulators in order to adjust phasing of the phase-shifted input beamlets.

Abstract: A molded semiconductor package includes: a semiconductor die embedded in a mold compound; a first heat spreader partly embedded in the mold compound and thermally coupled to a first side of the semiconductor die; and a second heat spreader partly embedded in the mold compound and thermally coupled to a second side of the semiconductor die opposite the first side. The first heat spreader includes at least one heat dissipative structure protruding from a side of the first heat spreader uncovered by the mold compound and facing away from the semiconductor die. The mold compound is configured to channel a fluid over the at least one heat dissipative structure in a direction parallel to the first side of the power semiconductor die. Corresponding methods of production and electronic assemblies are also described.

Abstract: Techniques and mechanisms for promoting heat conduction in a packaged device using a heat spreader that is fabricated by a build-up process. In an embodiment, 3D printing of a heat spreader successively deposit layers of a thermal conductor material, where said layers variously extend each over a respective one or more IC dies. The heat spreader forms a flat top side, wherein a bottom side of the heat spreader extends over, and conforms at least partially to, different respective heights of various IC dies. In another embodiment, fabrication of a portion of the heat spreader comprises printing pore structures that contribute to a relatively low thermal conductivity of said portion. An average orientation of the oblong pores contributes to different respective thermal conduction properties for various directions of heat flow.

Abstract: The disclosed systems and structures are directed to providing a hybrid liquid-cooling system for at least one rack-mounted immersion case containing at least one electronic assembly submerged in dielectric immersion cooling liquid. The hybrid liquid cooling system comprises a closed-loop fluid distribution arrangement configured to circulate channelized fluid, an external cooling module configured to thermally condition the channelized fluid circulated by the closed-loop fluid distribution arrangement, a serpentine convection coil structured to internally convey channelized fluid to operatively cool ambient temperatures of the dielectric immersion cooling liquid, and one or more fluid cooling blocks arranged to be in direct thermal contact with one or more heat-generating electronic processing components of the at least one electronic assembly.

Abstract: A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where the device includes at least one power supply circuit.

Abstract: A semiconductor device includes a substrate, a package structure, a first heat spreader, and a second heat spreader. The package structure is disposed on the substrate. The first heat spreader is disposed on the substrate. The first heat spreader surrounds the package structure. The second heat spreader is disposed on the package structure. The second heat spreader is connected to the first heat spreader. A material of the first heat spreader is different from a material of the second heat spreader.

Abstract: A method for forming a package structure is provided, including forming an interconnect structure over a carrier substrate and forming a semiconductor die over a first side of the interconnect structure. A removable film is formed over the semiconductor die. The method includes forming a first stacked die package structure over the first side of the interconnect structure. A top surface of the removable film is higher than a top surface of the first stacked die package structure. The method includes forming a package layer, removing a portion of the package layer to expose a portion of the removable film, removing the removable film to form a recess, forming a lid structure over the semiconductor die and the first stacked die package structure. The lid structure has a main portion and a protruding portion disposed in the recess and extending from the main portion.

Abstract: A hybrid semiconductor device includes an interposer substrate, a semiconductor package mounted on the interposer substrate, a molding member on the package substrate covering at least a portion of the semiconductor chip and exposing an upper surface of the semiconductor chip, and a stiffener disposed on an upper surface of the interposer substrate substantially around the semiconductor package.

Abstract: A liquid-submersible thermal management system includes a cylindrical outer shell and an inner shell positioned in an interior volume of the outer shell. The cylindrical outer shell has a longitudinal axis oriented vertically relative to a direction of gravity, and the inner shell defines an immersion chamber. The liquid-submersible thermal management system a spine positioned inside the immersion chamber and oriented at least partially in a direction of the longitudinal axis with a heat-generating component located in the immersion chamber. A working fluid is positioned in the immersion chamber and at least partially surrounding the heat-generating component. The working fluid receives heat from the heat-generating component.

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

Abstract: A module according to the present disclosure includes a circuit board, an electronic component on one of two principal surfaces of the circuit board, a connection conductor on the principal surface of the circuit board, and sealing resin on the principal surface of the circuit board. The electronic component and the connection conductor are covered with the sealing resin. The connection conductor includes a plate-shaped conductor and terminal sections. The plate-shaped conductor is disposed upright on the principal surface of the circuit board. The terminal sections extend from the plate-shaped conductor and away from the principal surface of the circuit board and are arranged side by side. Tip portions of the terminal sections are exposed at a surface of the sealing resin.

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.

Abstract: An imaging unit comprising an imaging chip and a mounting substrate that has the imaging chip mounted thereon and includes a first metal layer for outputting a signal generated by the imaging chip to the outside. An imaging apparatus comprises an imaging unit that includes an imaging chip and a mounting substrate that has the imaging chip mounted thereon and includes a first metal layer for outputting a signal generated by the imaging chip to the outside.

Abstract: An integrated circuit device testing system includes a socket configured to receive an integrated circuit device, wherein the socket comprises at least one conductive trace made of a material with a resistivity that is a function of temperature, and wherein the socket is configured such that, when the integrated circuit device is located in the socket, the at least one conductive trace extends along a surface of the integrated circuit device. The integrated circuit device testing system further includes a controller or active circuit configured to determine a temperature at the surface of the integrated circuit device based on a measured resistance of the at least one conductive trace.

Abstract: Stacked die semiconductor packages may include a spacer die disposed between stacked dies in the semiconductor package and the semiconductor package substrate. The spacer die translates thermally induced stresses on the solder connections between the substrate and an underlying member, such as a printed circuit board, from electrical structures communicably or conductively coupling the semiconductor package substrate to the underlying structure to mechanical structures that physically couple the semiconductor package to the underlying structure. The footprint area of the spacer die is greater than the sum of the footprint areas of the individual stacked dies in the semiconductor package and less than or equal to the footprint area of the semiconductor package substrate. The spacer die may have nay physical configuration, thickness, shape, or geometry. The spacer die may have a coefficient of thermal expansion similar to that of the lowermost semiconductor die in the die stack.

Abstract: A semiconductor device having a radiating element and a directing structure is provided. The semiconductor device includes a device package. A semiconductor die is coupled to the radiating element integrated in the device package. The directing structure is affixed to the device package by way of an adhesive. The directing structure is located over the radiating element and configured for propagation of radio frequency (RF) signals.

Abstract: Power electronics device assemblies, circuit board assemblies, and power electronics assemblies are disclosed. In one embodiment, a power electronics device assembly includes an S-cell including a first metal layer, a first graphite layer bonded to the first metal layer, an electrically insulating layer bonded to the first graphite layer, a second graphite layer bonded to the electrically insulating layer and a second metal layer bonded to the second graphite layer, the second metal layer comprising a surface and a recess provided within the surface. The power electronics device assembly further includes a power electronics device disposed within the recess of the surface.

Abstract: Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge. The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.

Abstract: A driver board assembly includes a printed circuit board (PCB) substrate, one or more power devices embedded within the PCB substrate, and a plurality of conductive layers arranged within the PCB substrate. The plurality of conductive layers are configured to electrically couple the one or more power devices to a current source and thermally couple the one or more power devices to one or more cooling assemblies mounted to at least one of a first surface of the PCB substrate and a second surface of the PCB substrate opposite the first surface of the PCB substrate.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, through substrate vias, conductive pillars and dummy conductive pillars. The interconnection structure is disposed at a front side of the semiconductor substrate, and comprises a stack of dielectric layers and interconnection elements spreading in the stack of dielectric layers. The through substrate vias separately penetrate through the semiconductor substrate and the stack of dielectric layers. The conductive pillars are disposed at a front side of the interconnection structure facing away from the semiconductor substrate, and respectively in electrical connection with one of the through substrate vias. The dummy conductive pillars are disposed aside the conductive pillars at the front side of the interconnection structure.

Abstract: A cooling array for cooling of an electronic component includes the electronic component, a housing which at least partially enclosing the electronic component, a heat sink support connected to the housing in a fluid-tight manner, and a heat sink which is accommodated in the heat sink support. The heat sink is thermally coupled to the electronic component in order to disperse heat generated by the electronic component.

Abstract: According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing.

Abstract: A package includes a circuit that includes at least one active area and at least one secondary device area, a support configured to support the circuit, and a die attach material. The circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.

Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.

Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.

Abstract: The disclosure relates to an electronic system including a plurality of adjacent, elementary power electronics modules and connected to one another by an electrical module connection. Each elementary module including at least one power component integrated on a printed circuit inserted between two electrically conductive heat sinks. The electrical module connection is made by heat sinks at the side and/or central connection surfaces thereof.

Abstract: An apparatus for a common cooling solution for multiple packages of a common height, including: a first die package; a second die package having a same height as the first die package; and a cooling element thermally coupled to the first die package and the second die package by a planar surface of the cooling element.