For Integrated Circuit Patents (Class 257/713)
  • Patent number: 11521939
    Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a die and a stiffener. The substrate has an upper surface. The die is disposed on the upper surface of the substrate. The stiffener is disposed on the upper surface of the substrate and surrounds the die. The stiffener has a first upper surface adjacent to the die, a second upper surface far from the die and a lateral surface extending from the first upper surface to the second upper surface. A first distance between the first upper surface of the stiffener and the upper surface of the substrate is less than a second distance between the second upper surface of the stiffener and the upper surface of the substrate.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: December 6, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jui-Tzu Chen, Yu-Hsing Lin, Chia-Chieh Hu, Chun-Cheng Kuo, Yu-Hsiang Chao
  • Patent number: 11515259
    Abstract: A method for the integration of semiconductor components in a confined space, in particular for 3D integration, in which, after positioning relative to a carrier substrate and/or a redistribution layer, the semiconductor components are protected and fixed in their relative position by introduction of a potting compound, characterized in that before the introduction of the potting compound, a glass substrate having a multiplicity of cutouts separated by partition walls and serving to receive a semiconductor component, is positioned in such a way that the semiconductor component is enclosed by the sidewall surfaces—facing it—of the respective partition walls of the glass substrate.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: November 29, 2022
    Assignee: LPKF LASER & ELECTRONICS AG
    Inventors: Roman Ostholt, Norbert Ambrosius
  • Patent number: 11508679
    Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: November 22, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Soon Wei Wang, Chee Hiong Chew, Francis J. Carney
  • Patent number: 11502075
    Abstract: A semiconductor structure includes a first semiconductor substrate, a second semiconductor substrate, a depletion layer, an isolation structure, a first gate structure, and a second gate structure. The first and second semiconductor substrates respectively have a first active region and a second active region overlapping the first active region. The depletion layer is disposed between the first active region and the second active region. The isolation structure surrounds the first and second active regions. The first gate structure is disposed in the second active region. The second gate structure is disposed in the second active region. The second active region has a portion between the first gate structure and the second gate structure.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: November 15, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Tseng-Fu Lu
  • Patent number: 11482471
    Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 25, 2022
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Junnan Zhao, Zhimin Wan, Ying Wang, Yikang Deng, Chong Zhang, Jiwei Sun, Zhenguo Jiang, Kyu-Oh Lee
  • Patent number: 11482482
    Abstract: A substrate structure, a method for manufacturing the same and a semiconductor device structure including the same are provided. The substrate structure includes a heat pipe, a first conductive layer and an insulation layer. The heat pipe has an upper surface and a lower surface. The heat pipe includes an opening extending from the upper surface to the lower surface. The first conductive layer is disposed on the upper surface and includes a via structure passing through the opening. The insulation layer is disposed between the heat pipe and the conductive layer.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: October 25, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ian Hu, Jin-Feng Yang, Cheng-Yu Tsai, Hung-Hsien Huang
  • Patent number: 11483951
    Abstract: A method for forming an assembly is provided. The method includes depositing a colloidal template onto a substrate, wherein the colloidal template is porous, depositing a metal layer onto and within the colloidal template, depositing a cap structure onto the colloidal template opposite of the substrate, and removing the colloidal template from between the substrate and the cap structure to form a metal inverse opal structure disposed therebetween. The method continues by depositing an electrical isolation layer in contact with the cap structure opposite the metal inverse opal structure, and attaching the electrical isolation layer to a cooling device.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: October 25, 2022
    Assignees: Toyota Motor Engineering & Manufacturing North America, Inc., The Board of Trustees of the University of Illinois
    Inventors: Shailesh N. Joshi, Paul Braun, Julia Kohanek, Gaurav Singhal
  • Patent number: 11476242
    Abstract: The present invention provides a packaging method and a packaging structure for a cascode power electronic device, in which a hetero-multiple chip scale package is used to replace the traditional die bonding and wire bonding packaging method. The cascode power electronic device can reduce the inductance resistance and thermal resistance of the connecting wires and reduce the size of the package; and increase the switching frequency of power density. The chip scale package of the present invention uses more than one gallium nitride semiconductor die, more than one diode, and more than one metal oxide semiconductor transistor. The package structure can use TO-220, quad flat package or other shapes and sizes; the encapsulation process of the traditional epoxy molding compounds can be used in low-power applications; and the encapsulation process of ceramic material can be used in high-power applications.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: October 18, 2022
    Assignee: ULTRABAND TECHNOLOGIES INC.
    Inventors: Tai-Hui Liu, Chung-Hsi Liu
  • Patent number: 11456227
    Abstract: A mechanism is provided to remove heat from an integrated circuit (IC) device die by directing heat through a waveguide to a heat sink. The waveguide is mounted on top of a package containing the IC device die. The waveguide is thermally coupled to the IC device die. The waveguide transports the heat to a heat sink coupled to the waveguide and located adjacent to the package on top of a printed circuit board on which the package is mounted. Embodiments provide both thermal dissipation of the generated heat while at the same time maintaining good radio frequency performance of the waveguide.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 27, 2022
    Assignee: NXP USA, INC.
    Inventors: Michael B. Vincent, Antonius Johannes Matheus de Graauw, Giorgio Carluccio, Waqas Hassan Syed, Maristella Spella
  • Patent number: 11456328
    Abstract: Image sensors include a pixel die that is stacked on a logic die. The logic die includes at least one function logic element disposed on a bond side thereof, and a logic oxide array of raised logic oxide features also disposed on the bond side. The pixel die includes a pixel array disposed on a light receiving side thereof, and a pixel oxide array of raised pixel oxide features disposed on a bond side of the pixel die. A plurality of outer bonds is disposed between an outer region of the logic die and an outer region of the pixel die. A plurality of inner bonds is formed at an inner region of the image sensor between the pixel oxide array and the logic oxide array, the inner bonds being spaced apart by a plurality of fluidly connected air gaps that extend between the logic die and the pixel die.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: September 27, 2022
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventor: Sing-Chung Hu
  • Patent number: 11450632
    Abstract: A semiconductor package includes a redistribution structure including an insulating layer having an upper surface and a lower surface, a redistribution pad and a redistribution pattern on the lower surface of the insulating layer and electrically connected to each other, and a passivation layer on the lower surface of the insulating layer and having an opening exposing at least a portion of the redistribution pad; a semiconductor chip on the redistribution structure and including a connection pad electrically connected to the redistribution pad; an encapsulant on the redistribution structure and encapsulating the semiconductor chip; and a connection bump and a dummy bump on the passivation layer, wherein the redistribution pattern has a width narrower than a width of the redistribution pad, the connection bump vertically overlaps the redistribution pad, and the dummy bump vertically overlaps the redistribution pattern.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: September 20, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Taeho Kang
  • Patent number: 11452206
    Abstract: A card-type solid state drive (SSD) including: a substrate that has a first surface and a second surface facing each other; a memory controller and a nonvolatile memory device that are on the first surface; a plurality of functional terminals on the second surface; and a plurality of thermal terminals on the second surface, wherein the functional terminals include first-row functional terminals, second-row functional terminals, and third-row functional terminals, wherein at least one of the first-row functional terminals, at least one of the second-row functional terminals, and at least one of the third-row functional terminals are electrically connected to the memory controller or the nonvolatile memory device, and wherein the thermal terminals are not electrically connected to the memory controller or the nonvolatile memory device.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: September 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-Jae Lee, Youngdong Kim, Sang Sub Song, Ki-Hong Jeong
  • Patent number: 11441953
    Abstract: A power circuit module includes an electronic circuit board, a heat generating element mounted on a first surface of the electronic circuit board and being a semiconductor electronic component that constitutes a part of a power circuit, a temperature detecting element that detects the temperature of the heat generating element, an electric circuit wiring, a heat dissipating body that dissipates heat of the heat generating element, and a heat conduction sheet having elasticity and flexibility, and a thickness. The heat conduction sheet is between the heat generating element and the heat dissipating body, the temperature detecting element is thermally connected to the heat generating element via the heat conduction sheet and is electrically connected via the electric circuit wiring, and with regard to the sizes of the components, the following relationship holds: temperature detecting element<heat generating element<heat dissipating body.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 13, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tatsuya Hosotani
  • Patent number: 11443995
    Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Tzuan-Horng Liu
  • Patent number: 11444036
    Abstract: A power module assembly is disclosed and includes a package body, a first wiring layer, a capacitor, and a system bus set. The package body includes a first surface, a second surface and two switches connected in series to form a bridge arm between the first surface and the second surface. The first wiring layer is disposed on the first surface. The capacitor is connected in parallel with the bridge arm to form a first high-frequency loop. The system bus set includes a positive-electrode bus and a negative-electrode bus fanned out from the first surface, respectively. The projection of the positive-electrode bus or/and the negative-electrode bus on the first surface is at least partially overlapped with the projection of the two switches on the first surface. The bridge arm is electrically connected between the positive-electrode bus and the negative-electrode bus to form a second high-frequency loop.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: September 13, 2022
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Shouyu Hong, Yan Tong, Weicheng Zhou, Dongfang Lian, Haiyang Cao, Haibin Xu, Tao Wang, Yicong Xie
  • Patent number: 11444003
    Abstract: An integrated heat spreader includes channel structures assembled in a frame. Each channel structure is independent of the other, and can be used to dissipate heat from integrated circuitry at a specific location within a package, and without allowing heat from that particular location to propagate to integrated circuitry at other locations within the package. Each channel structure can be implemented with metal having a high thermal conductivity (e.g., copper). The channel structures can be used in conjunction with liquid-based cooling or air-based cooling. The frame can be implemented with low thermal conductivity molding compound or plastic so the heat transfer from one channel structure to another is inhibited. The channel structures can have different configurations (e.g., straight, pillars, and/or pin fins) to provide different rates of flow, mixing, and/or cooling. The flow direction of air or liquid for the channel structures can be the same (parallel) or different (counter).
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Chia-Pin Chiu, Chandra Mohan Jha, Weihua Tang, Shankar Devasenathipathy
  • Patent number: 11444002
    Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Chen-Hua Yu, Chung-Shi Liu, Hsiao-Chung Liang, Hao-Yi Tsai, Chien-Ling Hwang, Kuo-Lung Pan, Pei-Hsuan Lee, Tin-Hao Kuo, Chih-Hsuan Tai
  • Patent number: 11430768
    Abstract: A chip package structure includes a wiring board, a first chip, a second chip, a thermally conductive material, a molding compound and a heat dissipation part. The wiring board includes a plurality of circuit pads. The first chip is mounted on the wiring board and is electrically connected to at least one of the circuit pads. The first chip is located between the second chip and the wiring board. The thermally conductive material is located on the wiring board and penetrates the second chip and the first chip to extend to the wiring board. The molding compound is disposed on the wiring board, and the heat dissipation part is disposed on the molding material and thermally coupled to the thermally conductive material.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: August 30, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Tzu-Hsuan Wang, Chen-Hsien Liu
  • Patent number: 11432441
    Abstract: The present application discloses a display module (20) and a display apparatus (10). The display panel (10) includes a heat dissipation structure (70) for dissipating heat of a source driver (60). The heat dissipation structure (70) is adhered to an upper surface (61) of the source driver (60) far away from the printed circuit board (50), and at least one side or top corner of the upper surface (61) is not adhered with the heat dissipation structure.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: August 30, 2022
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Mingliang Wang
  • Patent number: 11424222
    Abstract: A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; and a via disposed through the first level, where the first level thickness is less than two microns.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: August 23, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 11408692
    Abstract: A liquid cooling device includes a liquid cooling conductor, a detecting probe, and a determining circuit. The liquid cooling conductor includes a chamber defined therein for communicating with the outside, the chamber is configured to accommodate the coolant, and the surface of the liquid cooling conductor is provided with at least one communicating port communicating with the chamber; wherein the liquid cooling conductor is formed joining at least two combination blocks, and at least one of the two combination blocks is a metal conductor. The detecting probe is disposed on the liquid cooling conductor and normally electrically disconnected from the metal conductor. The determining circuit is electrically connected to the metal conductor and the detecting probe, and generates a liquid leakage alarm signal when the metal conductor and the detecting probe are electrically connected.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: August 9, 2022
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Shun-Chih Huang, Tai-Chuan Mao, Ching-Yu Lu, Yi-Jhen Lin, Liang-Yu Wu
  • Patent number: 11410981
    Abstract: A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, Owen R. Fay
  • Patent number: 11402160
    Abstract: A heat exchanger includes a fin body and a heat pipe having a first portion disposed on or at least partially within the fin body and a second portion extending from the fin body, wherein the heat pipe includes a hollow core filled with a heat pipe working fluid having a liquid phase that is configured to transition to gas and to be returned to the liquid phase at an operational temperature of the heat exchanger.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: August 2, 2022
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Peter L. Jalbert, Leo J. Veilleux, Jr.
  • Patent number: 11388841
    Abstract: An electronic device according to various embodiments of the disclosure includes: a housing including a plurality of acoustic holes; an enclosure mounted in the housing; at least one heating element disposed in the enclosure; a heat dissipation structure disposed on the heating element to transfer heat generated from the heating element; and a heat dissipation duct disposed at least partially on the heat dissipation structure to provide a path for transferring the heat transferred from the heat dissipation structure to the outside through the acoustic holes. The heat dissipation structure may include: at least one first heat transfer member coupled to the one heating element; and a second heat transfer member disposed at least partially on the first heat transfer member to transfer, to the heat dissipation duct, heat transferred from the first heat transfer member.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunmin Oh, Sungjin Park, Daegyu Kang, Insu Kim, Daegi Lee, Jonghyun Lee
  • Patent number: 11367540
    Abstract: Embodiments described herein relate generally to large scale synthesis of thinned graphite and in particular, few layers of graphene sheets and graphene-graphite composites. In some embodiments, a method for producing thinned crystalline graphite from precursor crystalline graphite using wet ball milling processes is disclosed herein. The method includes transferring crystalline graphite into a ball milling vessel that includes a grinding media. A first and a second solvent are transferred into the ball milling vessel and the ball milling vessel is rotated to cause the shearing of layers of the crystalline graphite to produce thinned crystalline graphite.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: June 21, 2022
    Assignee: NanoXplore Inc.
    Inventors: Marie Bozalina, Philippe Perret, Soroush Nazarpour
  • Patent number: 11357097
    Abstract: Heat management in electronic components is an important factor in managing the performance and longevity of such electronic components. By omitting a thermal interface layer and providing thermal vias between a heatsink and an electronic component, such as a surface mount technology (SMT) package, such components may improve thermal transfer to the heatsink and simplify assembly. Thermal vias may be fused during reflow to the heatsink and/or electronic component. As a benefit to the improved heat transfer provided, electronic components may operate at a lower temperature or be configured to perform greater heat-producing activities.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: June 7, 2022
    Assignee: Flex Ltd.
    Inventors: Yung You Lin, Lien Jin Chiang, Hung Cheng Chang
  • Patent number: 11355412
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 7, 2022
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Gamal Refai-Ahmed, Henley Liu, Myongseob Kim, Tien-Yu Lee, Suresh Ramalingam, Cheang-Whang Chang
  • Patent number: 11337346
    Abstract: An electronic device module includes a first substrate, at least one electronic device mounted on a lower surface of the first substrate, a second substrate mounted on a lower surface of the first substrate to electrically connect the first substrate to an external source of power, a connecting conductor bonded to a lower surface of the second substrate, and a sealing portion sealing the electronic device, the second substrate, and the connecting conductor, wherein a mounting height of the second substrate is configured to be lower than a mounting height of the electronic device.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: May 17, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Chul Hwan Jung
  • Patent number: 11328977
    Abstract: This application is directed to a semiconductor system including a substrate, an electronic device, a plurality of compliant interconnects and a support structure. The substrate has a first surface and a plurality of first contacts formed on the first surface. The electronic device has a second surface facing the first surface of the substrate, and a plurality of second contacts formed on the second surface. The compliant interconnects are disposed between the first surface of the substrate and the second surface of the electronic device, and are configured to electrically couple the first contacts on the first surface of the substrate to the second contacts on the second surface of the electronic device. The support structure is coupled to the substrate and the electronic device, and extends beyond a footprint of the electronic device. The support structure is configured to mechanically couple the electronic device to the substrate.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: May 10, 2022
    Assignee: COBHAM COLORADO SPRINGS INC.
    Inventor: Sean Leighton Thorne
  • Patent number: 11326836
    Abstract: A vapor/liquid condensation system includes a condensation unit and an evaporation unit. The condensation unit is connected with the evaporation unit via conduits. The evaporation unit has a liquid inlet, a vapor outlet and an evaporation chamber in communication with each other. The evaporation unit converts liquid-phase working fluid into vapor-phase working fluid, which spreads to the condensation unit. The condensation unit cools and condenses the vapor-phase working fluid into liquid-phase working fluid, which goes back the evaporation unit. After the vapor-phase working fluid enters the condensation unit, the vapor-phase working fluid is distributed and condensed into liquid-phase working fluid. Then the liquid-phase working fluid is collected and then goes back to the evaporation unit. The length of the pipeline is shortened and the pipeline pressure is lowered to avoid interruption of heat dissipation circulation and failure in heat dissipation.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: May 10, 2022
    Assignee: ASIA VITAL COMPONENTS CO., LTD.
    Inventors: Chih-Peng Chen, Yu-Min Lin
  • Patent number: 11330704
    Abstract: An electronic control device includes a housing that stores a substrate on which an electronic component is mounted, a first capacitance unit formed between the housing and the electronic component, and a second capacitance unit formed between the housing and the substrate, in which a noise transmission path is formed between the housing and the substrate via the first capacitance unit and the second capacitance unit.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: May 10, 2022
    Assignee: HITACHI ASTEMO, LTD.
    Inventors: Masahiro Toyama, Umberto Paoletti, Takeshi Yamakawa, Yoko Ohkubo, Hideyuki Sakamoto
  • Patent number: 11322819
    Abstract: An antenna module according to an embodiment of the present disclosure includes a dielectric substrate, a first antenna element, a first radio-frequency element, and a first heat-dissipating component. The first antenna element is provided on the dielectric substrate. The first radio-frequency element supplies electric power to the first antenna element. The first heat-dissipating component directs heat from the first radio-frequency element to the outside. The dielectric substrate, the first radio-frequency element, and the first heat-dissipating component are stacked in this order in the Z-axis direction, which is the direction normal to the dielectric substrate. The first heat-dissipating component includes metal. The first heat-dissipating component has a first width at its first position that differs from a second width at its second position located away from the first position in the Z-axis direction.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: May 3, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kengo Onaka, Kuniaki Yosui, Hirotsugu Mori
  • Patent number: 11324111
    Abstract: An apparatus for a shielding structure for surface-mount components and filters to increase the signal isolation from input signal port to output signal port. An LTCC filter device with an increased rejection of undesired frequencies in a stopband and minimal distortion or loss of desired signals in a passband.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: May 3, 2022
    Assignee: Scientific Components Corporation
    Inventors: Aaron Vaisman, Benjamin Kahtan, Behnam Tabrizi, Himat Hayer
  • Patent number: 11272640
    Abstract: A solid-state drive device includes a first module including a first region containing a volatile main memory device and a controller device and a second region containing a first nonvolatile memory device, a second module disposed on the first module and having a third region containing a second nonvolatile memory device, the second module being connected to the first module, and a heat dissipating member disposed on the second module as vertically juxtaposed with the first and second modules. The heat dissipating member has a protruding portion protruding toward the first module and in direct thermal contact with the first region, and a plate-shaped portion having a main surface in direct thermal contact with the third region.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: March 8, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Chul Hur, Do Il Kong
  • Patent number: 11257741
    Abstract: A semiconductor package may comprise: a first passivation layer forming an electrical connection with one or more first bumps; a substrate layer including a second passivation layer and a silicon layer; a back-end-of-line (BEOL) layer formed on the substrate layer; and a third passivation layer formed on the BEOL layer forming an electrical connection with one or more second bumps, wherein the substrate layer includes a first signal TSV (Through Silicon Via) which transmits a first signal between the BEOL layer and a first lower pad, a second signal TSV which transmits a second signal between the BEOL layer and a second lower pad, and a ground TSV which is disposed between the first signal TSV and the second signal TSV and formed so that one end thereof is connected to the BEOL layer and the other end thereof floats.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: February 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo Pu, Jun So Pak, Sung Wook Moon
  • Patent number: 11251350
    Abstract: A light-emitting diode package including a carrier structure, a patterned conductive layer, at least one chip, a dielectric layer, at least one first conductive via, a build-up circuit structure, and at least one light-emitting diode is provided. The patterned conductive layer is disposed on the carrier structure. The chip is disposed on the carrier structure. The dielectric layer is disposed on the carrier structure and encapsulates the chip and the patterned conductive layer. The first conductive via penetrates the dielectric layer and is electrically connected to the patterned conductive layer. The build-up circuit structure is disposed on the dielectric layer and electrically connected to the first conductive via. The light-emitting diode is disposed on the build-up circuit structure.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: February 15, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Yi-Cheng Lin, Yu-Hua Chen, Chun-Hsien Chien, Chien-Chou Chen, Cheng-Hui Wu
  • Patent number: 11240940
    Abstract: A heat radiation structure of an electric parts assembly, a heat conduction sheet, and a method of manufacturing an electric parts assembly are provided that are capable of reducing a gap between neighboring separate sheets after sheet compression while minimizing an unintentional increase in sheet reaction force. A heat conduction sheet (101A) disposed between a cooler and a heat generating element includes a plurality of separate sheets (102), each of the separate sheets (102) includes a plurality of convex sections protruding circumferentially outward from the sheet and a plurality of concave section recessed circumferentially inward on an outer circumferential edge of a shape when seen in a plan view in a state before being pinched between a cooler and a heat generating element, and the convex sections and the concave sections are disposed to be arranged alternately in a circumferential direction of the separate sheets (102) in a shape when seen in a plan view.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: February 1, 2022
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Takaaki Fushimi, Ryota Kitamoto, Jun Kato
  • Patent number: 11233037
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: January 25, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Hayashi, Akihiro Suzaki, Masaaki Matsuo, Ryuta Watanabe, Makoto Ikenaga
  • Patent number: 11232995
    Abstract: To provide a semiconductor device capable of effectively releasing heat from a semiconductor element, the semiconductor device includes a semiconductor element, a heat sink connected thermally to the semiconductor element and a coolant flow channel formed facing the heat sink. The heat sink is integrally composed of multiple cooling fins projecting toward the coolant flow channel. A linear base of each of the multiple cooling fins inclines relative to a direction in which a coolant is supplied through the coolant flow channel. An inclination of a linear base of each of the cooling fins arranged adjacent to each other in the direction relative to the coolant flow direction is substantially opposite from each other.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: January 25, 2022
    Assignee: DENSO CORPORATION
    Inventors: Hiroki Matsuzawa, Bahman Hossini Soltani, Kazuya Takeuchi
  • Patent number: 11217506
    Abstract: In a general aspect, a semiconductor device assembly can include a substrate, a semiconductor die disposed on the substrate, a thermally conductive spacer having a first side and a second side, the second side being opposite the first side. The first side of the thermally conductive spacer can include a plurality of steps that are coupled with the substrate. The first side of the thermally conductive spacer can also include a surface that is disposed between the plurality of steps, where the surface can be coupled with the semiconductor die.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: January 4, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atapol Prajuckamol, Chee Hiong Chew
  • Patent number: 11205620
    Abstract: An integrated circuit module, system and method of providing power and signals is disclosed that includes a silicon chip and a package substrate having voltage connections and signal connections. The silicon chip includes a silicon substrate having a top surface, a bottom surface and circuitry formed therein, one or more front-side metal layers formed on the top surface of the silicon substrate, one or more back-side metal layers formed on the bottom surface of the silicon substrate, and one or more through silicon vias (TSVs) formed through the silicon substrate for creating a conductive pathway from the back-side of the silicon substrate to the front-side of the silicon substrate, preferably closest to the silicon substrate.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: December 21, 2021
    Assignee: International Business Machines Corporation
    Inventors: Hassan Naser, Daniel Stasiak
  • Patent number: 11201127
    Abstract: A device that includes a first package and a second package coupled to the first package. The first package includes a first integrated device, a first encapsulation layer encapsulating the first integrated device, a plurality of vias traveling through the first encapsulation layer, a first redistribution portion comprising a first plurality of redistribution interconnects, wherein the first redistribution portion is coupled to the first encapsulation layer, and a first plurality of contacts coupled to the first integrated device.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: December 14, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Jonghae Kim, Milind Shah, Periannan Chidambaram
  • Patent number: 11184225
    Abstract: Methods, computer program products, and systems are presented. There can be provided for example: obtaining user defined connectivity pattern information; and establishing commands for provisioning one or more network device for implementation of a network connection based on the user defined connectivity pattern information.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Milly Chen, Dan Lu, Chun Feng Wu, Nan Zhang, Xiao Yang Zhu
  • Patent number: 11177193
    Abstract: The disclosure describes a heat-dissipating object having a reservoir structure so that a reservoir system can be formed in an electronic device, allowing for a liquid TIM in the gap between the heat-dissipating object and the electronic device. The reservoir structure comprises a seal ring, a connecting hole and a reservoir which is a tube for taking in a liquid material and releasing it again when needed. A heat-dissipating object, including a heat sink, a cold plate and a vapor chamber and an electronic device, including a flip chip package and a lidded flip chip package are particularly described in details of the embodiments of the present invention.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: November 16, 2021
    Inventor: Yuci Shen
  • Patent number: 11152330
    Abstract: A method for forming a semiconductor package structure includes stacking chips to form a chip stack over an interposer. The method also includes disposing a semiconductor die over the interposer. The method also includes filling a first encapsulating layer between the chips and surrounding the chip stack and the semiconductor die. The method also includes forming a second encapsulating layer covering the chip stack and the semiconductor die. The first encapsulating layer fills the gap between the chip stack and the semiconductor die.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Chieh Li, Pu Wang, Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu
  • Patent number: 11145569
    Abstract: A module that has excellent heat dissipation performance and enables height reduction easily is provided. The module includes a wiring substrate, a plurality of components mounted on the top surface of the wiring substrate, a plurality of heat dissipation members, a sealing resin layer laminated on the top surface of the wiring substrate, and a shield film that covers surfaces of the sealing resin layer. The heat dissipation member is formed into a strip-shaped sheet. In addition, both end portions of the heat dissipation member are in contact with the top surface of the wiring substrate and also with the components disposed between the both end portions. The heat dissipation member thereby forms a heat dissipation path that transmits heat generated by the component to the wiring substrate.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: October 12, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Akihiro Fujii, Toru Komatsu
  • Patent number: 11122706
    Abstract: A heat transfer apparatus and method of manufacture is disclosed. The manifold may have a first mechanical interface, a second mechanical interface remote from the first mechanical interface and one or more internal walls defining at least first and second channels within the manifold between the first and second mechanical interfaces. An evaporator member may be attached to the manifold so as to seal the first mechanical interface. A condenser member may be attached to the manifold so as to seal the second mechanical interface. The manifold, evaporator and condenser members may provide a contained heat transfer system in which a working fluid moves between the condenser member and the evaporator member.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: September 14, 2021
    Assignee: Nokia Technologies Oy
    Inventor: Nicholas Jeffers
  • Patent number: 11099616
    Abstract: A pluggable electronic device includes a base, a heat source module and an upper cover. The base is made of a metal material. The heat source is disposed at the base. The upper cover covers the heat source module, is connected to the base, and includes an enclosed cavity and an operating fluid cyclically performing evaporation and condensation in the enclosed cavity.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: August 24, 2021
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventor: Chi-Jung Wu
  • Patent number: 11096313
    Abstract: Heat sink and heat sink arrangements are provided for an electronic device immersed in a liquid coolant. A heat sink may comprise: a base for mounting on top of a heat-transmitting surface of the electronic device and transferring heat from the heat-transmitting surface; and a retaining wall extending from the base and defining a volume. A heat sink may have a wall arrangement to define a volume, in which the electronic device is mounted. A heat sink may be for an electronic device to be mounted on a surface in a container, in an orientation that is substantially perpendicular to a floor of the container. Heat is transferred from the electronic device to liquid coolant held in the heat sink volume. A cooling module comprising a heat sink is also provided. A nozzle arrangement may direct liquid coolant to a base of the heat sink.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: August 17, 2021
    Assignee: Iceotope Group Limited
    Inventors: David Amos, Neil Edmunds, Andrew Young, Jasper Kidger, Nathan Longhurst
  • Patent number: 11094608
    Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: August 17, 2021
    Inventors: Po-Hsiang Huang, Chin-Chou Liu, Chin-Her Chien, Fong-yuan Chang, Hui Yu Lee