For Integrated Circuit Patents (Class 257/713)
  • Patent number: 11145569
    Abstract: A module that has excellent heat dissipation performance and enables height reduction easily is provided. The module includes a wiring substrate, a plurality of components mounted on the top surface of the wiring substrate, a plurality of heat dissipation members, a sealing resin layer laminated on the top surface of the wiring substrate, and a shield film that covers surfaces of the sealing resin layer. The heat dissipation member is formed into a strip-shaped sheet. In addition, both end portions of the heat dissipation member are in contact with the top surface of the wiring substrate and also with the components disposed between the both end portions. The heat dissipation member thereby forms a heat dissipation path that transmits heat generated by the component to the wiring substrate.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: October 12, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Akihiro Fujii, Toru Komatsu
  • Patent number: 11122706
    Abstract: A heat transfer apparatus and method of manufacture is disclosed. The manifold may have a first mechanical interface, a second mechanical interface remote from the first mechanical interface and one or more internal walls defining at least first and second channels within the manifold between the first and second mechanical interfaces. An evaporator member may be attached to the manifold so as to seal the first mechanical interface. A condenser member may be attached to the manifold so as to seal the second mechanical interface. The manifold, evaporator and condenser members may provide a contained heat transfer system in which a working fluid moves between the condenser member and the evaporator member.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: September 14, 2021
    Assignee: Nokia Technologies Oy
    Inventor: Nicholas Jeffers
  • Patent number: 11099616
    Abstract: A pluggable electronic device includes a base, a heat source module and an upper cover. The base is made of a metal material. The heat source is disposed at the base. The upper cover covers the heat source module, is connected to the base, and includes an enclosed cavity and an operating fluid cyclically performing evaporation and condensation in the enclosed cavity.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: August 24, 2021
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventor: Chi-Jung Wu
  • Patent number: 11096313
    Abstract: Heat sink and heat sink arrangements are provided for an electronic device immersed in a liquid coolant. A heat sink may comprise: a base for mounting on top of a heat-transmitting surface of the electronic device and transferring heat from the heat-transmitting surface; and a retaining wall extending from the base and defining a volume. A heat sink may have a wall arrangement to define a volume, in which the electronic device is mounted. A heat sink may be for an electronic device to be mounted on a surface in a container, in an orientation that is substantially perpendicular to a floor of the container. Heat is transferred from the electronic device to liquid coolant held in the heat sink volume. A cooling module comprising a heat sink is also provided. A nozzle arrangement may direct liquid coolant to a base of the heat sink.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: August 17, 2021
    Assignee: Iceotope Group Limited
    Inventors: David Amos, Neil Edmunds, Andrew Young, Jasper Kidger, Nathan Longhurst
  • Patent number: 11094608
    Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: August 17, 2021
    Inventors: Po-Hsiang Huang, Chin-Chou Liu, Chin-Her Chien, Fong-yuan Chang, Hui Yu Lee
  • Patent number: 11088049
    Abstract: Some embodiments may include a porous silicon carbide substrate plugged with dielectric material, the porous silicon carbide substrate including a first side to couple to a heat source and a second side to couple to an electrically conductive surface, wherein the second side is opposite the first side; wherein in the case that an opening on the area of the first side forms a channel with an opening on an area of the second side, a portion of the dielectric material located in the channel is arranged to prevent an electrical short from forming through the porous silicon carbide substrate to the electrically conductive surface. In some examples, the heat source may be one or more semiconductor laser diode chips. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: August 10, 2021
    Assignee: NLIGHT INC.
    Inventor: Travis Arthur Abshere
  • Patent number: 11056418
    Abstract: A stacked semiconductor microcooler includes a first and second semiconductor microcooler. Each microcooler includes silicon fins extending from a silicon substrate. A metal layer may be formed upon the fins. The microcoolers may be positioned such that the fins of each microcooler are aligned. One or more microcoolers may be thermally connected to a surface of a coolant conduit that is thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the conduit and heat from the one or more microcoolers may transfer to the liquid coolant.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Donald F. Canaperi, Daniel A. Corliss, Dario Goldfarb, Dinesh Gupta, Fee Li Lie, Kamal K. Sikka
  • Patent number: 11049789
    Abstract: A stacked semiconductor microcooler includes a first microcooler and a second microcooler. The microcoolers may be positioned such that the fins of each microcooler are vertically aligned. The microcoolers may include an inlet passage to accept coolant and an outlet passage to expel the coolant. One or more microcoolers may be thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the passages and heat from the one or more microcoolers may transfer to the liquid coolant.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Donald F. Canaperi, Daniel A. Corliss, Dario Goldfarb, Dinesh Gupta, Fee Li Lie, Kamal K. Sikka
  • Patent number: 11049786
    Abstract: The semiconductor device includes a wiring substrate, a first and second semiconductor chips, and the heat sink. The wiring substrate has a first surface. The first and second semiconductor chips are disposed on the first surface. The heat sink is disposed on the first surface so as to cover the first semiconductor chip. The heat sink has a second surface and the third surface opposite the first surface. The second surface faces the first surface. The heat sink has a first cut-out portion. The first cut-out portion is formed at a position overlapping with the second semiconductor chip in plan view, and penetrates the heat sink in a direction from the third surface toward the second surface. The second surface is joined to at least four corners of the first surface.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: June 29, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keita Tsuchiya, Shuuichi Kariyazaki, Takashi Kikuchi, Michiaki Sugiyama, Yusuke Tanuma
  • Patent number: 11049793
    Abstract: A heat sink having a flexible heat sink base is disclosed in order to flex the heat sink into contact with concave heat sources. Flexibility is achieved by providing a series of concentric grooves on the heat sink base on a surface opposite the surface contacting the heat source. A central cylinder is provided at the center of the concentric grooves. A biasing device, such as a spring, exerts a force on the central cylinder to flex the heat sink base.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: June 29, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Yu-Nien Huang, Kuen-Hsien Wu, Shih-I Liang
  • Patent number: 11024571
    Abstract: A coil built-in multilayer substrate includes a multilayer substrate, a coil, interlayer connection conductors, and gaps. The multilayer substrate includes a magnetic layer, a component-mounting land conductor provided on a first principal surface, and a terminal conductor provided on a second principal surface. The coil is provided in the magnetic layer and includes an axis extending in a direction perpendicular or substantially perpendicular to the first and second principal surfaces. The interlayer connection conductors are provided in the magnetic layer in a region inside the spiral coil. Gaps penetrate lateral surfaces of the interlayer connection conductors.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: June 1, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Keito Yonemori
  • Patent number: 11024557
    Abstract: A semiconductor package structure includes a package substrate, a semiconductor die, a vapor chamber and a heat dissipating device. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is electrically connected to the first surface of the package substrate. The vapor chamber is thermally connected to a first surface of the semiconductor die. The vapor chamber defines an enclosed chamber for accommodating a first working liquid. The heat dissipating device is thermally connected to the vapor chamber. The heat dissipating device defines a substantially enclosed space for accommodating a second working liquid.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: June 1, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsin-En Chen, Ian Hu, Jin-Feng Yang
  • Patent number: 10991639
    Abstract: A compliant pin fin heat sink includes a flexible base plate having a thickness of from about 0.2 mm to about 0.5 mm. A plurality of pins extends from the flexible base plate and is formed integral with the flexible base plate by forging. A flexible top plate is connected to and spaced from the flexible base plate. The plurality of pins is disposed between the flexible base plate and the flexible top plate.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: April 27, 2021
    Assignee: International Business Machines Corporation
    Inventor: Mark D. Schultz
  • Patent number: 10976507
    Abstract: An optical module using an optical assembly for optical transmission and reception is disclosed. At least one embodiment of the present disclosure provides an optical module which can improve the productivity by enabling efficient optical alignment and optical coupling between optical devices and optical fibers in an optical transmission-reception module using a plurality of optical fibers while increasing the data transfer rate per unit module.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: April 13, 2021
    Inventors: Taeyong Kim, Yong Geon Lee, Yung Sung Son
  • Patent number: 10973114
    Abstract: Indium-based interface systems, structures, and methods for forming the same are provided. The disclosed indium-based interfaces may be formed as solid structures between two solid surfaces by providing a solid indium-based material between the two surfaces, and heating the indium-based material above its melting point while in contact with each of the two surfaces to cause the indium-based material to reflow or otherwise liquefy between the two surfaces. The indium-based material may then be cooled below its melting point to form a solid interface material structure that is positioned between and in contact with each of the surfaces.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: April 6, 2021
    Assignee: L3 Technologies, Inc.
    Inventors: Matthew J. Spitzner, Fernando Ortiz
  • Patent number: 10964618
    Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip attached to an upper surface of the first semiconductor chip, a silicon heat-dissipation body thermally connected to at least one of the first semiconductor chip and the second semiconductor chip, and a molding member configured to surround the first semiconductor chip and the second semiconductor chip and exposing an upper surface of the silicon heat-dissipation body.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jang-woo Lee, Kyung-suk Oh, Yung-cheol Kong, Woo-hyun Park, Jong-bo Shim, Jae-myeong Cha
  • Patent number: 10964677
    Abstract: A semiconductor package apparatus includes a passive device that is embedded in a bottom package stiffener, and a top stiffener is stacked above the bottom package stiffener. Electrical connection through the passive device is accomplished through the stiffeners to a semiconductor die that is seated upon an infield region of the semiconductor package substrate.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Jenny Shio Yin Ong, Bok Eng Cheah, Jackson Chung Peng Kong, Seok Ling Lim, Kooi Chi Ooi
  • Patent number: 10959357
    Abstract: A circuit block assembly is provided that includes circuit blocks that each include a circuit board and a semiconductor element that is disposed on a first main surface of the circuit board. Moreover, each of the circuit blocks includes a metal heat spreader that is connected to the semiconductor element directly or by a thermally conductive member interposed therebetween. A thermally conductive sheet is provided that is thermally connected to the heat spreader. The thermally conductive sheet has a specific electrical resistance higher than a specific electrical resistance of the heat spreader.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: March 23, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takeaki Tamayama, Akihiro Motoki
  • Patent number: 10950521
    Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Ok Na, Jongkook Kim, Hyo-Chang Ryu, Jin-woo Park, BongJin Son, Jangwoo Lee
  • Patent number: 10890931
    Abstract: A method is disclosed for implementing a scheme to configure thermal management control for a memory device resident on a memory module for a computing platform. A method is also disclosed for implementing the configured thermal management control. In a run-time environment for a computing platform a temperature is obtained from a thermal sensor monitoring the memory module. The memory module is in a given memory module with thermal sensor configuration that includes the memory device. An approximation of a temperature for the memory device is made based on thermal information associated with the given configuration of the memory module and the obtained temperature. The configured thermal management control for the memory device is implemented based on the approximated temperature. Other implementations and examples are also described in this disclosure.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: January 12, 2021
    Assignee: INTEL CORPORATION
    Inventors: Ishmael Santos, Corinne Hall, Christopher Cox
  • Patent number: 10879222
    Abstract: Provided is a power chip integration module including: a first semiconductor chip; a second semiconductor chip; a wiring layer on an upper surface or a lower surface of the first semiconductor chip and the second semiconductor chip to electrically connect the first semiconductor chip and the second semiconductor chip; an internal electrode extending from an internal electrode pad on an upper surface of at least one of the wiring layer, the first semiconductor chip, the second semiconductor chip, and combinations thereof to an external solder pad formed on an installation surface of the first semiconductor chip and the second semiconductor chip; and a first molding member in a shape to surround at least a portion of the first semiconductor chip, the second semiconductor chip, and the internal electrode.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: December 29, 2020
    Assignee: HYUNDAI AUTRON CO., LTD.
    Inventor: Han Sin Cho
  • Patent number: 10847469
    Abstract: A microelectronic structure having CTE compensation for use in wafer-level and chip-scale packages, comprising a plurality of substrate tiles each having a generally planar upper surface, the upper surfaces of the tiles disposed within a common plane to provide a generally planar grid of the tiles, each respective pair of adjacent tiles having a gap disposed therebetween.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: November 24, 2020
    Assignee: CUBIC CORPORATION
    Inventors: Kenneth J. Vanhille, Aaron C. Caba, Masud Beroz, Jared W. Jordan, Timothy A. Smith, Anatoliy O. Boryssenko, Steven E. Huettner
  • Patent number: 10849217
    Abstract: An electrical-circuit assembly includes an electrical-device and a heat-sink. The heat-sink has a base having a first-surface and a second-surface. The first-surface is in thermal communication with the electrical-device. The heat sink also has a lid having a third-surface and a fourth-surface. The third-surface faces toward the second-surface. The heat sink also has side-walls disposed between the base and the lid extending from the second-surface to the third-surface. The base, the lid, and the side-walls define a cavity. The heat sink also has a porous-structure extending from the second-surface toward the third-surface terminating a portion of the distance between the second-surface and the third-surface thereby defining a void between the porous-structure and the third-surface. The base, the side-walls, and the porous-structure are integrally formed of a common material. The porous-structure is characterized as having a contiguous-porosity network.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: November 24, 2020
    Assignee: Aptiv Technologies Limited
    Inventors: Scott D. Brandenburg, Manuel R. Fairchild, Paul R. Martindale
  • Patent number: 10840227
    Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chi-Hui Lai, Ban-Li Wu, Ying-Cheng Tseng, Ting-Ting Kuo, Chih-Hsuan Tai, Hao-Yi Tsai, Chuei-Tang Wang, Chung-Shi Liu, Chen-Hua Yu, Chiahung Liu
  • Patent number: 10842014
    Abstract: A memory heat dissipation unit is disclosed. The memory heat dissipation unit includes a main body having a first portion, a second portion and a connection portion having two lateral edges separately connected to the first and the second portion. The first and the second portion have at least one first heat-receiving section and at least one second heat-receiving section formed thereon, respectively; and the first and the second heat-receiving section are correspondingly in contact with at least one memory chip each to exchange heat with the chips and accordingly cool the same.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: November 17, 2020
    Inventor: Tung-Yi Wu
  • Patent number: 10791630
    Abstract: A printed circuit board having conductor tracks formed on one side of a substrate. The substrate is able to be cohesively bonded at a contact face to a cover for protecting the conductor tracks. In this case, the substrate includes a step, which forms a barrier with respect to an auxiliary material for promoting the cohesive bond, in order to prevent any wetting of the conductor tracks with the auxiliary material. A sensor having a printed circuit board for use in a fuel filling level measurement system of a vehicle.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 29, 2020
    Assignee: Vitesco Technologies GmbH
    Inventors: Erich Mattmann, Robert Peter, Waldemar Brinkis, Martin Maasz, Burkhard Dasbach
  • Patent number: 10784181
    Abstract: An apparatus includes a circuit device, a heat sink fin, and a thermal interface material layer. The thermal interface material layer is thermally coupled to the circuit device and the heat sink fin. The thermal interface material layer includes a first alloy layer, a nanometal particle layer, and a second alloy layer. The first alloy layer is thermally coupled to the circuit device. The nanometal particle layer is thermally coupled to the first alloy layer. The nanometal particle layer includes nanometal particles and an intermediate mixture.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: September 22, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: HuiLi Fu, Jyh Rong Lin, Shujie Cai
  • Patent number: 10784227
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a semiconductor package. The method may be performed by attaching a first thermal conductivity layer to an upper surface of a first chip, and attaching a second thermal conductivity layer to an upper surface of a second chip. A first support substrate is attached to lower surfaces of the first chip and the second chip. A molding compound is formed over the first support substrate and laterally surrounds the first chip and the second chip. The first support substrate is replaced with a package substrate after forming the molding compound over the first support substrate.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Tseng, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 10779444
    Abstract: A control box includes a housing defining an interior, a circuit board disposed within the interior, and an input/output connector extending from the housing. The control box further includes a heat sink removably connected to the housing such that the circuit board is positioned between the housing and the heat sink. The circuit board is in contact with the heat sink.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: September 15, 2020
    Assignee: GE Aviation Systems LLC
    Inventors: Randall Lee Neuman, Stefano Angelo Mario Lassini, Jason Eggiman
  • Patent number: 10727153
    Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: July 28, 2020
    Assignee: NXP USA, Inc.
    Inventors: Lakshminarayan Viswanathan, Jaynal A Molla
  • Patent number: 10714406
    Abstract: The module (PM1) has an architecture with 3D stacking of the electronic power switching chips (IT, ID) and comprises first and second dielectric substrates (SH, SL) that are intended to come into thermal contact with first and second heat sinks (DH, DL), respectively, at least one pair of first and second stacked electronic power switching chips (ITHS, IDHS; ITHS, IDHS) and a common intermediate substrate (SC), the first and second electronic power switching chips being sandwiched between the first dielectric substrate and the common intermediate substrate and between the common intermediate substrate and the second dielectric substrate, respectively. According to the invention, the common intermediate substrate is a metal element formed as a single piece and comprises a central portion for the implantation of the electronic power switching chips and at least one.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 14, 2020
    Assignee: INSTITUT VEDECOM
    Inventors: Hadi Alawieh, Menouar Ameziani
  • Patent number: 10670819
    Abstract: A non-plated region is formed in a certain range from an end of a submount. The non-plated region is a portion where a plating layer is not provided, and thus a substrate of the submount is exposed. An intermediate layer is formed on the plating layer. Furthermore, a plating layer is formed on the intermediate layer. A semiconductor laser is formed on the plating layer. The position of an end of the semiconductor laser substantially coincides with the position of an end of the plating layer (the intermediate layer). That is, even in a case where there is a deviation between an end face of the intermediate layer and an end face of the semiconductor laser, the amount of this deviation is sufficiently smaller than the amount by which the intermediate layer is set back from an end face of the submount.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: June 2, 2020
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Masakazu Miura, Jun Miyokawa, Kazuki Yamaoka, Hajime Mori
  • Patent number: 10624240
    Abstract: An example device in accordance with an aspect of the present disclosure includes a first shield to provide thermal isolation between a first component and a heatsink of a second component, and to provide a cooling channel that is thermally isolated from the heatsink to receive an airflow for the first component. A second shield is to provide thermal isolation between the first shield and the heatsink, and to provide a thermal barrier region between the first shield and the second shield.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: April 14, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kevin Leigh, John Norton, George D. Megason
  • Patent number: 10600753
    Abstract: A semiconductor device includes an integrated circuit attached to a chip carrier in a flip chip configuration. A substrate extends to a back surface of the integrated circuit, and an interconnect region extends to a front surface of the integrated circuit. A substrate bond pad is disposed at the front surface, and is electrically coupled through the interconnect region to the semiconductor material. The chip carrier includes a substrate lead at a front surface of the chip carrier. The substrate lead is electrically coupled to the substrate bond pad. An electrically conductive compression sheet is disposed on the back surface of the integrated circuit, with lower compression tips making electrical contact with the semiconductor material in the substrate. The electrically conductive compression sheet is electrically coupled to the substrate lead of the chip carrier by a back surface shunt disposed outside of the integrated circuit.
    Type: Grant
    Filed: August 28, 2016
    Date of Patent: March 24, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: James Fred Salzman
  • Patent number: 10600774
    Abstract: An integrated circuit (IC) is fabricated with transistors and gated diodes having selected epitaxial growth. The transistors may be Field-Effect Transistors (FETs) for example, and more specifically, may be fin-based FETs (finFETs) where fins are fabricated, in part, using an epitaxial growth process. The IC is further fabricated with gated diodes. Selected gated diodes within the IC are fabricated using the epitaxial growth process on the fins of the gated diode to form an anode and a cathode. Other selected gated diodes are fabricated without using epitaxial growth processes to form the anode and the cathode. In still another aspect, selected gated diodes are fabricated with epitaxial growth processes on either the anode or the cathode, but not both. In an exemplary aspect, the other selected gated diodes are part of electrostatic discharge (ESD) protection circuits in an input/output (I/O) region of the IC.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: March 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Youn Sung Choi, Youseok Suh, Kwanyong Lim
  • Patent number: 10586760
    Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in the casing, and for forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The outer sidewalls of the upper portion of the casing are located between vertical planes defined by opposing outer sidewalls of the lower portion of the casing.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kerry Bernstein, Thomas Brunschwiler, Bruno Michel
  • Patent number: 10586779
    Abstract: Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400° C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, James C. Matayabas, Jr., Akshay Mathkar
  • Patent number: 10546798
    Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: January 28, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino Tolentino, Vernal Raja Manikam, Azhar Aripin
  • Patent number: 10504817
    Abstract: Provided is a technique for improving product attachment. In a semiconductor device, the following expression is satisfied by an angle A formed by an imaginary line connecting two attachment holes together and an imaginary line connecting together a lowest point of one of two projections positioned in a surrounding portion of one of the two attachment holes and a contact point between a bulge and a heat sink, with a screw fastened to the heat sink through the one attachment hole, where M represents a vertical direction between the lower end of a body and the lower end of a case, where W represents a bulge amount of the bulge, where T represents a height of the projection, where L represents a horizontal distance from the outer peripheral end of the case to the outer peripheral end of the heat dissipation plate: 0<A<arctan((M+W?T)/L).
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 10, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuya Okada, Hiroki Muraoka, Koichi Masuda, Yasutaka Shimizu, Shoji Izumi
  • Patent number: 10499500
    Abstract: A metal pallet is integrated within a circuit board using a process similar to a multilayer PCB, which integrates the metal pallet into the circuit board at the same time as the supporting layers are fabricated. The use of B-stage material provides a bonding mechanism for the metal pallet to be embedded within the circuit board, creating a cohesive integrated part. Embedding the pallet during the fabrication process, pre-lamination, generates a more robust construction and connection not impacted by post fabrication process in assembly. After assembly the circuit board with embedded metal pallet can be mounted directly on a heat sink, cool ribbon or other feature required to help remove heat. The planar back side surface provides a more robust mounting of the metal pallet than a post fabricated assembly as used in conventional techniques.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: December 3, 2019
    Assignee: Flex Ltd.
    Inventors: J H Berkel, Todd Robinson, Joan K. Vrtis
  • Patent number: 10468332
    Abstract: Provided is a cooler including an upper plate configured to have a semiconductor chip to be arranged thereon, a plurality of plate-like fins arranged under the upper plate, and a coupling bar coupled to the plate-like fins. The coupling bar has a main-body portion and a plurality of comb-tooth portions protruding from the main-body portion into the flow channel, the cooler includes a plurality of openings in a plane orthogonal to an extending direction of the plate-like fins, and the openings are defined at least by the comb-tooth portions and the plate-like fins, and the openings include a first opening provided in a first flow channel that does not run below the semiconductor chip, and a second opening provided in a second flow channel that runs below the semiconductor chip, where the second opening is larger than the first opening.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: November 5, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Toru Yamada
  • Patent number: 10438930
    Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, Christopher L. Rumer, Nitin Deshpande, Robert M. Nickerson
  • Patent number: 10433414
    Abstract: A method of manufacturing a printed circuit board includes providing a substrate having at least one resin plate and a semi-cured sheet. A through hole is formed in the substrate to accommodate a radiator having an electrically conductive layer and an electrically insulated layer. The substrate and radiator are heat pressed to fully cure the epoxy and couple the substrate and radiator together. The excess resin is removed and electrically conductive layers are plated on the board. Surface circuits and a heat dissipating pattern are then etched into the conductive layer. An LED is attached to the printed circuit board. In some embodiments, a flexible segment is formed by removing a portion of the substrate. The radiator can have an electrically insulated layer extending at least partially across a surface of an electrically insulated and thermally conductive core.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: October 1, 2019
    Assignee: Rayben Technologies (HK) Limited
    Inventors: Kai Chiu Wu, Lam Wai Kin Raymond, Zheng Wang
  • Patent number: 10433463
    Abstract: Embodiments herein relate to a heat sink having nano- and/or micro-replication directly embossed in a bulk solidifying amorphous alloy comprising a metal alloy, wherein the heat sink is configured to transfer heat out of the heat sink by natural convection by air or forced convection by air, or by fluid phase change of a fluid and/or liquid cooling by a liquid. Other embodiments relate apparatus having the heat sink. Yet other embodiments relate to methods of manufacturing the heat sink and apparatus having the heat sink.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: October 1, 2019
    Assignees: Crucible Intellectual Property, LLC, Apple Inc.
    Inventors: Christopher D. Prest, Joseph Poole, Joseph W. Stevick, Quoc Tran Pham, Theodore Andrew Waniuk
  • Patent number: 10418309
    Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a substrate, a first die, a gasket, and a thermal interface. The first die may be connected to the substrate. The gasket may be connected to the substrate and may encircle the first die to form a space between the first die and the gasket. The thermal interface material may be located within the space formed by the first die and the gasket.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Bijoyraj Sahu, Thomas A. Boyd, Jeffory L. Smalley
  • Patent number: 10411042
    Abstract: Disclosed is a display device including: a substrate including a display area for displaying an image and a peripheral area neighboring the display area; a plurality of signal lines formed in the display area; a pad formed in the peripheral area; and a plurality of connection wires for connecting the signal lines and the pad, wherein a first connection wire and a second connection wire neighboring the first connection wire from among the plurality of connection wires are disposed on different layers, and the first connection wire and the second connection wire, which are formed to extend from the pad and are bent at least twice to have at least one being bent toward backward direction, are disposed in the peripheral area.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung-Kyu Lee, Tae Hoon Kwon, Ji-Hyun Ka
  • Patent number: 10332899
    Abstract: An IC package, comprising a substrate and two or more vertically stacked dies disposed within the substrate, wherein all the edges of the two or more dies are aligned with respect to one another, wherein at least two dies of the two or more vertically stacked dies are coupled directly to one another by at least one wire bonded to the ones of the at least two dies.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Yi Xu, Florence Pon, Yong She
  • Patent number: 10319660
    Abstract: A heat transportation mechanism that is thermally conductive, but not electrically conductive, is provided so as to permit transportation of heat generated by a semiconductor device die to the exterior of a semiconductor device package. Embodiments can use a thermally conductive polymer structure, added to the package mold compound, to transport heat through the mold compound. The thermally conductive polymer structure can be fixed to the semiconductor device die prior to molding or can be included in an overmolding compound slug prior to performing the overmolding process. Flexibility of placement of the thermally conductive polymer structure is provided by using dielectric compounds.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: June 11, 2019
    Assignee: NXP USA, INC.
    Inventor: Christopher W. Argento
  • Patent number: 10321569
    Abstract: Electronic module with all-sided electromagnetic interference (EMI) shielding and methods of making same. The electronic module includes an encapsulated circuit board between a top plate and a conductive bottom plate, electrical leads extending from the circuit board through the bottom plate, and a continuous conductive coating substantially covering the entire electronic module except for a bottom surface of the bottom plate. The conductive coating forms direct, independent connections at least to the circuit board and the bottom plate. The conductive coating provides EMI shielding across the top and sides of the electronic module. The conductive bottom plate provides EMI shielding across the bottom of the electronic module. Methods of manufacturing include encapsulating a circuit board between a top plate and bottom plate, separating materials from the encapsulated circuit board to expose conductive traces on the circuit board and bottom plate, and coating the sawed device with a conductive coating.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: June 11, 2019
    Assignee: VPT, INC.
    Inventors: Stephen J. Butler, Anthony G. Salamone
  • Patent number: 10276549
    Abstract: A package structure and method for forming the same are provided. The package structure includes a package component, and a device die formed over the package component. The device die includes a device substrate and a conductive pad over the device substrate, and the device die has a first height. The package structure also includes a dummy die formed over the package component and adjacent to the device die, and the dummy die has a second height smaller than the first height.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Wei Chen, Li-Hsien Huang