For Integrated Circuit Patents (Class 257/713)
  • Patent number: 11915992
    Abstract: A method for forming a package structure is provided, including forming an interconnect structure over a carrier substrate and forming a semiconductor die over a first side of the interconnect structure. A removable film is formed over the semiconductor die. The method includes forming a first stacked die package structure over the first side of the interconnect structure. A top surface of the removable film is higher than a top surface of the first stacked die package structure. The method includes forming a package layer, removing a portion of the package layer to expose a portion of the removable film, removing the removable film to form a recess, forming a lid structure over the semiconductor die and the first stacked die package structure. The lid structure has a main portion and a protruding portion disposed in the recess and extending from the main portion.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Puu Jeng, Po-Yao Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Chin-Hua Wang
  • Patent number: 11916045
    Abstract: A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where the device includes at least one power supply circuit.
    Type: Grant
    Filed: August 21, 2023
    Date of Patent: February 27, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 11915991
    Abstract: A semiconductor device includes a substrate, a package structure, a first heat spreader, and a second heat spreader. The package structure is disposed on the substrate. The first heat spreader is disposed on the substrate. The first heat spreader surrounds the package structure. The second heat spreader is disposed on the package structure. The second heat spreader is connected to the first heat spreader. A material of the first heat spreader is different from a material of the second heat spreader.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
  • Patent number: 11908810
    Abstract: A hybrid semiconductor device includes an interposer substrate, a semiconductor package mounted on the interposer substrate, a molding member on the package substrate covering at least a portion of the semiconductor chip and exposing an upper surface of the semiconductor chip, and a stiffener disposed on an upper surface of the interposer substrate substantially around the semiconductor package.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heungkyu Kwon, Junso Pak, Heeseok Lee
  • Patent number: 11910567
    Abstract: A liquid-submersible thermal management system includes a cylindrical outer shell and an inner shell positioned in an interior volume of the outer shell. The cylindrical outer shell has a longitudinal axis oriented vertically relative to a direction of gravity, and the inner shell defines an immersion chamber. The liquid-submersible thermal management system a spine positioned inside the immersion chamber and oriented at least partially in a direction of the longitudinal axis with a heat-generating component located in the immersion chamber. A working fluid is positioned in the immersion chamber and at least partially surrounding the heat-generating component. The working fluid receives heat from the heat-generating component.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: February 20, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Husam Atallah Alissa, Ioannis Manousakis, Nicholas Andrew Keehn, Eric C. Peterson, Bharath Ramakrishnan, Christian L. Belady, Ricardo Gouvea Bianchini
  • Patent number: 11901258
    Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 11894287
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
  • Patent number: 11895769
    Abstract: A module according to the present disclosure includes a circuit board, an electronic component on one of two principal surfaces of the circuit board, a connection conductor on the principal surface of the circuit board, and sealing resin on the principal surface of the circuit board. The electronic component and the connection conductor are covered with the sealing resin. The connection conductor includes a plate-shaped conductor and terminal sections. The plate-shaped conductor is disposed upright on the principal surface of the circuit board. The terminal sections extend from the plate-shaped conductor and away from the principal surface of the circuit board and are arranged side by side. Tip portions of the terminal sections are exposed at a surface of the sealing resin.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: February 6, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuya Okamoto, Takashi Haga, Masayoshi Takagi, Kazushige Sato
  • Patent number: 11887839
    Abstract: An imaging unit comprising an imaging chip and a mounting substrate that has the imaging chip mounted thereon and includes a first metal layer for outputting a signal generated by the imaging chip to the outside. An imaging apparatus comprises an imaging unit that includes an imaging chip and a mounting substrate that has the imaging chip mounted thereon and includes a first metal layer for outputting a signal generated by the imaging chip to the outside.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: January 30, 2024
    Assignee: NIKON CORPORATION
    Inventors: Hirofumi Arima, Ryoichi Suganuma, Takuya Sato, Satoru Suzuki
  • Patent number: 11881441
    Abstract: Stacked die semiconductor packages may include a spacer die disposed between stacked dies in the semiconductor package and the semiconductor package substrate. The spacer die translates thermally induced stresses on the solder connections between the substrate and an underlying member, such as a printed circuit board, from electrical structures communicably or conductively coupling the semiconductor package substrate to the underlying structure to mechanical structures that physically couple the semiconductor package to the underlying structure. The footprint area of the spacer die is greater than the sum of the footprint areas of the individual stacked dies in the semiconductor package and less than or equal to the footprint area of the semiconductor package substrate. The spacer die may have nay physical configuration, thickness, shape, or geometry. The spacer die may have a coefficient of thermal expansion similar to that of the lowermost semiconductor die in the die stack.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 23, 2024
    Assignee: Intel Corporation
    Inventors: Sireesha Gogineni, Andrew Kim, Yong She, Karissa J. Blue
  • Patent number: 11879910
    Abstract: An integrated circuit device testing system includes a socket configured to receive an integrated circuit device, wherein the socket comprises at least one conductive trace made of a material with a resistivity that is a function of temperature, and wherein the socket is configured such that, when the integrated circuit device is located in the socket, the at least one conductive trace extends along a surface of the integrated circuit device. The integrated circuit device testing system further includes a controller or active circuit configured to determine a temperature at the surface of the integrated circuit device based on a measured resistance of the at least one conductive trace.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: January 23, 2024
    Assignee: DELTA DESIGN, INC.
    Inventor: Jerry Ihor Tustaniwskyj
  • Patent number: 11876059
    Abstract: A semiconductor device having a radiating element and a directing structure is provided. The semiconductor device includes a device package. A semiconductor die is coupled to the radiating element integrated in the device package. The directing structure is affixed to the device package by way of an adhesive. The directing structure is located over the radiating element and configured for propagation of radio frequency (RF) signals.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: January 16, 2024
    Assignee: NXP USA, INC.
    Inventors: Robert Joseph Wenzel, Michael B. Vincent
  • Patent number: 11869760
    Abstract: Power electronics device assemblies, circuit board assemblies, and power electronics assemblies are disclosed. In one embodiment, a power electronics device assembly includes an S-cell including a first metal layer, a first graphite layer bonded to the first metal layer, an electrically insulating layer bonded to the first graphite layer, a second graphite layer bonded to the electrically insulating layer and a second metal layer bonded to the second graphite layer, the second metal layer comprising a surface and a recess provided within the surface. The power electronics device assembly further includes a power electronics device disposed within the recess of the surface.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: January 9, 2024
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventors: Feng Zhou, Hiroshi Ukegawa
  • Patent number: 11868174
    Abstract: Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge. The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: January 9, 2024
    Assignee: XILINX, INC.
    Inventor: Brian C. Gaide
  • Patent number: 11864323
    Abstract: A driver board assembly includes a printed circuit board (PCB) substrate, one or more power devices embedded within the PCB substrate, and a plurality of conductive layers arranged within the PCB substrate. The plurality of conductive layers are configured to electrically couple the one or more power devices to a current source and thermally couple the one or more power devices to one or more cooling assemblies mounted to at least one of a first surface of the PCB substrate and a second surface of the PCB substrate opposite the first surface of the PCB substrate.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: January 2, 2024
    Assignees: Toyota Motor Engineering & Manufacturing North America, Inc., Toyota Jidosha Kabushiki Kaisha
    Inventors: Feng Zhou, Shohei Nagai
  • Patent number: 11855021
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, through substrate vias, conductive pillars and dummy conductive pillars. The interconnection structure is disposed at a front side of the semiconductor substrate, and comprises a stack of dielectric layers and interconnection elements spreading in the stack of dielectric layers. The through substrate vias separately penetrate through the semiconductor substrate and the stack of dielectric layers. The conductive pillars are disposed at a front side of the interconnection structure facing away from the semiconductor substrate, and respectively in electrical connection with one of the through substrate vias. The dummy conductive pillars are disposed aside the conductive pillars at the front side of the interconnection structure.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Chen-Hua Yu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 11846474
    Abstract: A cooling array for cooling of an electronic component includes the electronic component, a housing which at least partially enclosing the electronic component, a heat sink support connected to the housing in a fluid-tight manner, and a heat sink which is accommodated in the heat sink support. The heat sink is thermally coupled to the electronic component in order to disperse heat generated by the electronic component.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: December 19, 2023
    Assignee: LISA DRAEXLMAIER GMBH
    Inventors: Erwin Lichtenberg, Christian Goestl, Christian Friedrich
  • Patent number: 11848320
    Abstract: According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: December 19, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jerome Teysseyre, Inpil Yoo, JooYang Eom
  • Patent number: 11830787
    Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Aleksandar Aleksov, Johanna M. Swan
  • Patent number: 11832419
    Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Nicholas Neal, Nicholas S. Haehn, Je-Young Chang, Kyle Arrington, Aaron McCann, Edvin Cetegen, Ravindranath V. Mahajan, Robert L. Sankman, Ken P. Hackenberg, Sergio A. Chan Arguedas
  • Patent number: 11830810
    Abstract: A package includes a circuit that includes at least one active area and at least one secondary device area, a support configured to support the circuit, and a die attach material. The circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: November 28, 2023
    Assignee: WOLFSPEED, INC.
    Inventors: Mitch Flowers, Erwin Cohen, Alexander Komposch, Larry Christopher Wall
  • Patent number: 11823971
    Abstract: The disclosure relates to an electronic system including a plurality of adjacent, elementary power electronics modules and connected to one another by an electrical module connection. Each elementary module including at least one power component integrated on a printed circuit inserted between two electrically conductive heat sinks. The electrical module connection is made by heat sinks at the side and/or central connection surfaces thereof.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: November 21, 2023
    Assignee: INSTITUT POLYTECHNIQUE DE GRENOBLE
    Inventor: Yvan Avenas
  • Patent number: 11817436
    Abstract: An apparatus for a common cooling solution for multiple packages of a common height, including: a first die package; a second die package having a same height as the first die package; and a cooling element thermally coupled to the first die package and the second die package by a planar surface of the cooling element.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: November 14, 2023
    Inventor: Christopher M. Jaggers
  • Patent number: 11810876
    Abstract: An electronic assembly has a host wafer having a first circuit including passive devices for the purpose of one of tuning or matching networks. Chiplets are placed in the cavities. At least one chiplet has a second circuit including at least one transistor or switch device and passive tuning circuits including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low-noise network. Electrical interconnects between the chiplets and wafer electrically connect the first circuitry to the second circuitry.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: November 7, 2023
    Assignee: PseudolithIC, Inc.
    Inventors: James Buckwalter, Michael Hodge, Justin Kim, Florian Herrault, Daniel Green
  • Patent number: 11807381
    Abstract: A hybrid propulsion system for use with an aircraft includes a gas turbine engine, at least one propulsor, and an electric power system. The electric power system is coupled to the gas turbine engine to generate electrical energy and the propulsor to provide electrical energy to drive the propulsor. The electric power system includes a thermal management system configured to cool a heat load generated by the electric power system.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: November 7, 2023
    Assignee: Rolls-Royce Corporation
    Inventors: Krishnamoorthi Sivalingam, Chandana J. Gajanayake, Jeyaraman Kumaravel, Palanisamy Mohan Kumar, Govind Pandey, Yunzhe Zhai, Divya Bharathi Perumal
  • Patent number: 11805621
    Abstract: A memory auxiliary heat transfer structure is correspondingly assembled with at least one memory unit and a water-cooling assembly. The memory auxiliary heat transfer structure includes a main body. The main body has a first end, a second end and a middle section. The middle section has a heated side and a contact side. The heated side is disposed corresponding to at least one chip disposed on the memory unit. The contact side is attached to and assembled with the water-cooling assembly. The memory auxiliary heat transfer structure serves to reduce the friction between the memory unit and the water-cooling assembly and fill the gap so as to reduce the heat resistance.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: October 31, 2023
    Assignee: ASIA VITAL COMPONENTS (CHINA) CO., LTD.
    Inventor: Sung-Wei Lee
  • Patent number: 11800632
    Abstract: According to various embodiments, an electronic device may include a first plate, a second plate facing away from the first plate, and a side member surrounding a space between the first plate and the second plate, a middle plate disposed in the space between the first plate and the second plate in parallel with the second plate, a first Printed Circuit Board (PCB) disposed in a space between the second plate and the middle plate, a first electronic component mounted on the first PCB between the first PCB and the middle plate, a first heat transfer structure disposed between the first electronic component and the middle plate, a second electronic component including a first surface disposed in the space and spaced apart from the first PCB, a second surface facing away from the first surface, and a side face substantially perpendicular to the first surface or the second surface, and a second heat transfer structure.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: October 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yonghwa Kim, Min Park, Dongil Son, Hyunwoo Sim, Jaedeok Lim, Chunghyo Jung, Seungbum Choi
  • Patent number: 11791234
    Abstract: A semiconductor device includes a substrate that has a first surface and a second surface on which a plurality of solder balls are provided, a semiconductor memory on the first surface of the substrate, a controller arranged on the first surface of the substrate, separated from the semiconductor memory along a first direction, and configured to control the semiconductor memory, a graphite sheet extending along the first direction above the controller and the semiconductor memory, and a first sealing material that seals the semiconductor memory, the controller, and the graphite sheet.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: October 17, 2023
    Assignee: Kioxia Corporation
    Inventors: Ryo Kamoda, Hideki Takahashi
  • Patent number: 11785764
    Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Kunal R. Parekh, Terrence B. McDaniel, Beau D. Barry
  • Patent number: 11774180
    Abstract: A heat pipe including a pipe body. The pipe body has an evaporation portion and a condensation portion. The condensation portion is connected to the evaporation portion. The condensation portion includes a condensation end. The evaporation portion includes an evaporation end. The evaporation end and/or the condensation end are/is in a rectangular shape.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: October 3, 2023
    Assignee: VAST GLORY ELECTRONICS & HARDWARE & PLASTIC(HUI ZHOU) LTD.
    Inventors: Xue Mei Wang, Lei Lei Liu
  • Patent number: 11756852
    Abstract: A semiconductor device including a substrate, a semiconductor package, a plurality of pillars and a lid is provided. The semiconductor package is disposed on the substrate and includes at least one semiconductor die. The plurality of pillars are disposed on the semiconductor package. The lid is disposed on the substrate and covers the semiconductor package and the plurality of pillars. The lid includes an inflow channel and an outflow channel to allow a coolant to flow into and out of a space between the substrate, the semiconductor package, the plurality of pillars and the lid. An inner surface of the lid, which faces and overlaps the plurality of pillars along a stacking direction of the semiconductor package and the lid, is a flat surface.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Jeng-Nan Hung, Kuo-Chung Yee, Po-Fan Lin
  • Patent number: 11754343
    Abstract: Embodiments of the disclosure relate to an electronic assembly including a substrate having a first surface and a second surface opposite to the first surface and one or more electronic devices bonded to the first surface of the substrate. A first heat-storing region is embedded within the substrate and proximate to the second surface. The first heat-storing region comprises a phase change material encapsulated by an encapsulating layer. A melting temperature of the encapsulating layer is higher than a melting temperature of the phase change material and a maximum operating temperature of the one or more electronic devices. A heat transfer layer is embedded within the substrate and thermally connects the first heat-storing region to the one or more electronic devices.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: September 12, 2023
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Shailesh N. Joshi, Ercan M. Dede
  • Patent number: 11758690
    Abstract: A heat-dissipation device with detachability against the adhesion of a paste includes a heat-dissipation structure and a detachment device. The heat-dissipation structure installed on a heat-generating component includes a base, and a heat-dissipation element disposed on the base, and a through hole penetrating through the base. The detachment device includes a housing disposed on the base and covering the through hole, wherein the housing includes a gas chamber, and a gas hole connected to the gas chamber, the gas hole being in communication with the through hole. An adjustment element is movably disposed in the gas chamber. A gas in the housing is pushed out through the gas hole by moving the adjustment element downwards, creating a positive gas pressure and thus forcing a separation between the heat-dissipation structure and the heat-generating component on which the structure is installed.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: September 12, 2023
    Assignee: Nanning FuLian FuGui Precision Industrial Co., Ltd.
    Inventor: Chih-Yu Yeh
  • Patent number: 11749584
    Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hsiang Huang, Chin-Chou Liu, Chin-Her Chien, Fong-yuan Chang, Hui Yu Lee
  • Patent number: 11735548
    Abstract: Electronic assemblies may be fabricated with interconnects of different types present in multiple locations and comprising fused copper nanoparticles. Each interconnect or a portion thereof comprises a bulk copper matrix formed from fusion of copper nanoparticles or a reaction product formed from copper nanoparticles. The interconnects may comprise a copper-based wire bonding assembly, a copper-based flip chip connection, a copper-based hermetic seal assembly, a copper-based connector between an IC substrate and a package substrate, a copper-based component interconnect, a copper-based interconnect comprising via copper for establishing electrical communication between opposite faces of a package substrate, a copper-based interconnect defining a heat channel formed from via copper, and any combination thereof.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: August 22, 2023
    Assignee: Kuprion Inc.
    Inventor: Alfred A. Zinn
  • Patent number: 11735434
    Abstract: A method is provided for producing an insulating circuit substrate with a heat sink including an insulating circuit substrate and a heat sink, the insulating circuit substrate including a circuit layer and a metal layer that are formed on an insulating layer, and the heat sink being bonded to the metal layer side. The method includes: an aluminum bonding layer forming step of forming an aluminum bonding layer formed of aluminum or an aluminum alloy having a solidus temperature of 650° C. or lower on the metal layer; and a heat sink bonding step of laminating a copper bonding material formed of copper or a copper alloy between the aluminum bonding layer and the heat sink and bonding the aluminum bonding layer, the copper bonding material, and the heat sink to each other by solid phase diffusion bonding.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: August 22, 2023
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Ryouhei Yumoto, Tomoya Oohiraki, Takeshi Kitahara, Yoshiyuki Nagatomo
  • Patent number: 11737237
    Abstract: A liquid cooling arrangement for peripheral board incorporates cooling plates on one side and resilient cushion on the opposite side and enclosing the peripheral board between the cooling plates and the cushion. The cushion exerts pressure on the backside of the peripheral board to ensure physical contact of the microchips and the cooling plates for good thermal conductance. Cooling hoses are connected to the cooling plates to circulate cooling liquid. An electrically insulating layer may be included between the backside of the peripheral board and the cushion. An extension frame may optionally be added onto the cooling frame to house the cooling houses and increase the variability of deployments.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: August 22, 2023
    Assignee: BAIDU USA LLC
    Inventor: Tianyi Gao
  • Patent number: 11728237
    Abstract: The semiconductor device includes a supporting member, a conductive member, and a semiconductor element. The supporting member has a supporting surface facing in a thickness direction. The conductive member has an obverse surface facing the same side as the supporting surface faces in the thickness direction, and a reverse surface opposite to the obverse surface. The conductive member is bonded to the supporting member such that the reverse surface faces the supporting surface. The semiconductor element is bonded to the obverse surface. The semiconductor device further includes a first metal layer and a second metal layer. The first metal layer covers at least a part of the supporting surface. The second metal layer covers the reverse surface. The first metal layer and the second layer are bonded to each other by solid phase diffusion.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 15, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Xiaopeng Wu
  • Patent number: 11728909
    Abstract: Described are methods and apparatuses pertaining to stacked integrated circuits having application in ultra-low-power and small form factor design, with fast prototyping and mass-production cycle time, including application for millimeter wave radio frequency circuits.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: August 15, 2023
    Assignee: Shenzhen Chipuller Chip Technology Co., LTD
    Inventors: Jawad Nasrullah, Omar Alnaggar, Hanfeng Wang, Mohamed Sameh Mahmoud
  • Patent number: 11710674
    Abstract: Various embodiments disclosed relate to a substrate for a semiconductor device. The substrate includes a first major surface and a second major surface opposite the first major surface. The substrate further includes a cavity defined by a portion of the first major surface. The cavity includes a bottom dielectric surface and a plurality of sidewalls extending from the bottom surface to the first major surface. A first portion of a first sidewall includes a conductive material.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: July 25, 2023
    Assignee: Intel Corporation
    Inventors: Yi Elyn Xu, Bilal Khalaf, Dennis Sean Carr
  • Patent number: 11705413
    Abstract: A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: July 18, 2023
    Assignee: MEDIATEK INC.
    Inventors: Chia-Hao Hsu, Tai-Yu Chen, Shiann-Tsong Tsai, Hsing-Chih Liu, Yao-Pang Hsu, Chi-Yuan Chen, Chung-Fa Lee
  • Patent number: 11705417
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an interface layer over the first dies, a backside metallization (BSM) layer directly on the interface layer, where the BSM layer includes first, second, and third conductive layer, and a heat spreader over the BSM layer. The first conductive layer includes a titanium material. The second conductive layer includes a nickel-vanadium material. The third conductive layer includes a gold material, a silver material, or a copper material. The copper material may include copper bumps. The semiconductor package may include a plurality of second dies on a package substrate. The substrate may be on the package substrate. The second dies may have top surfaces substantially coplanar to top surface of the first dies. The BSM and interface layers may be respectively over the first and second dies.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Chandra Mohan Jha, Prasad Ramanathan, Xavier F. Brun, Jimmin Yao, Mark Allen
  • Patent number: 11705408
    Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Jung-Wei Cheng, Yu-Min Liang, Jiun-Yi Wu, Yen-Fu Su, Chien-Chang Lin, Hsin-Yu Pan
  • Patent number: 11699642
    Abstract: A semiconductor package is provided. The semiconductor package includes a redistribution layer, a semiconductor chip, solder balls, an interposer, an encapsulant layer, and an underfill layer. The semiconductor chip is electrically connected to the redistribution layer, and disposed on an upper surface of the redistribution layer. The solder balls are disposed on the upper surface of the redistribution layer spaced apart from the semiconductor chip and are electrically connected to the redistribution layer. The interposer is electrically connected to the solder balls, and is disposed on an upper surface of the solder balls. The encapsulant layer encapsulates the semiconductor chip and side surfaces of the redistribution layer under the interposer. The underfill layer fills a space between a lower surface of the interposer and an upper surface of the encapsulant layer. The encapsulant layer includes a side surface encapsulant region surrounding the side surfaces of the redistribution layer.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: July 11, 2023
    Assignee: SAMSUNG ELECTRONIC CO., LTD.
    Inventor: Dongho Kim
  • Patent number: 11694997
    Abstract: In some embodiments, the present disclosure relates to method of forming an integrated circuit, including forming a semiconductor device on a frontside of a semiconductor substrate; depositing a dielectric layer over a backside of the semiconductor substrate; patterning the dielectric layer to form a first opening in the dielectric layer so that the first opening exposes a surface of the backside of the semiconductor substrate; depositing a glue layer having a first thickness over the first opening; filling the first opening with a first material to form a backside contact that is separated from the semiconductor substrate by the glue layer; and depositing more dielectric layers, bonding contacts, and bonding wire layers over the dielectric layer to form a second bonding structure on the backside of the semiconductor substrate, so that the backside contact is coupled to the bonding contacts and the bonding wire layers.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: July 4, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Tzu Chen, Hsing-Chih Lin, Min-Feng Kao
  • Patent number: 11688697
    Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: June 27, 2023
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Dong Won Son, Byeonghoon Kim, Sung Ho Choi, Sung Jae Lim, Jong Ho Shin, SungWon Cho, ChangOh Kim, KyoungHee Park
  • Patent number: 11684400
    Abstract: A first module configured to engage with a second module in a stacked configuration to define a modular energy system is provided. The first module comprises a first bridge connector portion and a second conductive portion. The first bridge connector portion is configured to engage with a second bridge connector portion of the second module as the first module and the second module are engaged. The first conductive portion is configured to engage with a second conductive portion of the second module as the first module and the second module are engaged, prior to engagement between the first bridge connector portion and the second bridge connector portion.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: June 27, 2023
    Assignee: Cilag GmbH International
    Inventors: Madeleine C. Jayme, Kristen G. Denzinger, Joshua Henderson, Ryan M. Asher, William B. Weisenburgh, II, Amrita S. Sawhney
  • Patent number: 11682614
    Abstract: A semiconductor package includes a semiconductor chip and a package substrate. The semiconductor chip is mounted on the package substrate. The package substrate includes a dielectric layer through which a vent hole penetrates, trace patterns disposed on the dielectric layer, and a protecting block disposed between the trace patterns and the vent hole.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: June 20, 2023
    Assignee: SK hynix Inc.
    Inventors: Hyun Chul Seo, Jun Sik Kim
  • Patent number: 11676873
    Abstract: Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 13, 2023
    Assignee: Intel Corporation
    Inventors: Dinesh Padmanabhan Ramalekshmi Thanu, Hemanth K. Dhavaleswarapu, Venkata Suresh Guthikonda, John J. Beatty, Yonghao An, Marco Aurelio Cartas Ayala, Luke J. Garner, Peng Li
  • Patent number: 11676879
    Abstract: A semiconductor package includes: a carrier having a first side and a second side opposite the first side, the first side having a plurality of contact structures; a semiconductor die having a first side and a second side opposite the first side, the first side of the semiconductor die having a plurality of pads attached to the plurality of contact structures at the first side of the carrier; a metal plate attached to the second side of the semiconductor die, the metal plate having a size that is independent of the size of the carrier and based on an expected thermal load to be presented by the semiconductor die; and an encapsulant confined by the carrier and the metal plate and laterally surrounding an edge of the semiconductor die. Corresponding methods of production are also provided.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: June 13, 2023
    Assignee: Infineon Technologies AG
    Inventors: Stefan Woetzel, Chee Yang Ng