Abstract: A semiconductor device includes: a semiconductor element; a sealing resin; a gate terminal; a drain terminal; a source terminal; a heat dissipation plate electrically connected to the drain, and protruding from a second side intersecting with a first side of the sealing resin in top view; and a heat dissipation plate electrically connected to the drain, and protruding from a third side opposing the second side of the sealing resin in top view. At least a height position of a lower surface of a distal end portion of the heat dissipation plate and a height position of an upper surface of a proximal end portion of the heat dissipation plate or a height position of a lower surface of a distal end portion of the heat dissipation plate and a height position of an upper surface of a proximal end portion of the heat dissipation plate are the same.

Abstract: A portable information handling system manages thermal energy presented at a keyboard with a hybrid support plate having a first portion of a first material and first thermal conductivity and a second material of a second thermal conductivity so that heat is presented in an even manner at the keyboard. For example, a keyboard support plate of a metal, such as steel, has a portion of liquid crystal polymer aligned with a central processing unit to impede heat transfer at the location of the central processing unit. In various embodiments, the liquid crystal polymer can include a carbon liquid crystal polymer and a delta liquid crystal polymer.

Abstract: An apparatus is described. The apparatus includes a back plate, where, an electronic circuit board is to be placed between the back plate and a thermal cooling mass for a semiconductor chip package. The back plate includes a first material and a second material. The first material has greater stiffness than the second material. The back plate further includes at least one of: a third material having greater stiffness than the second material; re-enforcement wires composed of the first material; a plug composed of the second material that is inserted into a first cavity in the first material, a stud inserted into a second cavity in the plug. An improved bolster plate having inner support arms has also been described.

Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

Abstract: Provided is a thermoelectric generation module including a plurality of p-type thermoelectric elements 24a and a plurality of n-type thermoelectric elements 24b alternately connected in series and mounted with sandwiched by first and second flexible printed circuit boards 32, 33. The p-type thermoelectric elements and the n-type thermoelectric elements have a chip size of 1 mm or less and 0.2 mm or greater and a height of 0.8 mm or greater and 3 mm or less.

Abstract: A multilayer circuit board includes a board body including insulator layers stacked upon each other, a first land pattern at the board body to mount a passive component, a second land pattern at the board body to mount an active component, and a heat-dissipation layer between the insulator layers and extending along main surfaces of the insulator layers. The heat-dissipation layer includes a hole extending therethrough in a stacking direction of the insulator layers. In a plan view from the stacking direction, an outer edge of the hole of the heat-dissipation layer is on an outer side of the first land pattern, or overlaps the first land pattern.

Abstract: A die stack structure includes an interconnection structure, a logic die, a control die, a first insulating encapsulant, a dummy die, a memory cube and a second insulating encapsulant. The logic die is electrically connected to the interconnection structure. The logic die comprises a first dielectric bonding structure. The control die is laterally separated from the logic die and electrically connected to the interconnection structure. The first insulating encapsulant laterally encapsulates the logic die and the control die. The dummy die is stacked on the logic die, the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure. The memory cube is stacked on and electrically connected to the control die, wherein the control die is located between the interconnection structure and the memory cube.

Abstract: A semiconductor package includes an encapsulant body; a first electrically conductive element having an outwardly exposed metal surface; a first carrier substrate having a first electrically conductive layer, a second electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer; a first electrically conductive spacer between the first electrically conductive element and the first electrically conductive layer; a power semiconductor chip between the first electrically conductive element and the first electrically conductive layer; and a second electrically conductive spacer between the first electrically conductive element and the power semiconductor chip, a first carrier region of the first electrically conductive layer is connected to a first power terminal, a second carrier region of the first electrically conductive layer is alongside the first carrier region and is connected to a second power terminal, a first region of the first electrically conductive element is

Abstract: A power switch module includes a semiconductor die and a conductive busbar. The semiconductor die is electrically conductively mounted to the busbar. The module also includes a dielectric coolant fluid and the busbar and the semiconductor die mounted thereto are immersed in the dielectric coolant fluid. The module can be include in a power converter assembly.

Abstract: A method for forming a package structure is provided. The method includes disposing a semiconductor die over a carrier substrate, wherein a removable film is formed over the semiconductor die, disposing a first stacked die package structure over the carrier substrate, wherein a top surface of the removable film is higher than a top surface of the first stacked die package structure, and removing the removable film to expose a top surface of the semiconductor die, wherein a top surface of the semiconductor die is lower than the top surface of the first stacked die package structure.

Abstract: Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate.

Abstract: Power electronics device assemblies, circuit board assemblies, and power electronics assemblies are disclosed. In one embodiment, a power electronics device assembly includes an S-cell including a first metal layer comprising a first surface having a recess, a first graphite layer bonded to the first metal layer, a second metal layer bonded to the first graphite layer, a solder layer disposed on the second metal layer, and an electrically insulating layer bonded to the solder layer. The power electronics device assembly may further include a power electronics device disposed within the recess of the first surface of the first metal layer.

Abstract: A power overlay (POL) module includes a semiconductor device having a body, including a first side and an opposing second side. A first contact pad defined on the semiconductor device first side and a dielectric layer, having a first side and an opposing second side defining a set of first apertures therethrough, is disposed facing the semiconductor device first side. The POL module, includes a metal interconnect layer, having a first side and an opposing second side, the metal interconnect layer second side is disposed on the dielectric layer first side) and extends through the set of first apertures to define a set of vias electrically coupled to the first contact pad. An enclosure defining an interior portion is coupled to the metal interconnect layer first side, and a phase change material (PCM) is disposed in the enclosure interior portion.

Abstract: An integrated circuit structure and method of forming is provided. A die is placed on a substrate and encased in molding compound. A redistribution layer is formed overlying the die and the substrate is removed. One or more surface mounted devices and/or packages are connected to the redistribution layer on an opposite side of the redistribution layer from the die. The redistribution layer is connected to a printed circuit board.

Abstract: A method includes attaching a first anisotropic conductive film including first conductive particles to a front surface of a substrate structure; compressing a first redistribution structure on the front surface of the substrate structure such that a first redistribution conductor of the first redistribution structure that is exposed is electrically connected by the first conductive particles to a connection terminal or a vertical connection conductor that is exposed from the substrate structure, attaching a second anisotropic conductive film including second conductive particles to a rear surface of the substrate structure; and compressing a second redistribution structure on the rear surface of the substrate structure such that a second redistribution conductor of the second redistribution structure that is exposed is electrically connected by the second conductive particles to the vertical connection conductor.

Abstract: Electronic assemblies may be fabricated with interconnects of different types present in multiple locations and comprising fused copper nanoparticles. Each interconnect or a portion thereof comprises a bulk copper matrix formed from fusion of copper nanoparticles or a reaction product formed from copper nanoparticles. The interconnects may comprise a copper-based wire bonding assembly, a copper-based flip chip connection, a copper-based hermetic seal assembly, a copper-based connector between an IC substrate and a package substrate, a copper-based component interconnect, a copper-based interconnect comprising via copper for establishing electrical communication between opposite faces of a package substrate, a copper-based interconnect defining a heat channel formed from via copper, and any combination thereof.

Abstract: An electronic device includes an arithmetic unit layer and a power supply. The arithmetic unit layer comprises at least one arithmetic unit. Each arithmetic unit comprises a first housing in a shape of cuboid. A first side direction of the first housing extends in a first direction. The first housing is provided with first and second openings at both ends in the first side direction thereof to form a coolant passage extending in the first direction. The power supply is stacked with arithmetic unit layer in a second or a third direction. A first side direction of the power supply is aligned with the first side direction of each arithmetic unit. The power supply is provided with third and fourth openings at both ends in the first side direction thereof to form a coolant passage extending in the first side direction of the power supply.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: An electronic module includes a semiconductor package, and a clip connected to the semiconductor package. The clip is connected to or includes at least one fastening element which is configured to make a connection to an external heat sink.

Abstract: A liquid-submersible thermal management system includes a cylindrical outer shell and an inner shell positioned in an interior volume of the outer shell. The cylindrical outer shell has a longitudinal axis oriented vertically relative to a direction of gravity, and the inner shell defines an immersion chamber. The liquid-submersible thermal management system a spine positioned inside the immersion chamber and oriented at least partially in a direction of the longitudinal axis with a heat-generating component located in the immersion chamber. A working fluid is positioned in the immersion chamber and at least partially surrounding the heat-generating component. The working fluid receives heat from the heat-generating component.

Abstract: A heat sink is a multilayer cooler for cooling a contacting heat-generating element by flowing a coolant from a fluid inlet to a fluid outlet, and includes a heat-receiving plate, a channel plate, an orifice plate, a header plate, and a bottom plate stacked in this order from the top surface and bonded by diffusion bonding. The channel plate has many cooling micropaths arranged in a matrix. The orifice plate has jet orifices for jetting a coolant into the cooling micropaths and drain orifices for draining the coolant from the cooling micropaths. The header plate includes a baffle that separates the fluid inlet from the fluid outlet. The baffle includes a plurality of parallel plates and first end plates and second end plates that alternately close openings at an end and at the opposite end of the parallel plate. The baffle and the peripheral wall define a supply channel.

Abstract: A semiconductor device has a substrate and plurality of first bumps formed over the substrate in an array. An array of second bumps is formed over the substrate on at least two sides of the first bumps. An electrical component is disposed over the first bumps. A package structure is disposed over the substrate and electrical component. The package structure has a horizontal member and legs extending from the horizontal member to form a cavity. The package structure is coupled to the array of second bumps. The package structure includes a material to operate as a heat sink or shielding layer. The shielding layer makes ground connection through the array of second bumps. The first bumps and second bumps have a similar height and width to form in the same manufacturing step. A protective layer, such as conductive epoxy, is disposed over the array of second bumps.

Abstract: In one example, a semiconductor device includes a first substrate with a first substrate top side, a first substrate bottom side opposite to the first substrate top side, a first substrate lateral side interposed between the first substrate top side and the first substrate bottom side, and a first substrate conductive structure. An electronic component is coupled to the first substrate top side and coupled to the first substrate conductive structure. A support includes a support wall having a first ledge coupled to the first substrate top side, a first riser coupled to the first substrate lateral side, and a second ledge extending from the first riser away from the first substrate lateral side. Other examples and related methods are also disclosed herein.

Abstract: Stacked semiconductor die assemblies with heat sinks and associated methods and systems are disclosed. In some embodiments, a controller carrying one or more memory dies may be attached to a front side of a substrate. The substrate may include a heat sink formed on its back side such that the heat sink can establish a thermal contact with the controller. Further, the heat sink may be coupled to a thermally conductive pad of a printed circuit board (PCB) that carries the substrate. In this manner, the controller may be provided with a heat path toward the PCB to dissipate thermal energy generated during operation. In some cases, the substrate may include a set of thermal vias extending from the heat sink toward the controller to enhance the thermal contact between the controller and the heat sink.

Abstract: A pattern of microchannels is formed on a major surface of a substrate on the side opposite an adhesive surface thereof. Through holes extend through the substrate and are connected to the pattern of microchannels. Solid circuit dies are adhesively bonded to the adhesive surface of the substrate. The contact pads of the solid circuit dies at least partially overlie and face the through holes. Electrically conductive channel traces are formed to electrically connect to the solid circuit dies via the through holes.

Abstract: A vertical non-volatile memory device capable of stably maintaining an operating temperature in a chip level, a semiconductor package including the memory device, and a heat dissipation method of the memory device. The vertical non-volatile memory device includes a substrate on which a cell array area and an extension area are defined, a vertical channel structure formed on the substrate, a thermoelectric device including at least two semiconductor pillars formed on the substrate, and a stacked structure on the substrate. The stacked structure includes a gate electrode layer and an interlayer insulation layer which are stacked alternately along sidewalls of the vertical channel structure and the at least two semiconductor pillars. The at least two semiconductor pillars include an n-type semiconductor pillar and a p-type semiconductor pillar which are electrically connected to each other through a conductive layer on the substrate.

Abstract: The semiconductor device includes a supporting member, a conductive member, and a semiconductor element. The supporting member has a supporting surface facing in a thickness direction. The conductive member has an obverse surface facing the same side as the supporting surface faces in the thickness direction, and a reverse surface opposite to the obverse surface. The conductive member is bonded to the supporting member such that the reverse surface faces the supporting surface. The semiconductor element is bonded to the obverse surface. The semiconductor device further includes a first metal layer and a second metal layer. The first metal layer covers at least a part of the supporting surface. The second metal layer covers the reverse surface. The first metal layer and the second layer are bonded to each other by solid phase diffusion.

Abstract: A semiconductor apparatus includes a substrate, a plurality of heat generating elements mounted on the substrate, a heat dissipation member fixed to the substrate and disposed such that the heat generating elements are interposed between the heat dissipation member and the substrate, at least one first heat conduction member provided on a first surface of the heat dissipation member, the first surface facing the heat generating elements, and a plurality of second heat conduction members each provided on a second surface of a corresponding one of the heat generating elements, the second surface facing the heat dissipation member, wherein the at least one first heat conduction member and the second heat conduction members are in contact with each other at an interface between opposing surfaces thereof.

Abstract: A semiconductor package comprises a substrate and a ceramic carrier mounted to the substrate. An integrated circuit (IC) die is mounted to the ceramic carrier. A heat extraction path away from the IC die comprises: i) a thermal interface material over the IC die, the thermal interface material having a thickness of approximately 25 to 80 um; ii) an integrated heat spreader over the thermal interface material; iii) a ceramic carrier plate over the integrated heat spreader; and iv) an electrically conductive thermal pad between the ceramic carrier plate and a housing of the semiconductor package.

Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.

Abstract: According to one embodiment, an apparatus is provided that includes a first block and a second block, one or more springs provided between the first block and the second block, and a thermally conductive wrap extending from the first block to the second block, wherein the thermally conductive wrap is configured to conduct heat away from the first block. An assembly including a chassis, a receptacle, and the apparatus is also provided, as well as a method for operating the apparatus.

Abstract: A thermal islanding heatsink (a monolithic heat sink that includes a thermal insulating barrier is provided within a memory sub-system. The memory sub-system can be a solid state drive that can include a memory device, such as a volatile memory device and/or a non-volatile memory device, a power regulation area, and/or a controller. The thermal insulating barrier is deployed between the memory device and the power regulation area or between the memory device and the controller.

Abstract: A package carrier includes a circuit structure layer and a heat-conducting element. The circuit structure layer includes a notch portion. The heat-conducting element includes a first heat-conducting portion and a second heat-conducting portion vertically connected to the first heat-conducting portion. The notch portion exposes the first heat-conducting portion, and an outer surface of the second heat-conduction portion is aligned with a side surface of the circuit structure layer.

Abstract: An interposer includes a base layer including a first surface and a second surface that are opposite to each other. An interconnect structure is disposed on the first surface. The interconnect structure includes a metal interconnect pattern and an insulating layer surrounding the metal interconnect pattern. A first lower protection layer is disposed on the second surface. A plurality of lower conductive pads is disposed on the first lower protection layer. A plurality of through electrodes penetrates the base layer and the first lower protection layer. The plurality of through electrodes electrically connects the metal interconnect pattern of the interconnect structure to the lower conductive pads. At least one of the insulating layer and the first lower protection layer has compressive stress. A thickness of the first lower protection layer is in a range of about 13% to about 30% of a thickness of the insulating layer.

Abstract: Techniques for dynamically changing a pressure within a pressurized cooling system to thereby allow different cooling rates to be used to cool electronic equipment are disclosed. A pressurized cooling system cools electronic heat generating components using dielectric heat transfer fluid disposed within a two-phase immersion cooling container. This container is operable to maintain different pressure levels. The pressurized cooling system includes a pressure system structured to modify a pressure within the container. The system operates in a first state when the pressure is above a threshold pressure. The system operates in a second state when the pressure is at the threshold pressure. The system operates in either one of the first state or the second state based on an operating state of the heat generating component.

Abstract: A contiguous integrated heat spreader suitable for an integrated circuit (IC) die package. Heat spreader material may be deposited with a high throughput additive manufacturing (HTAM) technique directly upon a surface of an IC die, and over a portion of a package substrate beyond an edge of the IC die. The contiguous heat spreader may have high thermal conductivity and offer low thermal resistance in absence of any intervening thermal interface material (TIM). The contiguous heat spreader may span multiple IC die and accommodate different die heights. The heat spreader may be contiguous with multiple die. Heat spreader material may be absent where thermal breaks within the heat spreader are advantageous.

Abstract: A cooling device for cooling a chip, a server with such a cooling device, and a rack are disclosed. The cooling device comprises a cooling layer that is divided into multiple cooling regions; and an internal region that includes a vapor separation core. Two-phase coolant that enters a first cooling region of the cooling layer is converted to mixed fluid due to heat extracted from a corresponding region of the chip. The mixed fluid is elevated to the vapor separate core, which separates vapor from liquid in the mixed fluid. The vapor exits the cooling device while the liquid is transported to a second cooling region in the cooling layer. The cooling device can be used with a condenser in a server to form an internal server loop, and can be connected to a rack to form a main fluid loop. The two coolant recirculation loops are used together to maintain a predetermined liquid balance in the cooling device.

Abstract: A power module for operating an electric vehicle drive, comprising: numerous semiconductor components; a heatsink for discharging heat generated by the semiconductor components; a DC link capacitor connected in parallel to the semiconductor components; a DC link line electrically connecting the DC link capacitor to the semiconductor components; wherein the DC link line is at least partially located in a hole formed in the heatsink.

Abstract: Described are systems for electronic heatsink safety including a system comprising a thermoelectric generator integrated into a heatsink, where the thermoelectric generator includes a first portion exposed to ambient temperature and a second portion contacting the heatsink, and where the thermoelectric generator is configured to produce a current based on a temperature difference between the first portion and the second portion. The system further comprises a first Light Emitting Diode (LED) electrically connected to the thermoelectric generator, where the current is configured to activate the first LED.

Abstract: A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.

Abstract: Thermally conductive shock absorbers for electronic devices are disclosed. An electronic device includes a housing and a hardware component positioned inside the housing. A thermally conductive shock absorber is located between an inner surface of the housing and the hardware component. The thermally conductive shock absorber including an impact absorbing material and a thermal conductive material being in contact with at least a portion of the impact absorbing material.

Abstract: A semiconductor package includes a redistribution substrate, and a semiconductor chip disposed on a top surface of the redistribution substrate. The redistribution substrate includes under bump patterns laterally spaced apart from each other, a dummy pattern disposed between the under bump patterns, a passivation pattern disposed on a bottom surface of the dummy pattern, an insulating layer covering top surfaces and sidewalls of the under bump patterns and a sidewall and a top surface of the dummy pattern, and a redistribution pattern disposed on one of the under bump patterns and electrically connected to the one under bump pattern. The passivation pattern includes a different material from that of the insulating layer.

Abstract: A package structure includes a semiconductor package, a thermal conductive gel, a thermal conductive film and a heat spreader. The thermal conductive gel is disposed over the semiconductor package. The thermal conductive film is disposed over the semiconductor package and the thermal conductive gel. A thermal conductivity of the thermal conductive film is different from a thermal conductivity of the thermal conductive gel. The thermal conductive film is surrounded by the heat spreader.

Abstract: Disclosed are aspects of apparatuses and methods of fitting a cooling device to a circuit board for cooling a high-power electronic component mounted on the circuit board. Cooling apparatuses, and arrangement thereof, are also described. The method provides the cooling device with a cooling surface having a cooling area for thermally connecting to a to-be-cooled surface of the electronic component. Fixing elements are provided for moving the cooling surface towards the circuit board. A distance position “d” of the to-be-cooled surface from the circuit board is determined, and on this basis spacer elements are selected to be interposed between the cooling device and the circuit board to limit the movement by the fixing elements to a position where the cooling area is in proximity to the to-be-cooled surface.

Abstract: The invention discloses a method and modified aerodynamic apparatuses: fluid pushers-off and fluid motion-sensors, making enable efficient implementation and use of a controllable enhanced jet-effect, either the waving jet-effect, the Coanda jet-effect, the lift-effect, the effect of thrust, the Venturi effect, and/or the de Laval jet-effect, all are controllable using the Peltier effect and/or the Seebeck effect. The modified aerodynamic apparatuses are geometrically shaped and supplied with built-in thermoelectric devices, wherein the presence of the thermoelectric devices provides for new functional properties of the modified aerodynamic apparatuses. The method solves the problem of effective control of the operation of modified aerodynamic apparatuses such as airfoil wings of a flying vehicle, convergent-divergent nozzles, loudspeakers, and detectors of acoustic waves, all of a highly-efficient functionality.

Abstract: A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.

Abstract: A system for cooling a power component includes a first metal layer. A cooling layer having a first surface is in contact with a surface of the first metal layer. A second metal layer is included having a surface in contact with a second surface of the cooling layer opposite the first metal layer. The cooling layer is of a material different from that of the first metal layer and that of the second metal layer. A plurality of cooling features are embedded in the material of the cooling layer. The cooling channels are spaced apart from both the first metal layer and the second metal layer by the material of the cooling layer. An electrically conductive path connects the first metal plate to the second metal plate.

Abstract: A semiconductor device includes an insulating substrate, wiring layers, heat dissipation layers, a semiconductor element, and a sealing resin. The wiring layers each have a first obverse face and a first reverse face oriented in opposite directions in a thickness direction of the substrate. The first reverse faces of the wiring layers are connected to the substrate. The heat dissipation layers each have a second obverse face oriented in the same direction as the first obverse face, and a second reverse face oriented opposite to the second obverse face in the thickness direction. The heat dissipation layers are located opposite to the plurality of wiring layers in the thickness direction with respect to the substrate. The second obverse faces of the heat dissipation layers are connected to the substrate. The semiconductor element is connected to one of the first obverse faces of the wiring layers. The sealing resin covers the substrate, the wiring layers, and the semiconductor element.

Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

Abstract: A heat sink for use in an immersion cooling system that includes a sintered powder structure enclosed in a porous enclosure. The porous enclosure has openings, e.g., formed by a mesh, with a size to help contain sintered powder particles that may be dislodged during operation of the heat sink.