For Integrated Circuit Patents (Class 257/713)
  • Patent number: 10791630
    Abstract: A printed circuit board having conductor tracks formed on one side of a substrate. The substrate is able to be cohesively bonded at a contact face to a cover for protecting the conductor tracks. In this case, the substrate includes a step, which forms a barrier with respect to an auxiliary material for promoting the cohesive bond, in order to prevent any wetting of the conductor tracks with the auxiliary material. A sensor having a printed circuit board for use in a fuel filling level measurement system of a vehicle.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 29, 2020
    Assignee: Vitesco Technologies GmbH
    Inventors: Erich Mattmann, Robert Peter, Waldemar Brinkis, Martin Maasz, Burkhard Dasbach
  • Patent number: 10784181
    Abstract: An apparatus includes a circuit device, a heat sink fin, and a thermal interface material layer. The thermal interface material layer is thermally coupled to the circuit device and the heat sink fin. The thermal interface material layer includes a first alloy layer, a nanometal particle layer, and a second alloy layer. The first alloy layer is thermally coupled to the circuit device. The nanometal particle layer is thermally coupled to the first alloy layer. The nanometal particle layer includes nanometal particles and an intermediate mixture.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: September 22, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: HuiLi Fu, Jyh Rong Lin, Shujie Cai
  • Patent number: 10784227
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a semiconductor package. The method may be performed by attaching a first thermal conductivity layer to an upper surface of a first chip, and attaching a second thermal conductivity layer to an upper surface of a second chip. A first support substrate is attached to lower surfaces of the first chip and the second chip. A molding compound is formed over the first support substrate and laterally surrounds the first chip and the second chip. The first support substrate is replaced with a package substrate after forming the molding compound over the first support substrate.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Tseng, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 10779444
    Abstract: A control box includes a housing defining an interior, a circuit board disposed within the interior, and an input/output connector extending from the housing. The control box further includes a heat sink removably connected to the housing such that the circuit board is positioned between the housing and the heat sink. The circuit board is in contact with the heat sink.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: September 15, 2020
    Assignee: GE Aviation Systems LLC
    Inventors: Randall Lee Neuman, Stefano Angelo Mario Lassini, Jason Eggiman
  • Patent number: 10727153
    Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: July 28, 2020
    Assignee: NXP USA, Inc.
    Inventors: Lakshminarayan Viswanathan, Jaynal A Molla
  • Patent number: 10714406
    Abstract: The module (PM1) has an architecture with 3D stacking of the electronic power switching chips (IT, ID) and comprises first and second dielectric substrates (SH, SL) that are intended to come into thermal contact with first and second heat sinks (DH, DL), respectively, at least one pair of first and second stacked electronic power switching chips (ITHS, IDHS; ITHS, IDHS) and a common intermediate substrate (SC), the first and second electronic power switching chips being sandwiched between the first dielectric substrate and the common intermediate substrate and between the common intermediate substrate and the second dielectric substrate, respectively. According to the invention, the common intermediate substrate is a metal element formed as a single piece and comprises a central portion for the implantation of the electronic power switching chips and at least one.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 14, 2020
    Assignee: INSTITUT VEDECOM
    Inventors: Hadi Alawieh, Menouar Ameziani
  • Patent number: 10670819
    Abstract: A non-plated region is formed in a certain range from an end of a submount. The non-plated region is a portion where a plating layer is not provided, and thus a substrate of the submount is exposed. An intermediate layer is formed on the plating layer. Furthermore, a plating layer is formed on the intermediate layer. A semiconductor laser is formed on the plating layer. The position of an end of the semiconductor laser substantially coincides with the position of an end of the plating layer (the intermediate layer). That is, even in a case where there is a deviation between an end face of the intermediate layer and an end face of the semiconductor laser, the amount of this deviation is sufficiently smaller than the amount by which the intermediate layer is set back from an end face of the submount.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: June 2, 2020
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Masakazu Miura, Jun Miyokawa, Kazuki Yamaoka, Hajime Mori
  • Patent number: 10624240
    Abstract: An example device in accordance with an aspect of the present disclosure includes a first shield to provide thermal isolation between a first component and a heatsink of a second component, and to provide a cooling channel that is thermally isolated from the heatsink to receive an airflow for the first component. A second shield is to provide thermal isolation between the first shield and the heatsink, and to provide a thermal barrier region between the first shield and the second shield.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: April 14, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kevin Leigh, John Norton, George D. Megason
  • Patent number: 10600753
    Abstract: A semiconductor device includes an integrated circuit attached to a chip carrier in a flip chip configuration. A substrate extends to a back surface of the integrated circuit, and an interconnect region extends to a front surface of the integrated circuit. A substrate bond pad is disposed at the front surface, and is electrically coupled through the interconnect region to the semiconductor material. The chip carrier includes a substrate lead at a front surface of the chip carrier. The substrate lead is electrically coupled to the substrate bond pad. An electrically conductive compression sheet is disposed on the back surface of the integrated circuit, with lower compression tips making electrical contact with the semiconductor material in the substrate. The electrically conductive compression sheet is electrically coupled to the substrate lead of the chip carrier by a back surface shunt disposed outside of the integrated circuit.
    Type: Grant
    Filed: August 28, 2016
    Date of Patent: March 24, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: James Fred Salzman
  • Patent number: 10600774
    Abstract: An integrated circuit (IC) is fabricated with transistors and gated diodes having selected epitaxial growth. The transistors may be Field-Effect Transistors (FETs) for example, and more specifically, may be fin-based FETs (finFETs) where fins are fabricated, in part, using an epitaxial growth process. The IC is further fabricated with gated diodes. Selected gated diodes within the IC are fabricated using the epitaxial growth process on the fins of the gated diode to form an anode and a cathode. Other selected gated diodes are fabricated without using epitaxial growth processes to form the anode and the cathode. In still another aspect, selected gated diodes are fabricated with epitaxial growth processes on either the anode or the cathode, but not both. In an exemplary aspect, the other selected gated diodes are part of electrostatic discharge (ESD) protection circuits in an input/output (I/O) region of the IC.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: March 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Youn Sung Choi, Youseok Suh, Kwanyong Lim
  • Patent number: 10586760
    Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in the casing, and for forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The outer sidewalls of the upper portion of the casing are located between vertical planes defined by opposing outer sidewalls of the lower portion of the casing.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kerry Bernstein, Thomas Brunschwiler, Bruno Michel
  • Patent number: 10586779
    Abstract: Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400° C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, James C. Matayabas, Jr., Akshay Mathkar
  • Patent number: 10546798
    Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: January 28, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino Tolentino, Vernal Raja Manikam, Azhar Aripin
  • Patent number: 10504817
    Abstract: Provided is a technique for improving product attachment. In a semiconductor device, the following expression is satisfied by an angle A formed by an imaginary line connecting two attachment holes together and an imaginary line connecting together a lowest point of one of two projections positioned in a surrounding portion of one of the two attachment holes and a contact point between a bulge and a heat sink, with a screw fastened to the heat sink through the one attachment hole, where M represents a vertical direction between the lower end of a body and the lower end of a case, where W represents a bulge amount of the bulge, where T represents a height of the projection, where L represents a horizontal distance from the outer peripheral end of the case to the outer peripheral end of the heat dissipation plate: 0<A<arctan((M+W?T)/L).
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 10, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuya Okada, Hiroki Muraoka, Koichi Masuda, Yasutaka Shimizu, Shoji Izumi
  • Patent number: 10499500
    Abstract: A metal pallet is integrated within a circuit board using a process similar to a multilayer PCB, which integrates the metal pallet into the circuit board at the same time as the supporting layers are fabricated. The use of B-stage material provides a bonding mechanism for the metal pallet to be embedded within the circuit board, creating a cohesive integrated part. Embedding the pallet during the fabrication process, pre-lamination, generates a more robust construction and connection not impacted by post fabrication process in assembly. After assembly the circuit board with embedded metal pallet can be mounted directly on a heat sink, cool ribbon or other feature required to help remove heat. The planar back side surface provides a more robust mounting of the metal pallet than a post fabricated assembly as used in conventional techniques.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: December 3, 2019
    Assignee: Flex Ltd.
    Inventors: J H Berkel, Todd Robinson, Joan K. Vrtis
  • Patent number: 10468332
    Abstract: Provided is a cooler including an upper plate configured to have a semiconductor chip to be arranged thereon, a plurality of plate-like fins arranged under the upper plate, and a coupling bar coupled to the plate-like fins. The coupling bar has a main-body portion and a plurality of comb-tooth portions protruding from the main-body portion into the flow channel, the cooler includes a plurality of openings in a plane orthogonal to an extending direction of the plate-like fins, and the openings are defined at least by the comb-tooth portions and the plate-like fins, and the openings include a first opening provided in a first flow channel that does not run below the semiconductor chip, and a second opening provided in a second flow channel that runs below the semiconductor chip, where the second opening is larger than the first opening.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: November 5, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Toru Yamada
  • Patent number: 10438930
    Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, Christopher L. Rumer, Nitin Deshpande, Robert M. Nickerson
  • Patent number: 10433414
    Abstract: A method of manufacturing a printed circuit board includes providing a substrate having at least one resin plate and a semi-cured sheet. A through hole is formed in the substrate to accommodate a radiator having an electrically conductive layer and an electrically insulated layer. The substrate and radiator are heat pressed to fully cure the epoxy and couple the substrate and radiator together. The excess resin is removed and electrically conductive layers are plated on the board. Surface circuits and a heat dissipating pattern are then etched into the conductive layer. An LED is attached to the printed circuit board. In some embodiments, a flexible segment is formed by removing a portion of the substrate. The radiator can have an electrically insulated layer extending at least partially across a surface of an electrically insulated and thermally conductive core.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: October 1, 2019
    Assignee: Rayben Technologies (HK) Limited
    Inventors: Kai Chiu Wu, Lam Wai Kin Raymond, Zheng Wang
  • Patent number: 10433463
    Abstract: Embodiments herein relate to a heat sink having nano- and/or micro-replication directly embossed in a bulk solidifying amorphous alloy comprising a metal alloy, wherein the heat sink is configured to transfer heat out of the heat sink by natural convection by air or forced convection by air, or by fluid phase change of a fluid and/or liquid cooling by a liquid. Other embodiments relate apparatus having the heat sink. Yet other embodiments relate to methods of manufacturing the heat sink and apparatus having the heat sink.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: October 1, 2019
    Assignees: Crucible Intellectual Property, LLC, Apple Inc.
    Inventors: Christopher D. Prest, Joseph Poole, Joseph W. Stevick, Quoc Tran Pham, Theodore Andrew Waniuk
  • Patent number: 10418309
    Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a substrate, a first die, a gasket, and a thermal interface. The first die may be connected to the substrate. The gasket may be connected to the substrate and may encircle the first die to form a space between the first die and the gasket. The thermal interface material may be located within the space formed by the first die and the gasket.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Bijoyraj Sahu, Thomas A. Boyd, Jeffory L. Smalley
  • Patent number: 10411042
    Abstract: Disclosed is a display device including: a substrate including a display area for displaying an image and a peripheral area neighboring the display area; a plurality of signal lines formed in the display area; a pad formed in the peripheral area; and a plurality of connection wires for connecting the signal lines and the pad, wherein a first connection wire and a second connection wire neighboring the first connection wire from among the plurality of connection wires are disposed on different layers, and the first connection wire and the second connection wire, which are formed to extend from the pad and are bent at least twice to have at least one being bent toward backward direction, are disposed in the peripheral area.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung-Kyu Lee, Tae Hoon Kwon, Ji-Hyun Ka
  • Patent number: 10332899
    Abstract: An IC package, comprising a substrate and two or more vertically stacked dies disposed within the substrate, wherein all the edges of the two or more dies are aligned with respect to one another, wherein at least two dies of the two or more vertically stacked dies are coupled directly to one another by at least one wire bonded to the ones of the at least two dies.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Yi Xu, Florence Pon, Yong She
  • Patent number: 10321569
    Abstract: Electronic module with all-sided electromagnetic interference (EMI) shielding and methods of making same. The electronic module includes an encapsulated circuit board between a top plate and a conductive bottom plate, electrical leads extending from the circuit board through the bottom plate, and a continuous conductive coating substantially covering the entire electronic module except for a bottom surface of the bottom plate. The conductive coating forms direct, independent connections at least to the circuit board and the bottom plate. The conductive coating provides EMI shielding across the top and sides of the electronic module. The conductive bottom plate provides EMI shielding across the bottom of the electronic module. Methods of manufacturing include encapsulating a circuit board between a top plate and bottom plate, separating materials from the encapsulated circuit board to expose conductive traces on the circuit board and bottom plate, and coating the sawed device with a conductive coating.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: June 11, 2019
    Assignee: VPT, INC.
    Inventors: Stephen J. Butler, Anthony G. Salamone
  • Patent number: 10319660
    Abstract: A heat transportation mechanism that is thermally conductive, but not electrically conductive, is provided so as to permit transportation of heat generated by a semiconductor device die to the exterior of a semiconductor device package. Embodiments can use a thermally conductive polymer structure, added to the package mold compound, to transport heat through the mold compound. The thermally conductive polymer structure can be fixed to the semiconductor device die prior to molding or can be included in an overmolding compound slug prior to performing the overmolding process. Flexibility of placement of the thermally conductive polymer structure is provided by using dielectric compounds.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: June 11, 2019
    Assignee: NXP USA, INC.
    Inventor: Christopher W. Argento
  • Patent number: 10276549
    Abstract: A package structure and method for forming the same are provided. The package structure includes a package component, and a device die formed over the package component. The device die includes a device substrate and a conductive pad over the device substrate, and the device die has a first height. The package structure also includes a dummy die formed over the package component and adjacent to the device die, and the dummy die has a second height smaller than the first height.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Wei Chen, Li-Hsien Huang
  • Patent number: 10262921
    Abstract: A semiconductor module includes a baseplate, a cover element attached to the baseplate so that detaching the cover element from the baseplate requires material deformations, and a semiconductor element in a room defined by the baseplate and the cover element. The semiconductor element is in a heat conductive relation with the baseplate and an outer surface of the baseplate is provided with laser machined grooves suitable for conducting heat transfer fluid. The laser machining makes it possible to make the grooves after the semiconductor module has been assembled. Therefore, regular commercially available semiconductor modules can be modified, with the laser machining, to semiconductor modules as disclosed.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 16, 2019
    Assignee: LAPPEENRANNAN TEKNILLINEN YLIOPISTO
    Inventors: Mika Lohtander, Leevi Paajanen, Tapani Siivo, Antti Jortikka, Hannu Ylisiurua, Emma Paasonen, Jyrki Montonen
  • Patent number: 10244668
    Abstract: A heat radiation structure includes a heat spreader provided on a heating component mounted on a substrate, a heat sink disposed at a position facing the heat spreader, a heat transfer member disposed between the heat spreader and the heat sink, and transmitting heat from the heat spreader to the heat sink, and a conductive member electrically connecting the heat spreader and the heat sink.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: March 26, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yoshihide Nakanishi, Norihiro Yahata, Hisashi Serita, Masaya Koshimuta
  • Patent number: 10236229
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a conformal lid to improve the chip package assembly from deformation. In one example, a chip package assembly is provided that includes integrated circuit (IC) dies, a packaging substrate, and a lid. The packaging substrate has a die receiving area that is defined by the laterally outermost extents of the IC dies mounted to the packaging substrate. The lid a surface that includes a first region and a second region. The first region is disposed over the first IC die while the second region of the lid extends below the second surface the first IC die and is spaced above the packaging substrate. At least a portion of the second region of the lid is overlapped with the die receiving area.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 19, 2019
    Assignee: XILINX, INC.
    Inventor: Jaspreet Singh Gandhi
  • Patent number: 10224613
    Abstract: The present invention discloses a wireless device, which includes a substrate and an antenna. The antenna includes a printed antenna element and a 3-dimensional antenna element. The printed antenna element is printed on the substrate, while the 3-dimensional antenna element is disposed on the substrate and coupled to the printed antenna element. The printed antenna element and the 3-dimensional antenna element jointly have a physical length of a desired frequency.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: March 5, 2019
    Assignee: MEDIATEK INC.
    Inventors: Min-Chung Wu, Shao-Chin Lo
  • Patent number: 10224269
    Abstract: A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Brian M. Erwin, Brian W. Quinlan
  • Patent number: 10217692
    Abstract: A device and related method that provides a two-phase heat transfer device with a combination of enhanced evaporation and increase cooling capacity. A recess topology is used to increase suction of working fluid toward a heat source. A non-wetting coating or structure may be used to keep working fluid away from the spaces between elongated members of an evaporator and a wetting coating or structure may be used to form thin films of working fluid around the distal regions of elongated members. The devices and method described herein may be used to cool computer chips, the skin of a hypersonic flying object, a parabolic solar collector, a turbine engine blade, or other heat sources that require high heat flux.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: February 26, 2019
    Assignee: University of Virginia Patent Foundation
    Inventors: Hossein Haj-Hariri, Seyed Reza Monazami Miralipour
  • Patent number: 10177116
    Abstract: An electrical device that includes at least two active wafers having at least one through silicon via, and at least one unitary electrical communication and spacer structure present between a set of adjacently stacked active wafers of the at least two active wafers. The unitary electrical communication and spacer structure including an electrically conductive material core providing electrical communication to the at least one through silicon via structure in the set of adjacently stacked active wafers and a substrate material outer layer. The at least one unitary electrical communication and spacer structure being separate from and engaged to the adjacently stacked active wafers, wherein coolant passages are defined between surfaces of the adjacently stacked active wafers and the at least one unitary electrical communication and spacer structure.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul S. Andry, Mark D. Schultz, Cornelia K. Tsang
  • Patent number: 10170457
    Abstract: Chip on wafer on substrate structures and methods of forming are provided. The method includes attaching a first die and a second die to an interposer. The method also includes attaching a first substrate to a first surface of the first die and a first surface of the second die. The first substrate includes silicon. The first surface of the first side is opposite to the surface of the first die that is attached to the interposer, and the first surface of the second die is opposite to the surface of the second die that is attached to the interposer. The method includes bonding the interposer to a second substrate.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ming Chen, Tu-Hao Yu, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
  • Patent number: 10157856
    Abstract: A method of fabricating a semiconductor structure. The method includes forming a dummy structure over a semiconductor body. The method further includes depositing an inter-layer dielectric (ILD) over the semiconductor body. The method further includes removing a dummy material of the dummy structure to form an opening in the ILD. The method further includes filling the opening with a dielectric material to form a dielectric structure. The method further includes stacking a plurality of interconnect elements over the dielectric structure.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Shan Wang, Shun-Yi Lee
  • Patent number: 10159152
    Abstract: Embodiments of the invention include a printed circuit board (PCB) assembly that includes advanced component in cavity (ACC) technology and methods of forming such PCB assemblies. In one embodiment, the PCB assembly may include a PCB that has a cavity formed on a first surface of the PCB. A plurality of contacts may be formed in the cavity. The cavity provides a location where components may be electrically coupled to the PCB. Additionally, a package that is mounted to the PCB may extend over the cavity. Since the package passes directly over the component, the components may be used to electrically couple the package to one or more of the contacts formed in the cavity. Accordingly, embodiments of the invention allow for the surface area used for components to be reduced, and also improves electrical performance of the PCB assembly by positioning the components proximate to the package.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Ladd D. Campbell, Scott M. Mokler, Juan Landeros, Jr., Michael J. Hill, Jin Zhao
  • Patent number: 10150433
    Abstract: An aircraft power distribution system according to an exemplary aspect of the present disclosure includes, among other things, a power source, a load, and a power distribution panel receiving power from the power source and selectively providing power to the load. The power distribution panel includes a contactor having a housing. A heat sink provides a portion of the housing.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: December 11, 2018
    Assignee: HAMILTON SUNDSTRAND CORPORATION
    Inventor: Debabrata Pal
  • Patent number: 10153261
    Abstract: The subject disclosure relates to an integrated circuit package having an application specific integrated circuit, a high bandwidth memory, a first heat sink having a first footprint and a first path, and a second heat sink having a second footprint and a second path, wherein the second footprint does not exceed the first footprint. The thermal energy through the first path travels from the application specific integrated circuit to the first heat sink and thermal energy through the second path travel from the high bandwidth memory through one or more heat pipes to the second heat sink.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: December 11, 2018
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Baris Dogruoz, Vic Chia, M. Onder Cap
  • Patent number: 10128601
    Abstract: A contactor device includes: a first body substrate; a second body substrate; a flexible membrane connected to the first body substrate and second body substrate, wherein the second substrate body is movable relative to the first substrate body by flexure of the flexible membrane; an electrical contact member carried by the second substrate body; a microfluidic-channeled substrate coupled to the first body substrate, the microfluidic-channeled substrate having a chamber and a microfluidic channel in fluid communication with the chamber; and a 3-dimensional flexible membrane enclosing the chamber, wherein the 3-dimensional flexible membrane flexes toward the second body substrate when a fluid pressure is applied to the chamber through the microfluidic channel whereby a force or a movement is transferred to the second body substrate by the 3-dimensional flexible membrane.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 13, 2018
    Assignee: Componentzee, LLC
    Inventor: Masud Beroz
  • Patent number: 10108232
    Abstract: An electronics enclosure is disclosed that provides passive cooling of electronic components while reducing electromagnetic interference (EMI) emissions. The electronics enclosure includes an electronics assembly with at least one electronic component and a heat sink coupled to the electronics assembly. The heat sink has a base portion configured to thermally couple to the at least one electronic component when the heat sink is coupled to the electronic assembly. The electronics enclosure also includes a conductive enclosure forming an enclosed volume around the electronics assembly. The enclosure has a first opening configured to fit around the heat sink and at least one second opening. All non-conductive passages from the volume to the external environment have at least one cross-sectional opening having a continuous conductive perimeter with a maximum linear length within the opening of less than one quarter wavelength of a determined maximum shielding frequency.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: October 23, 2018
    Assignee: CAREFUSION 303, INC.
    Inventors: David H. Nicol, Michael Dugan Joyce, Brendan Burgess
  • Patent number: 10109162
    Abstract: A haptic effect enabled system generates a haptic effect using an electric potential responsive fluid. A haptic enabled apparatus includes a fluid and a substrate. The fluid is responsive to an electric field. The substrate is at least partially flexible and defines a channel. The fluid is positioned within at least a portion of the channel. A portion of the substrate proximal to the fluid is stiffer than a portion of the substrate spaced from the fluid, thereby creating a haptic effect.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: October 23, 2018
    Assignee: IMMERSION CORPORATION
    Inventors: Mansoor Alghooneh, Vahid Khoshkava, Juan Manuel Cruz Hernandez, Mohammadreza Motamedi
  • Patent number: 10094549
    Abstract: The present application discloses various embodiments of a heat sink for semiconductor devices and methods for using and constructing the same. According to at least one aspect of the present disclosure, a heat sink for cooling a semiconductor device includes a base plate including a first side and a second side; a leg extending from the second side of the base plate, the leg including a distal end opposite the base plate and opposing walls extending between the base plate and the distal end; a leg plate disposed adjacent the distal end of the leg; a plurality of fins disposed between the distal end of the leg and the leg plate; and a plurality of micro-channels defined by the distal end of the leg, the plurality of fins, and the leg plate.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: October 9, 2018
    Assignee: Flex-N-Gate Advanced Product Development, LLC
    Inventors: Muhammed Aquil Hamid, Steve Barman, Charles F. Schweitzer
  • Patent number: 10074633
    Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. Similarly, the package substrate includes a second peripheral portion extending laterally outward beyond a second edge surface of the second semiconductor die. The semiconductor die assembly further includes a first volume of molded underfill material between the first and second semiconductor dies, a second volume of molded underfill material between the package substrate and the second semiconductor die, a first molded peripheral structure laterally adjacent to the first edge surface of the first semiconductor die, and a second molded peripheral structure laterally adjacent to the second edge surface of the second semiconductor die.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Bradley R. Bitz, Xiao Li
  • Patent number: 10051735
    Abstract: A product and method for packaging high power integrated circuits or infrared emitter arrays for operation through a wide range of temperatures, including cryogenic operation. The present invention addresses key limitations with the prior art, by providing temperature control through direct thermal conduction or active fluid flow and avoiding thermally induced stress on the integrated circuits or emitter arrays. The present invention allows for scaling of emitter arrays up to extremely large formats, which is not viable under the prior art. The present invention eliminates or otherwise reduces risks associated with vaporization of coolant within the heatsink structure.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 14, 2018
    Assignee: Oleson Convergent Solutions LLC
    Inventor: Jim Oleson
  • Patent number: 10020240
    Abstract: A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a heat dissipation plate bonded to an upper surface of the semiconductor element with an adhesive, and an encapsulation resin that fills a gap between the heat dissipation plate and the wiring substrate. The heat dissipation plate includes a body overlapped with the semiconductor element in a plan view. The body is larger than the semiconductor element in a plan view. A projection is formed integrally with the body. The projection projects outward from an end of the body and is located at a lower position than the body. The encapsulation resin covers upper, lower, and side surfaces of the projection. The body includes an upper surface exposed from the encapsulation resin.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: July 10, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takashi Ozawa, Yasuhiro Sakuda
  • Patent number: 10015117
    Abstract: In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Linden Cornett, David B. Minturn, Sujoy Sen, Hemal V. Shah, Anshuman Thakur, Gary Tsao, Anil Vasudevan
  • Patent number: 10014233
    Abstract: An electronic component containing package includes a substrate including a placement region for placing an electronic component in an upper face thereof; a frame disposed on the upper face of the substrate surrounding the placement region, and including a penetration part opening; and an input/output member disposed in the frame closing the penetration part, including a plurality of wiring conductors which extend inward and outward of the frame and are electrically connected to the electronic component. The input/output member includes via conductors which are connected to the wiring conductors and embedded at sites overlapping with the wiring conductors within a region surrounded by the frame in the input/output member, and a ground layer disposed in a surrounding of lower ends of the via conductors being spaced from the via conductors. Improved high frequency characteristics can be achieved.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: July 3, 2018
    Assignee: KYOCERA CORPORATION
    Inventor: Yoshiki Kawazu
  • Patent number: 10015907
    Abstract: A heat dissipating device includes a thermal conductive substance, a plurality of heat-radiating protrusions and a plurality of turbulence-generating structures. The thermal conductive substance has a first surface and a second surface opposite to the first surface. The heat-radiating protrusions are integrally formed with the thermal conductive substance on the first surface. At least one of the turbulence-generating structures is formed on the first surface of the thermal conductive substance in concaved manner, and arranged around a bottom periphery of the heat-radiating protrusions, so as to obstruct a development of a boundary layer around the bottom of the heat-radiating protrusions.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: July 3, 2018
    Assignee: AMULAIRE THERMAL TECHNOLOGY, INC.
    Inventors: Chun-Lung Wu, Ming-Sian Lin
  • Patent number: 9997377
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming a sacrificial microchannel material on a device, forming an overmold material on the sacrificial microchannel material, and vaporizing the sacrificial microchannel material to form microchannel structures in the overmold that are conformal to the surfaces of the device.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventor: Arnab Choudhury
  • Patent number: 9998100
    Abstract: A semiconductor chip allows for a selected amount of on-die decoupling capacitance to be connected to a very-large-scale integrated circuit (VLSI) system after the circuit design is complete. The semiconductor chip comprises an integrated circuit disposed on a packaging substrate, and a power distribution network that is electrically connectable to the integrated circuit via a programmable connectivity array via the packaging substrate.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: June 12, 2018
    Assignee: Ampere Computing LLC
    Inventors: Rich Thaik, Alfred Yeung, April Lambert, Jeremy Plunkett
  • Patent number: 9992915
    Abstract: Size reduction of a power conversion device is intended. A power conversion device according to the present invention includes: a first power semiconductor module; a second semiconductor module; and a fixing member which fixes the first power semiconductor module, wherein the first power semiconductor module has a first power semiconductor device, a first case which houses the first power semiconductor device, and a first flange portion connected to the case, the second power semiconductor module has a second power semiconductor device, and a second case which houses the second power semiconductor device, the second case is connected to the first flange portion so as to provide a first flow path space for allowing a coolant to flow between the second case and the first case, and the first flange portion is fixed to the fixing member while supporting the first case and the second power semiconductor module.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: June 5, 2018
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Takahiro Shimura, Akira Matsushita, Shinichi Fujino