For Integrated Circuit Patents (Class 257/713)
  • Patent number: 12136577
    Abstract: A contiguous integrated heat spreader suitable for an integrated circuit (IC) die package. Heat spreader material may be deposited with a high throughput additive manufacturing (HTAM) technique directly upon a surface of an IC die, and over a portion of a package substrate beyond an edge of the IC die. The contiguous heat spreader may have high thermal conductivity and offer low thermal resistance in absence of any intervening thermal interface material (TIM). The contiguous heat spreader may span multiple IC die and accommodate different die heights. The heat spreader may be contiguous with multiple die. Heat spreader material may be absent where thermal breaks within the heat spreader are advantageous.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: November 5, 2024
    Assignee: Intel Corporation
    Inventors: Feras Eid, Joe Walczyk, Paul Diglio
  • Patent number: 12114468
    Abstract: A cooling device for cooling a chip, a server with such a cooling device, and a rack are disclosed. The cooling device comprises a cooling layer that is divided into multiple cooling regions; and an internal region that includes a vapor separation core. Two-phase coolant that enters a first cooling region of the cooling layer is converted to mixed fluid due to heat extracted from a corresponding region of the chip. The mixed fluid is elevated to the vapor separate core, which separates vapor from liquid in the mixed fluid. The vapor exits the cooling device while the liquid is transported to a second cooling region in the cooling layer. The cooling device can be used with a condenser in a server to form an internal server loop, and can be connected to a rack to form a main fluid loop. The two coolant recirculation loops are used together to maintain a predetermined liquid balance in the cooling device.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: October 8, 2024
    Assignee: BAIDU USA LLC
    Inventor: Tianyi Gao
  • Patent number: 12107027
    Abstract: A power module for operating an electric vehicle drive, comprising: numerous semiconductor components; a heatsink for discharging heat generated by the semiconductor components; a DC link capacitor connected in parallel to the semiconductor components; a DC link line electrically connecting the DC link capacitor to the semiconductor components; wherein the DC link line is at least partially located in a hole formed in the heatsink.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: October 1, 2024
    Assignee: ZF FRIEDRICHSHAFEN AG
    Inventor: Ake Ewald
  • Patent number: 12096693
    Abstract: Described are systems for electronic heatsink safety including a system comprising a thermoelectric generator integrated into a heatsink, where the thermoelectric generator includes a first portion exposed to ambient temperature and a second portion contacting the heatsink, and where the thermoelectric generator is configured to produce a current based on a temperature difference between the first portion and the second portion. The system further comprises a first Light Emitting Diode (LED) electrically connected to the thermoelectric generator, where the current is configured to activate the first LED.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: September 17, 2024
    Assignee: International Business Machines Corporation
    Inventors: Noah Singer, Marc Henri Coq, Dustin Demetriou
  • Patent number: 12082378
    Abstract: Thermally conductive shock absorbers for electronic devices are disclosed. An electronic device includes a housing and a hardware component positioned inside the housing. A thermally conductive shock absorber is located between an inner surface of the housing and the hardware component. The thermally conductive shock absorber including an impact absorbing material and a thermal conductive material being in contact with at least a portion of the impact absorbing material.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: September 3, 2024
    Assignee: Intel Corporation
    Inventors: Aleksander Magi, Jeff Ku, Juha Paavola, Prakash Kurma Raju
  • Patent number: 12080625
    Abstract: A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.
    Type: Grant
    Filed: August 18, 2023
    Date of Patent: September 3, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Li Fong Chong, Yee Beng Daryl Yeow, Chii Shang Hong, Azlina Kassim, Hui Kin Lit
  • Patent number: 12068218
    Abstract: A package structure includes a semiconductor package, a thermal conductive gel, a thermal conductive film and a heat spreader. The thermal conductive gel is disposed over the semiconductor package. The thermal conductive film is disposed over the semiconductor package and the thermal conductive gel. A thermal conductivity of the thermal conductive film is different from a thermal conductivity of the thermal conductive gel. The thermal conductive film is surrounded by the heat spreader.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pu Wang, Chin-Fu Kao, Szu-Wei Lu
  • Patent number: 12069795
    Abstract: Disclosed are aspects of apparatuses and methods of fitting a cooling device to a circuit board for cooling a high-power electronic component mounted on the circuit board. Cooling apparatuses, and arrangement thereof, are also described. The method provides the cooling device with a cooling surface having a cooling area for thermally connecting to a to-be-cooled surface of the electronic component. Fixing elements are provided for moving the cooling surface towards the circuit board. A distance position ā€œdā€ of the to-be-cooled surface from the circuit board is determined, and on this basis spacer elements are selected to be interposed between the cooling device and the circuit board to limit the movement by the fixing elements to a position where the cooling area is in proximity to the to-be-cooled surface.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: August 20, 2024
    Assignee: Aptiv Technologies AG
    Inventors: Frank H. Adam, Falk Rademacher
  • Patent number: 12068270
    Abstract: A semiconductor package includes a redistribution substrate, and a semiconductor chip disposed on a top surface of the redistribution substrate. The redistribution substrate includes under bump patterns laterally spaced apart from each other, a dummy pattern disposed between the under bump patterns, a passivation pattern disposed on a bottom surface of the dummy pattern, an insulating layer covering top surfaces and sidewalls of the under bump patterns and a sidewall and a top surface of the dummy pattern, and a redistribution pattern disposed on one of the under bump patterns and electrically connected to the one under bump pattern. The passivation pattern includes a different material from that of the insulating layer.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: August 20, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jongyoun Kim
  • Patent number: 12063763
    Abstract: A system for cooling a power component includes a first metal layer. A cooling layer having a first surface is in contact with a surface of the first metal layer. A second metal layer is included having a surface in contact with a second surface of the cooling layer opposite the first metal layer. The cooling layer is of a material different from that of the first metal layer and that of the second metal layer. A plurality of cooling features are embedded in the material of the cooling layer. The cooling channels are spaced apart from both the first metal layer and the second metal layer by the material of the cooling layer. An electrically conductive path connects the first metal plate to the second metal plate.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: August 13, 2024
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Jeffrey Ewanchuk, Kimberly Rae Saviers, Ram Ranjan, Ross Wilcoxon, Haley Steffen
  • Patent number: 12063858
    Abstract: The invention discloses a method and modified aerodynamic apparatuses: fluid pushers-off and fluid motion-sensors, making enable efficient implementation and use of a controllable enhanced jet-effect, either the waving jet-effect, the Coanda jet-effect, the lift-effect, the effect of thrust, the Venturi effect, and/or the de Laval jet-effect, all are controllable using the Peltier effect and/or the Seebeck effect. The modified aerodynamic apparatuses are geometrically shaped and supplied with built-in thermoelectric devices, wherein the presence of the thermoelectric devices provides for new functional properties of the modified aerodynamic apparatuses. The method solves the problem of effective control of the operation of modified aerodynamic apparatuses such as airfoil wings of a flying vehicle, convergent-divergent nozzles, loudspeakers, and detectors of acoustic waves, all of a highly-efficient functionality.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: August 13, 2024
    Assignee: SOLITON HOLDINGS CORPORATION, DELAWARE CORPORATION
    Inventor: Yuri Abramov
  • Patent number: 12062590
    Abstract: A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ting-Yu Yeh, Chia-Hao Hsu, Weiming Chris Chen, Kuo-Chiang Ting, Tu-Hao Yu, Shang-Yun Hou
  • Patent number: 12058863
    Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.
    Type: Grant
    Filed: January 24, 2023
    Date of Patent: August 6, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon Sung Kim, Byoung Il Lee, Seong-Hun Jeong, Jun Eon Jin
  • Patent number: 12057365
    Abstract: A semiconductor device includes an insulating substrate, wiring layers, heat dissipation layers, a semiconductor element, and a sealing resin. The wiring layers each have a first obverse face and a first reverse face oriented in opposite directions in a thickness direction of the substrate. The first reverse faces of the wiring layers are connected to the substrate. The heat dissipation layers each have a second obverse face oriented in the same direction as the first obverse face, and a second reverse face oriented opposite to the second obverse face in the thickness direction. The heat dissipation layers are located opposite to the plurality of wiring layers in the thickness direction with respect to the substrate. The second obverse faces of the heat dissipation layers are connected to the substrate. The semiconductor element is connected to one of the first obverse faces of the wiring layers. The sealing resin covers the substrate, the wiring layers, and the semiconductor element.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 6, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Takumi Kanda
  • Patent number: 12051635
    Abstract: In a general aspect, a packaged semiconductor device apparatus a conductive paddle, a semiconductor die coupled with the conductive paddle and a conductive clip having a first portion with a first thickness and a second portion with a second thickness. The first thickness can be greater than the second thickness. The first portion can be coupled with the semiconductor die. The device can also include a molding compound encapsulating the semiconductor die and at least partially encapsulating the conductive paddle and the conductive clip. The device can further include a signal lead that is at least partially encapsulated in the molding compound, the second portion of the conductive clip being coupled with the signal lead.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: July 30, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Maria Cristina Estacio, Elsie Agdon Cabahug, Romel N. Manatad
  • Patent number: 12050061
    Abstract: A heat sink for use in an immersion cooling system that includes a sintered powder structure enclosed in a porous enclosure. The porous enclosure has openings, e.g., formed by a mesh, with a size to help contain sintered powder particles that may be dislodged during operation of the heat sink.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: July 30, 2024
    Assignee: Aavid Thermalloy, LLC
    Inventor: Sukhvinder S. Kang
  • Patent number: 12048085
    Abstract: A power electronics module includes a heat sink structurally configured to dissipate thermal energy, an electrically-insulating layer directly contacting the heat sink, a conductive substrate positioned on and in direct contact with the electrically-insulating layer, a power electronics device positioned on and in direct contact with the conductive substrate, a printed circuit board layer that at least partially encapsulates the conductive substrate and the power electronics device, and a driver circuit component positioned on a surface of the printed circuit board layer.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: July 23, 2024
    Assignees: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC., TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Feng Zhou, Shohei Nagai
  • Patent number: 12046529
    Abstract: An array of heat-sinked power semiconductors that includes a power semiconductor and a heat sink. The power semiconductor has a power semiconductor die, a plurality of first terminals and a second terminal. The power semiconductor die has a plurality of semiconductor terminals. Each of the first terminals is electrically coupled to an associated one of the semiconductor terminals. The second terminal is a surface mount terminal and is electrically coupled to one of the first terminals. The heat sink has a heat sink body and a plurality of fins. The heat sink body has a base and an exterior surface. The base is fixedly coupled directly to the surface mount terminal. The exterior surface has a fin mount portion to which the fins extend. At least a portion of the fin-mount portion is oriented non-parallel to base.
    Type: Grant
    Filed: November 13, 2023
    Date of Patent: July 23, 2024
    Assignee: AMERICAN AXLE & MANUFACTURING, INC.
    Inventor: Jeffrey J. Ronning
  • Patent number: 12046528
    Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: July 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Patent number: 12038618
    Abstract: A first electronic device may comprise a chassis and first fins. The chassis may be configured to removably couple with a second electronic device. The first fins are configured to interleave with second fins of the second electronic device in a coupled state of the first and second electronic devices. A corrugated thermal interface device comprises folded fins. The folded fins are coupled to the first fins and are also removably couplable to the second fins in the coupled state of the first and second electronic devices. Each folded fin comprises one or more lateral walls, and the corrugated thermal interface device further comprises a plurality of spring fingers coupled to and extending at least partially in a lateral direction from the lateral walls. The spring finger contacts may be contacted and displaced by the second fins in the coupled state of the first and second electronic devices.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: July 16, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Harvey John Lunsman, Steven Dean
  • Patent number: 12033913
    Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure over the wiring substrate. The chip package structure includes a heat-spreading lid over the wiring substrate and covering the first chip structure. The heat-spreading lid includes a ring structure and a top plate. The ring structure surrounds the first chip structure. The top plate covers the ring structure and the first chip structure. The first chip structure has a first sidewall and a second sidewall opposite to the first sidewall, a first distance between the first sidewall and the ring structure is less than a second distance between the second sidewall and the ring structure, the top plate has a first opening, the first opening has a first inner wall and a second inner wall facing each other.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Shen Yeh, Che-Chia Yang, Yu-Sheng Lin, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 12033910
    Abstract: A semiconductor product in the form of a stack chip package and a method of manufacturing the same, where a plurality of semiconductor chips are stacked one on another so as to enable the exchange of electrical signals between the semiconductor chips, and where a conductive layer is included for inputting and outputting signals to and from individual chips. A stack chip package having a compact size may, for example, be manufactured by stacking, on a first semiconductor chip, a second semiconductor chip having a smaller surface area by means of interconnection structures so as to enable the exchange of electrical signals between the first and second semiconductor chips, and by using a conductive layer for inputting and outputting signals to and from individual semiconductor chips, in lieu of a thick substrate. Furthermore, heat dissipation effects can be enhanced by the addition of a heat dissipation unit.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: July 9, 2024
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Yeong Beom Ko, Dong Jin Kim, Se Woong Cha
  • Patent number: 12035477
    Abstract: An electronics module (100), especially a power electronics module, comprising a metal-ceramic substrate (1) serving as a carrier and having a ceramic element (10) and a primary component metallization (21), an insulation layer (40) directly or indirectly connected to the primary component metallization (21), and a secondary component metallization (22) which is connected to the side of the insulation layer (40) facing away from the metal-ceramic substrate (1) and is especially isolated from the primary component metallization (21) using the insulation layer (40), wherein the ceramic element (10) has a first size (L1, D1) and the insulation layer (40) has a second size (L2, D2) and a ratio of the second size (L2, D2) to the first size (L1, D1) has a value smaller than 0.8, to form an island-like insulation layer (40) on the primary component metallization (21).
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: July 9, 2024
    Assignee: ROGERS GERMANY GMBH
    Inventors: Andreas Meyer, Karsten Schmidt, Tilo Welker
  • Patent number: 12027444
    Abstract: An electronic device includes: a circuit board having a mounting face, on which an electronic component is mounted; a heat receiver including a heat receiving plate opposed to the electronic component; and a fastening mechanism that fixes the heat receiver to the circuit board. The fastening mechanism includes a receiver having a proximal end and a distal end, the receiver having a mounting hole penetrating from the proximal end to the distal end; and a fastener that is inserted into the mounting hole for fastening to the receiver to press the heat receiver. The receiver is surface-mounted on the mounting face by soldering with the proximal end facing the mounting face.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: July 2, 2024
    Assignee: LENOVO (SINGAPORE) PTE. LTD.
    Inventors: Seiji Yamasaki, Masaaki Bandoh, Shigeru Yuzawa, Hua Wang
  • Patent number: 12021016
    Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: June 25, 2024
    Assignee: Intel Corporation
    Inventors: Chandra Mohan Jha, Pooya Tadayon, Aastha Uppal, Weihua Tang, Paul Diglio, Xavier Brun
  • Patent number: 12009276
    Abstract: A semiconductor package including a lid having one or more heat pipes located on and/or within the lid to provide improved thermal management. A lid for a semiconductor package having one or more heat pipes thermally integrated with the lid may provide more uniform heat loss from the semiconductor package, reduce the risk of damage to the package due to excessive heat accumulation, and may enable the lid to be fabricated using less expensive materials, thereby reducing the costs of a semiconductor package.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Sheng Lin, Shu-Shen Yeh, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 12002728
    Abstract: An integrated radiator having a temperature gradient is disposed between a high-temperature device and a low-temperature device. The integrated radiator includes a first heat dissipation unit and a second heat dissipation unit which are integrally fixed. The first heat dissipation unit is configured to maintain the high-temperature device within a first temperature range, and the second heat dissipation unit is configured to maintain the low-temperature device within a second temperature range. A thermal conductive path of the first heat dissipation unit is isolated from a thermal conductive path of the second heat dissipation unit, and the first heat dissipation unit is physically connected to but thermally separated from the second heat dissipation unit.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: June 4, 2024
    Assignee: QKM TECHNOLOGY (DONG GUAN) CO., LTD
    Inventors: Jiang Liu, Chi Sha, Lihui Chen, Rongkui Zheng, Hui Du, Yu Lei, Bin Wang
  • Patent number: 12002795
    Abstract: A pluggable processor module includes a microprocessor package, a voltage regulator including a capacitor board, and contacts that each include a first side in contact with the microprocessor package and a second side in contact with the capacitor board. An assembly includes the pluggable processor module and a printed circuit board assembly (ā€œPCBAā€) including a module aperture that is large enough to receive the power board and narrower than the capacitor board.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: June 4, 2024
    Assignee: Google LLC
    Inventors: Houle Gan, Richard Stuart Roy, Yujeong Shim, William F. Edwards, Jr., Chenhao Nan
  • Patent number: 11997782
    Abstract: Various embodiments described herein provide a label configured for thermal conductivity and configured to pass over an edge of a printed circuit board (PCB) and attached to both sides of the printed circuit board. The label can be used with a printed circuit board that is associated with a memory sub-system, such as a memory module (e.g., solid state drive, SSD module).
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 28, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kaleb A. Wilson, Shams U Arifeen, Bradley Russell Bitz, JoĆ£o Elmiro Da Rocha Chaves, Mark A. Tverdy
  • Patent number: 11988882
    Abstract: The disclosure relates to a device for transferring heat between a second module, for example an optical transceiver module, and a first module, for example a heat sink. The device comprises a holder for holding the second module, a first unit configured to be thermally coupled to the first module, and a second unit which is urged against the second module placed in the holder by a biasing apparatus. The first and second units are thermally coupled to one another through a plurality of protrusions of the first or second unit and a plurality of complementary cavities of the other of the first and second unit.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: May 21, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Fredrik Ohlsson
  • Patent number: 11991869
    Abstract: A system is including: an overmolded layer that is placed above a top surface and below a bottom surface of a circuit board, wherein the overmolded layer exposes at least communication interfaces on the circuit board and surrounds a heat generating component on the circuit board; a conductive layer that is placed over the overmolded layer on the top surface of the circuit board, wherein the conductive layer exposes the communication interfaces of the circuit board and covers the heat generating component on the circuit board; and wherein heat from the heat generating component is transferred into the conductive layer.
    Type: Grant
    Filed: October 10, 2023
    Date of Patent: May 21, 2024
    Assignee: Lunar Energy, Inc.
    Inventors: Steven Nicholas Grolle, Gargi Kailkhura, Peter H. J. How, Charles Ingalz, Andrew Diao, Stephen Robert Bannick
  • Patent number: 11972998
    Abstract: A miniaturized and high-power semiconductor package device with its own heat-dissipating ability includes a thermal conductor, a redistribution layer, an electronic device, a molding layer, and a solder ball. The redistribution layer includes a first surface defining an opening, a second surface opposite to the first surface, and a circuit layer. The thermal conductor is disposed in the opening. The electronic device is disposed on the first surface of the redistribution layer above the thermal conductor. The molding layer is formed on the first surface and surrounding the electronic device. The solder balls are disposed on the second surface of the redistribution layer and can form electrical connections to the circuit layer.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: April 30, 2024
    Assignee: SHUNSIN TECHNOLOGY (ZHONG SHAN) LIMITED
    Inventor: Shun-Hsing Liao
  • Patent number: 11974414
    Abstract: A circuit board cooling apparatus is disclosed having a heat spreader device to be thermally coupled with a surface of the circuit board to be cooled. Also, a conforming heat transfer device is disclosed that is thermally and physically coupled with the heat spreader device to conform to a surface contour of the heat spreader device on a first side of the heat transfer device. The cooling apparatus also includes a heat transport device physically attached and thermally coupled with a second side of the heat transfer device.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 30, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ernesto Ferrer Medina, Harvey J. Lunsman, Tahir Cader, John Franz
  • Patent number: 11973005
    Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsun Wang, Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11967548
    Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, a system board configured to be electrically connected to the casing, and upper and lower cards connected to the casing for electrically connecting the casing to the system board.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Thomas Brunschwiler, Bruno Michel
  • Patent number: 11956930
    Abstract: A liquid-submersible thermal management system includes a shell, a heat-generating component, a working fluid, and at least one heat-dispersing element. The shell defines an immersion chamber where the heat-generating component is located in the immersion chamber. The working fluid is positioned in the immersion chamber and at least partially surrounds the heat-generating component so the working fluid receives heat from the heat-generating component. The at least one heat-dispersing element is positioned on exterior surface of the shell to conduct heat from the shell into the heat-dispersing element.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: April 9, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Husam Atallah Alissa, Ioannis Manousakis, Nicholas Andrew Keehn, Eric C. Peterson, Bharath Ramakrishnan, Christian L. Belady, Ricardo Gouvea Bianchini
  • Patent number: 11942503
    Abstract: An image sensor unit is disclosed that includes an array of image sensing pixels, arranged in a plurality of rows and a plurality of columns, wherein each pixel is individually addressable. Each row of pixels is controlled via a row control in communication with the row of pixels in the array via a row addressing line, and capable of selectively addressing one or more of the plurality of rows. Each column of pixels is controlled by a column control in communication with each column of pixels in the array via a column addressing line, and capable of selectively addressing one or more of the plurality of columns. A unit controller is configured to specify selective readout of one or more pixel readout signals by instructing the row and column control to address one or more specific rows and columns of the array.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: March 26, 2024
    Assignee: EASTERN BLUE TECHNOLOGIES, INC.
    Inventors: Jianjun Guo, Yin Qian
  • Patent number: 11942395
    Abstract: An apparatus including first and second substrates. The first and second substrates each include a base and at least one peripheral wall extending from the base. One of the at least one peripheral walls of the first or second substrates includes at least one well, and the other of the at least one peripheral walls of the first or the seconds substrate that does not include a well is mechanically anchored to the well. The apparatus includes a stack having a first and second end, and the stack is disposed on the base of the first and/or the second substrates at the first and/or second ends. The stack includes at least one element configured to generate energy. A method of assembling the apparatus by contacting the substrates.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: March 26, 2024
    Assignee: Ciena Corporation
    Inventors: Raphael BeauprƩ-Laflamme, Simon Savard, Lam Nguyen
  • Patent number: 11937413
    Abstract: A power electronics module includes at least one first substrate having on a first side one or more first semiconductor dies, the one or more first semiconductor dies and the at least one first substrate providing a higher power part of the power electronics module, at least one second substrate having on a first side one or more second semiconductor dies, the one or more second semiconductor dies and the at least one second substrate providing a lower power part of the power electronics module, and a common frame at least partially encasing the first and second substrates and being a monobloc part, the higher power part being configured for direct liquid cooling and the lower power part being configured for indirect cooling.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: March 19, 2024
    Assignee: Infineon Technologies AG
    Inventors: Tomas Manuel Reiter, Elvis Keli
  • Patent number: 11934048
    Abstract: An apparatus includes a photonic integrated circuit, which includes at least one splitter configured to split at least one input beam into multiple input beamlets and multiple phase modulators configured to phase-shift at least some of the input beamlets. The apparatus also includes an array of optical amplifiers configured to amplify the phase-shifted input beamlets and generate amplified beamlets. The apparatus further incudes a beam combiner configured to combine the amplified beamlets and generate an output beam. In addition, the apparatus includes a controller configured to control the phase modulators in order to adjust phasing of the phase-shifted input beamlets.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: March 19, 2024
    Assignee: Raytheon Company
    Inventors: Stephen P. Palese, Avram Bar-Cohen
  • Patent number: 11929298
    Abstract: A molded semiconductor package includes: a semiconductor die embedded in a mold compound; a first heat spreader partly embedded in the mold compound and thermally coupled to a first side of the semiconductor die; and a second heat spreader partly embedded in the mold compound and thermally coupled to a second side of the semiconductor die opposite the first side. The first heat spreader includes at least one heat dissipative structure protruding from a side of the first heat spreader uncovered by the mold compound and facing away from the semiconductor die. The mold compound is configured to channel a fluid over the at least one heat dissipative structure in a direction parallel to the first side of the power semiconductor die. Corresponding methods of production and electronic assemblies are also described.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: March 12, 2024
    Assignee: Infineon Technologies AG
    Inventors: Jo Ean Joanna Chye, Edward Fuergut, Ralf Otremba
  • Patent number: 11923268
    Abstract: Techniques and mechanisms for promoting heat conduction in a packaged device using a heat spreader that is fabricated by a build-up process. In an embodiment, 3D printing of a heat spreader successively deposit layers of a thermal conductor material, where said layers variously extend each over a respective one or more IC dies. The heat spreader forms a flat top side, wherein a bottom side of the heat spreader extends over, and conforms at least partially to, different respective heights of various IC dies. In another embodiment, fabrication of a portion of the heat spreader comprises printing pore structures that contribute to a relatively low thermal conductivity of said portion. An average orientation of the oblong pores contributes to different respective thermal conduction properties for various directions of heat flow.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Jesus Gerardo Reyes Schuldes, Shankar Devasenathipathy, Pramod Malatkar, Aravindha Antoniswamy, Kyle Arrington
  • Patent number: 11924998
    Abstract: The disclosed systems and structures are directed to providing a hybrid liquid-cooling system for at least one rack-mounted immersion case containing at least one electronic assembly submerged in dielectric immersion cooling liquid. The hybrid liquid cooling system comprises a closed-loop fluid distribution arrangement configured to circulate channelized fluid, an external cooling module configured to thermally condition the channelized fluid circulated by the closed-loop fluid distribution arrangement, a serpentine convection coil structured to internally convey channelized fluid to operatively cool ambient temperatures of the dielectric immersion cooling liquid, and one or more fluid cooling blocks arranged to be in direct thermal contact with one or more heat-generating electronic processing components of the at least one electronic assembly.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: March 5, 2024
    Assignee: OVH
    Inventors: Mohamad Hnayno, Ali Chehade, Henryk Klaba
  • Patent number: 11916045
    Abstract: A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where the device includes at least one power supply circuit.
    Type: Grant
    Filed: August 21, 2023
    Date of Patent: February 27, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 11915991
    Abstract: A semiconductor device includes a substrate, a package structure, a first heat spreader, and a second heat spreader. The package structure is disposed on the substrate. The first heat spreader is disposed on the substrate. The first heat spreader surrounds the package structure. The second heat spreader is disposed on the package structure. The second heat spreader is connected to the first heat spreader. A material of the first heat spreader is different from a material of the second heat spreader.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
  • Patent number: 11915992
    Abstract: A method for forming a package structure is provided, including forming an interconnect structure over a carrier substrate and forming a semiconductor die over a first side of the interconnect structure. A removable film is formed over the semiconductor die. The method includes forming a first stacked die package structure over the first side of the interconnect structure. A top surface of the removable film is higher than a top surface of the first stacked die package structure. The method includes forming a package layer, removing a portion of the package layer to expose a portion of the removable film, removing the removable film to form a recess, forming a lid structure over the semiconductor die and the first stacked die package structure. The lid structure has a main portion and a protruding portion disposed in the recess and extending from the main portion.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Puu Jeng, Po-Yao Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Chin-Hua Wang
  • Patent number: 11908810
    Abstract: A hybrid semiconductor device includes an interposer substrate, a semiconductor package mounted on the interposer substrate, a molding member on the package substrate covering at least a portion of the semiconductor chip and exposing an upper surface of the semiconductor chip, and a stiffener disposed on an upper surface of the interposer substrate substantially around the semiconductor package.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heungkyu Kwon, Junso Pak, Heeseok Lee
  • Patent number: 11910567
    Abstract: A liquid-submersible thermal management system includes a cylindrical outer shell and an inner shell positioned in an interior volume of the outer shell. The cylindrical outer shell has a longitudinal axis oriented vertically relative to a direction of gravity, and the inner shell defines an immersion chamber. The liquid-submersible thermal management system a spine positioned inside the immersion chamber and oriented at least partially in a direction of the longitudinal axis with a heat-generating component located in the immersion chamber. A working fluid is positioned in the immersion chamber and at least partially surrounding the heat-generating component. The working fluid receives heat from the heat-generating component.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: February 20, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Husam Atallah Alissa, Ioannis Manousakis, Nicholas Andrew Keehn, Eric C. Peterson, Bharath Ramakrishnan, Christian L. Belady, Ricardo Gouvea Bianchini
  • Patent number: 11901258
    Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 11895769
    Abstract: A module according to the present disclosure includes a circuit board, an electronic component on one of two principal surfaces of the circuit board, a connection conductor on the principal surface of the circuit board, and sealing resin on the principal surface of the circuit board. The electronic component and the connection conductor are covered with the sealing resin. The connection conductor includes a plate-shaped conductor and terminal sections. The plate-shaped conductor is disposed upright on the principal surface of the circuit board. The terminal sections extend from the plate-shaped conductor and away from the principal surface of the circuit board and are arranged side by side. Tip portions of the terminal sections are exposed at a surface of the sealing resin.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: February 6, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuya Okamoto, Takashi Haga, Masayoshi Takagi, Kazushige Sato