Abstract: A semiconductor package structure includes a package substrate, a semiconductor die, a vapor chamber and a heat dissipating device. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is electrically connected to the first surface of the package substrate. The vapor chamber is thermally connected to a first surface of the semiconductor die. The vapor chamber defines an enclosed chamber for accommodating a first working liquid. The heat dissipating device is thermally connected to the vapor chamber. The heat dissipating device defines a substantially enclosed space for accommodating a second working liquid.

Abstract: A coil built-in multilayer substrate includes a multilayer substrate, a coil, interlayer connection conductors, and gaps. The multilayer substrate includes a magnetic layer, a component-mounting land conductor provided on a first principal surface, and a terminal conductor provided on a second principal surface. The coil is provided in the magnetic layer and includes an axis extending in a direction perpendicular or substantially perpendicular to the first and second principal surfaces. The interlayer connection conductors are provided in the magnetic layer in a region inside the spiral coil. Gaps penetrate lateral surfaces of the interlayer connection conductors.

Abstract: A compliant pin fin heat sink includes a flexible base plate having a thickness of from about 0.2 mm to about 0.5 mm. A plurality of pins extends from the flexible base plate and is formed integral with the flexible base plate by forging. A flexible top plate is connected to and spaced from the flexible base plate. The plurality of pins is disposed between the flexible base plate and the flexible top plate.

Abstract: An optical module using an optical assembly for optical transmission and reception is disclosed. At least one embodiment of the present disclosure provides an optical module which can improve the productivity by enabling efficient optical alignment and optical coupling between optical devices and optical fibers in an optical transmission-reception module using a plurality of optical fibers while increasing the data transfer rate per unit module.

Abstract: Indium-based interface systems, structures, and methods for forming the same are provided. The disclosed indium-based interfaces may be formed as solid structures between two solid surfaces by providing a solid indium-based material between the two surfaces, and heating the indium-based material above its melting point while in contact with each of the two surfaces to cause the indium-based material to reflow or otherwise liquefy between the two surfaces. The indium-based material may then be cooled below its melting point to form a solid interface material structure that is positioned between and in contact with each of the surfaces.

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip attached to an upper surface of the first semiconductor chip, a silicon heat-dissipation body thermally connected to at least one of the first semiconductor chip and the second semiconductor chip, and a molding member configured to surround the first semiconductor chip and the second semiconductor chip and exposing an upper surface of the silicon heat-dissipation body.

Abstract: A semiconductor package apparatus includes a passive device that is embedded in a bottom package stiffener, and a top stiffener is stacked above the bottom package stiffener. Electrical connection through the passive device is accomplished through the stiffeners to a semiconductor die that is seated upon an infield region of the semiconductor package substrate.

Abstract: A circuit block assembly is provided that includes circuit blocks that each include a circuit board and a semiconductor element that is disposed on a first main surface of the circuit board. Moreover, each of the circuit blocks includes a metal heat spreader that is connected to the semiconductor element directly or by a thermally conductive member interposed therebetween. A thermally conductive sheet is provided that is thermally connected to the heat spreader. The thermally conductive sheet has a specific electrical resistance higher than a specific electrical resistance of the heat spreader.

Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.

Abstract: A method is disclosed for implementing a scheme to configure thermal management control for a memory device resident on a memory module for a computing platform. A method is also disclosed for implementing the configured thermal management control. In a run-time environment for a computing platform a temperature is obtained from a thermal sensor monitoring the memory module. The memory module is in a given memory module with thermal sensor configuration that includes the memory device. An approximation of a temperature for the memory device is made based on thermal information associated with the given configuration of the memory module and the obtained temperature. The configured thermal management control for the memory device is implemented based on the approximated temperature. Other implementations and examples are also described in this disclosure.

Abstract: Provided is a power chip integration module including: a first semiconductor chip; a second semiconductor chip; a wiring layer on an upper surface or a lower surface of the first semiconductor chip and the second semiconductor chip to electrically connect the first semiconductor chip and the second semiconductor chip; an internal electrode extending from an internal electrode pad on an upper surface of at least one of the wiring layer, the first semiconductor chip, the second semiconductor chip, and combinations thereof to an external solder pad formed on an installation surface of the first semiconductor chip and the second semiconductor chip; and a first molding member in a shape to surround at least a portion of the first semiconductor chip, the second semiconductor chip, and the internal electrode.

Abstract: An electrical-circuit assembly includes an electrical-device and a heat-sink. The heat-sink has a base having a first-surface and a second-surface. The first-surface is in thermal communication with the electrical-device. The heat sink also has a lid having a third-surface and a fourth-surface. The third-surface faces toward the second-surface. The heat sink also has side-walls disposed between the base and the lid extending from the second-surface to the third-surface. The base, the lid, and the side-walls define a cavity. The heat sink also has a porous-structure extending from the second-surface toward the third-surface terminating a portion of the distance between the second-surface and the third-surface thereby defining a void between the porous-structure and the third-surface. The base, the side-walls, and the porous-structure are integrally formed of a common material. The porous-structure is characterized as having a contiguous-porosity network.

Abstract: A microelectronic structure having CTE compensation for use in wafer-level and chip-scale packages, comprising a plurality of substrate tiles each having a generally planar upper surface, the upper surfaces of the tiles disposed within a common plane to provide a generally planar grid of the tiles, each respective pair of adjacent tiles having a gap disposed therebetween.

Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

Abstract: A memory heat dissipation unit is disclosed. The memory heat dissipation unit includes a main body having a first portion, a second portion and a connection portion having two lateral edges separately connected to the first and the second portion. The first and the second portion have at least one first heat-receiving section and at least one second heat-receiving section formed thereon, respectively; and the first and the second heat-receiving section are correspondingly in contact with at least one memory chip each to exchange heat with the chips and accordingly cool the same.

Abstract: A printed circuit board having conductor tracks formed on one side of a substrate. The substrate is able to be cohesively bonded at a contact face to a cover for protecting the conductor tracks. In this case, the substrate includes a step, which forms a barrier with respect to an auxiliary material for promoting the cohesive bond, in order to prevent any wetting of the conductor tracks with the auxiliary material. A sensor having a printed circuit board for use in a fuel filling level measurement system of a vehicle.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a semiconductor package. The method may be performed by attaching a first thermal conductivity layer to an upper surface of a first chip, and attaching a second thermal conductivity layer to an upper surface of a second chip. A first support substrate is attached to lower surfaces of the first chip and the second chip. A molding compound is formed over the first support substrate and laterally surrounds the first chip and the second chip. The first support substrate is replaced with a package substrate after forming the molding compound over the first support substrate.

Abstract: An apparatus includes a circuit device, a heat sink fin, and a thermal interface material layer. The thermal interface material layer is thermally coupled to the circuit device and the heat sink fin. The thermal interface material layer includes a first alloy layer, a nanometal particle layer, and a second alloy layer. The first alloy layer is thermally coupled to the circuit device. The nanometal particle layer is thermally coupled to the first alloy layer. The nanometal particle layer includes nanometal particles and an intermediate mixture.

Abstract: A control box includes a housing defining an interior, a circuit board disposed within the interior, and an input/output connector extending from the housing. The control box further includes a heat sink removably connected to the housing such that the circuit board is positioned between the housing and the heat sink. The circuit board is in contact with the heat sink.

Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.

Abstract: The module (PM1) has an architecture with 3D stacking of the electronic power switching chips (IT, ID) and comprises first and second dielectric substrates (SH, SL) that are intended to come into thermal contact with first and second heat sinks (DH, DL), respectively, at least one pair of first and second stacked electronic power switching chips (ITHS, IDHS; ITHS, IDHS) and a common intermediate substrate (SC), the first and second electronic power switching chips being sandwiched between the first dielectric substrate and the common intermediate substrate and between the common intermediate substrate and the second dielectric substrate, respectively. According to the invention, the common intermediate substrate is a metal element formed as a single piece and comprises a central portion for the implantation of the electronic power switching chips and at least one.

Abstract: A non-plated region is formed in a certain range from an end of a submount. The non-plated region is a portion where a plating layer is not provided, and thus a substrate of the submount is exposed. An intermediate layer is formed on the plating layer. Furthermore, a plating layer is formed on the intermediate layer. A semiconductor laser is formed on the plating layer. The position of an end of the semiconductor laser substantially coincides with the position of an end of the plating layer (the intermediate layer). That is, even in a case where there is a deviation between an end face of the intermediate layer and an end face of the semiconductor laser, the amount of this deviation is sufficiently smaller than the amount by which the intermediate layer is set back from an end face of the submount.

Abstract: An example device in accordance with an aspect of the present disclosure includes a first shield to provide thermal isolation between a first component and a heatsink of a second component, and to provide a cooling channel that is thermally isolated from the heatsink to receive an airflow for the first component. A second shield is to provide thermal isolation between the first shield and the heatsink, and to provide a thermal barrier region between the first shield and the second shield.

Abstract: A semiconductor device includes an integrated circuit attached to a chip carrier in a flip chip configuration. A substrate extends to a back surface of the integrated circuit, and an interconnect region extends to a front surface of the integrated circuit. A substrate bond pad is disposed at the front surface, and is electrically coupled through the interconnect region to the semiconductor material. The chip carrier includes a substrate lead at a front surface of the chip carrier. The substrate lead is electrically coupled to the substrate bond pad. An electrically conductive compression sheet is disposed on the back surface of the integrated circuit, with lower compression tips making electrical contact with the semiconductor material in the substrate. The electrically conductive compression sheet is electrically coupled to the substrate lead of the chip carrier by a back surface shunt disposed outside of the integrated circuit.

Abstract: An integrated circuit (IC) is fabricated with transistors and gated diodes having selected epitaxial growth. The transistors may be Field-Effect Transistors (FETs) for example, and more specifically, may be fin-based FETs (finFETs) where fins are fabricated, in part, using an epitaxial growth process. The IC is further fabricated with gated diodes. Selected gated diodes within the IC are fabricated using the epitaxial growth process on the fins of the gated diode to form an anode and a cathode. Other selected gated diodes are fabricated without using epitaxial growth processes to form the anode and the cathode. In still another aspect, selected gated diodes are fabricated with epitaxial growth processes on either the anode or the cathode, but not both. In an exemplary aspect, the other selected gated diodes are part of electrostatic discharge (ESD) protection circuits in an input/output (I/O) region of the IC.

Abstract: Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400° C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.

Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in the casing, and for forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The outer sidewalls of the upper portion of the casing are located between vertical planes defined by opposing outer sidewalls of the lower portion of the casing.

Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.

Abstract: Provided is a technique for improving product attachment. In a semiconductor device, the following expression is satisfied by an angle A formed by an imaginary line connecting two attachment holes together and an imaginary line connecting together a lowest point of one of two projections positioned in a surrounding portion of one of the two attachment holes and a contact point between a bulge and a heat sink, with a screw fastened to the heat sink through the one attachment hole, where M represents a vertical direction between the lower end of a body and the lower end of a case, where W represents a bulge amount of the bulge, where T represents a height of the projection, where L represents a horizontal distance from the outer peripheral end of the case to the outer peripheral end of the heat dissipation plate: 0<A<arctan((M+W?T)/L).

Abstract: A metal pallet is integrated within a circuit board using a process similar to a multilayer PCB, which integrates the metal pallet into the circuit board at the same time as the supporting layers are fabricated. The use of B-stage material provides a bonding mechanism for the metal pallet to be embedded within the circuit board, creating a cohesive integrated part. Embedding the pallet during the fabrication process, pre-lamination, generates a more robust construction and connection not impacted by post fabrication process in assembly. After assembly the circuit board with embedded metal pallet can be mounted directly on a heat sink, cool ribbon or other feature required to help remove heat. The planar back side surface provides a more robust mounting of the metal pallet than a post fabricated assembly as used in conventional techniques.

Abstract: Provided is a cooler including an upper plate configured to have a semiconductor chip to be arranged thereon, a plurality of plate-like fins arranged under the upper plate, and a coupling bar coupled to the plate-like fins. The coupling bar has a main-body portion and a plurality of comb-tooth portions protruding from the main-body portion into the flow channel, the cooler includes a plurality of openings in a plane orthogonal to an extending direction of the plate-like fins, and the openings are defined at least by the comb-tooth portions and the plate-like fins, and the openings include a first opening provided in a first flow channel that does not run below the semiconductor chip, and a second opening provided in a second flow channel that runs below the semiconductor chip, where the second opening is larger than the first opening.

Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.

Abstract: A method of manufacturing a printed circuit board includes providing a substrate having at least one resin plate and a semi-cured sheet. A through hole is formed in the substrate to accommodate a radiator having an electrically conductive layer and an electrically insulated layer. The substrate and radiator are heat pressed to fully cure the epoxy and couple the substrate and radiator together. The excess resin is removed and electrically conductive layers are plated on the board. Surface circuits and a heat dissipating pattern are then etched into the conductive layer. An LED is attached to the printed circuit board. In some embodiments, a flexible segment is formed by removing a portion of the substrate. The radiator can have an electrically insulated layer extending at least partially across a surface of an electrically insulated and thermally conductive core.

Abstract: Embodiments herein relate to a heat sink having nano- and/or micro-replication directly embossed in a bulk solidifying amorphous alloy comprising a metal alloy, wherein the heat sink is configured to transfer heat out of the heat sink by natural convection by air or forced convection by air, or by fluid phase change of a fluid and/or liquid cooling by a liquid. Other embodiments relate apparatus having the heat sink. Yet other embodiments relate to methods of manufacturing the heat sink and apparatus having the heat sink.

Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a substrate, a first die, a gasket, and a thermal interface. The first die may be connected to the substrate. The gasket may be connected to the substrate and may encircle the first die to form a space between the first die and the gasket. The thermal interface material may be located within the space formed by the first die and the gasket.

Abstract: Disclosed is a display device including: a substrate including a display area for displaying an image and a peripheral area neighboring the display area; a plurality of signal lines formed in the display area; a pad formed in the peripheral area; and a plurality of connection wires for connecting the signal lines and the pad, wherein a first connection wire and a second connection wire neighboring the first connection wire from among the plurality of connection wires are disposed on different layers, and the first connection wire and the second connection wire, which are formed to extend from the pad and are bent at least twice to have at least one being bent toward backward direction, are disposed in the peripheral area.

Abstract: An IC package, comprising a substrate and two or more vertically stacked dies disposed within the substrate, wherein all the edges of the two or more dies are aligned with respect to one another, wherein at least two dies of the two or more vertically stacked dies are coupled directly to one another by at least one wire bonded to the ones of the at least two dies.

Abstract: A heat transportation mechanism that is thermally conductive, but not electrically conductive, is provided so as to permit transportation of heat generated by a semiconductor device die to the exterior of a semiconductor device package. Embodiments can use a thermally conductive polymer structure, added to the package mold compound, to transport heat through the mold compound. The thermally conductive polymer structure can be fixed to the semiconductor device die prior to molding or can be included in an overmolding compound slug prior to performing the overmolding process. Flexibility of placement of the thermally conductive polymer structure is provided by using dielectric compounds.

Abstract: Electronic module with all-sided electromagnetic interference (EMI) shielding and methods of making same. The electronic module includes an encapsulated circuit board between a top plate and a conductive bottom plate, electrical leads extending from the circuit board through the bottom plate, and a continuous conductive coating substantially covering the entire electronic module except for a bottom surface of the bottom plate. The conductive coating forms direct, independent connections at least to the circuit board and the bottom plate. The conductive coating provides EMI shielding across the top and sides of the electronic module. The conductive bottom plate provides EMI shielding across the bottom of the electronic module. Methods of manufacturing include encapsulating a circuit board between a top plate and bottom plate, separating materials from the encapsulated circuit board to expose conductive traces on the circuit board and bottom plate, and coating the sawed device with a conductive coating.

Abstract: A package structure and method for forming the same are provided. The package structure includes a package component, and a device die formed over the package component. The device die includes a device substrate and a conductive pad over the device substrate, and the device die has a first height. The package structure also includes a dummy die formed over the package component and adjacent to the device die, and the dummy die has a second height smaller than the first height.

Abstract: A semiconductor module includes a baseplate, a cover element attached to the baseplate so that detaching the cover element from the baseplate requires material deformations, and a semiconductor element in a room defined by the baseplate and the cover element. The semiconductor element is in a heat conductive relation with the baseplate and an outer surface of the baseplate is provided with laser machined grooves suitable for conducting heat transfer fluid. The laser machining makes it possible to make the grooves after the semiconductor module has been assembled. Therefore, regular commercially available semiconductor modules can be modified, with the laser machining, to semiconductor modules as disclosed.

Abstract: A heat radiation structure includes a heat spreader provided on a heating component mounted on a substrate, a heat sink disposed at a position facing the heat spreader, a heat transfer member disposed between the heat spreader and the heat sink, and transmitting heat from the heat spreader to the heat sink, and a conductive member electrically connecting the heat spreader and the heat sink.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a conformal lid to improve the chip package assembly from deformation. In one example, a chip package assembly is provided that includes integrated circuit (IC) dies, a packaging substrate, and a lid. The packaging substrate has a die receiving area that is defined by the laterally outermost extents of the IC dies mounted to the packaging substrate. The lid a surface that includes a first region and a second region. The first region is disposed over the first IC die while the second region of the lid extends below the second surface the first IC die and is spaced above the packaging substrate. At least a portion of the second region of the lid is overlapped with the die receiving area.

Abstract: The present invention discloses a wireless device, which includes a substrate and an antenna. The antenna includes a printed antenna element and a 3-dimensional antenna element. The printed antenna element is printed on the substrate, while the 3-dimensional antenna element is disposed on the substrate and coupled to the printed antenna element. The printed antenna element and the 3-dimensional antenna element jointly have a physical length of a desired frequency.

Abstract: A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.

Abstract: A device and related method that provides a two-phase heat transfer device with a combination of enhanced evaporation and increase cooling capacity. A recess topology is used to increase suction of working fluid toward a heat source. A non-wetting coating or structure may be used to keep working fluid away from the spaces between elongated members of an evaporator and a wetting coating or structure may be used to form thin films of working fluid around the distal regions of elongated members. The devices and method described herein may be used to cool computer chips, the skin of a hypersonic flying object, a parabolic solar collector, a turbine engine blade, or other heat sources that require high heat flux.

Abstract: An electrical device that includes at least two active wafers having at least one through silicon via, and at least one unitary electrical communication and spacer structure present between a set of adjacently stacked active wafers of the at least two active wafers. The unitary electrical communication and spacer structure including an electrically conductive material core providing electrical communication to the at least one through silicon via structure in the set of adjacently stacked active wafers and a substrate material outer layer. The at least one unitary electrical communication and spacer structure being separate from and engaged to the adjacently stacked active wafers, wherein coolant passages are defined between surfaces of the adjacently stacked active wafers and the at least one unitary electrical communication and spacer structure.

Abstract: Chip on wafer on substrate structures and methods of forming are provided. The method includes attaching a first die and a second die to an interposer. The method also includes attaching a first substrate to a first surface of the first die and a first surface of the second die. The first substrate includes silicon. The first surface of the first side is opposite to the surface of the first die that is attached to the interposer, and the first surface of the second die is opposite to the surface of the second die that is attached to the interposer. The method includes bonding the interposer to a second substrate.

Abstract: Embodiments of the invention include a printed circuit board (PCB) assembly that includes advanced component in cavity (ACC) technology and methods of forming such PCB assemblies. In one embodiment, the PCB assembly may include a PCB that has a cavity formed on a first surface of the PCB. A plurality of contacts may be formed in the cavity. The cavity provides a location where components may be electrically coupled to the PCB. Additionally, a package that is mounted to the PCB may extend over the cavity. Since the package passes directly over the component, the components may be used to electrically couple the package to one or more of the contacts formed in the cavity. Accordingly, embodiments of the invention allow for the surface area used for components to be reduced, and also improves electrical performance of the PCB assembly by positioning the components proximate to the package.

Abstract: A method of fabricating a semiconductor structure. The method includes forming a dummy structure over a semiconductor body. The method further includes depositing an inter-layer dielectric (ILD) over the semiconductor body. The method further includes removing a dummy material of the dummy structure to form an opening in the ILD. The method further includes filling the opening with a dielectric material to form a dielectric structure. The method further includes stacking a plurality of interconnect elements over the dielectric structure.