Heat Dissipating Element Held In Place By Clamping Or Spring Means Patents (Class 257/718)
  • Patent number: 11367670
    Abstract: An object is to improve the productivity of a power semiconductor device. A power semiconductor device according to the invention includes a circuit portion having a conductor for transmitting a current and a power semiconductor element, a first base portion and a second base portion facing each other with the circuit portion interposed therebetween, and a transfer mold member which is in contact with the conductor and the power semiconductor element and is filled in a space between the first base portion and the second base portion. The first base portion includes a first flat portion that is connected to a peripheral edge of the first base portion, and a first bent portion that connects the first flat portion and another portion of the first base portion and is plastically deformed. The transfer mold member is integrally configured in contact with the first flat portion.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: June 21, 2022
    Assignee: HITACHI ASTEMO, LTD.
    Inventor: Nobutake Tsuyuno
  • Patent number: 11342278
    Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: May 24, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: SungWon Cho, ChangOh Kim, Il Kwon Shim, InSang Yoon, KyoungHee Park
  • Patent number: 11296272
    Abstract: A multilayer piezoelectric element includes a ceramic base body, a pair of external electrodes, multiple internal electrodes, and surface electrodes. The ceramic base body is formed by a piezoelectric ceramic. The pair of external electrodes cover a pair of end faces. The multiple internal electrodes are stacked inside the ceramic base body along a thickness direction crossing at right angles with a longitudinal direction, and connected alternately to the pair of external electrodes in the thickness direction. The surface electrodes are provided on a pair of principal faces, respectively, and are each connected to the external electrode different from the one to which the internal electrode adjacent in the thickness direction is connected. The pair of external electrodes have a higher porosity than the surface electrodes.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: April 5, 2022
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Sumiaki Kishimoto, Hiroyuki Shimizu, Tomohiro Harada, Yukihiro Konishi
  • Patent number: 11277932
    Abstract: Provided is a power conversion device, including: a semiconductor module including a semiconductor switching element; a heat sink configured to cool the semiconductor module; a spring member configured to press the semiconductor module onto the heat sink; a casing configured to accommodate the semiconductor module and the spring member; and a bridge-like structure configured to press the semiconductor module onto the heat sink through intermediation of the spring member when the casing is mounted to the heat sink.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: March 15, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kohei Seike, Ryohei Hayashi
  • Patent number: 11239400
    Abstract: A light-emitting diode (LED) array is formed by bonding an LED chip or wafer to a backplane substrate via curved interconnects. The backplane substrate may include circuits for driving the LED's. One or more curved interconnects are formed on the backplane substrate. A curved interconnect may be electrically connected to a corresponding circuit of the backplane substrate, and may include at least a portion with curvature. The LED chip or wafer may include one or more LED devices. Each LED device may have one or more electrical contacts. The LED chip or wafer is positioned above the backplane substrate to spatially align electrical contacts of the LED devices with the curved interconnects on the backplane substrate. The electrical contacts are bonded to the curved interconnects to electrically connect the LED devices to corresponding circuits of the backplane substrate.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: February 1, 2022
    Assignee: Facebook Technologies, LLC
    Inventors: Zheng Sung Chio, Daniel Brodoceanu, Oscar Torrents Abad, Ali Seng├╝l, Pooya Saketi, Jeb Wu, Chao Kai Tung, Remi Alain Delille, Tennyson Nguty, Allan Pourchet
  • Patent number: 11217529
    Abstract: A semiconductor device and method is disclosed. The semiconductor device may include a semiconductor substrate including an active area, a metal layer structure over the active area, wherein the metal layer structure is configured to form an electrical contact, the metal layer structure including a solder area, a buffer area, and a barrier area between the solder area and the buffer area, wherein, in the barrier area, the metal layer structure is further away from the active area than in the solder area and in the buffer area, and wherein each of the solder area and the buffer area is in direct contact with the active area or with a wiring layer structure arranged between the active area and the metal layer structure.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: January 4, 2022
    Assignee: Infineon Technologies AG
    Inventors: Stefan Beyer, Marius Aurel Bodea, Jia Yi Wong
  • Patent number: 11195775
    Abstract: A semiconductor module includes an insulation circuit substrate in which circuit patterns are formed on an upper surface of an insulation plate, switching elements that are arranged on an upper surface of the circuit patterns, a first heat dissipation plate that is arranged on a lower surface of the insulation plate, a casing member that surrounds a periphery of the insulation circuit substrate, the switching elements, and the first heat dissipation plate such that a lower surface of the first heat dissipation plate is exposed, and a second heat dissipation plate that is arranged on an upper surface side of the switching elements such that a prescribed gap is provided. The casing member has notch portions having a depth corresponding to a thickness of the second heat dissipation plate. At least a portion of the second heat dissipation plate engages with the notch portions.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: December 7, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeshi Kamimura
  • Patent number: 11183087
    Abstract: Systems and methods for supporting a plurality of display units are disclosed. The systems and methods may support the plurality of display units to form an overall display wall.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: November 23, 2021
    Assignee: Draper, Inc.
    Inventors: Adam Timmins, Steven E. Enochs
  • Patent number: 11171120
    Abstract: An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes a first integrated circuit die mounted on a first substrate. The second integrated circuit package includes a second integrated circuit die mounted on a second substrate. The second integrated circuit package is disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package and provide electrical signal connections between the first integrated circuit die and the second integrated circuit die. A buffer layer is disposed between the first substrate and the second integrated circuit die to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 11127651
    Abstract: In one general aspect, a package can include a first submodule including a first semiconductor die coupled to a first substrate and a first spacer, and disposed between the first spacer and the first substrate. The first submodule includes a second spacer disposed lateral to the first semiconductor die. The package includes a second submodule including a second semiconductor die coupled to a second substrate and a third spacer, and disposed between the third spacer and the second substrate. The second submodule includes a fourth spacer disposed lateral to the second semiconductor die. The package includes an inter-module layer disposed between the first submodule and the second submodule. The first spacer of the first submodule is electrically coupled to the fourth spacer of the second-submodule via the inter-module layer. The second spacer of the first submodule is electrically coupled to the third spacer of the second-submodule via the inter-module layer.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: September 21, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jie Chang, HuiBin Chen, Keunhyuk Lee, Jerome Tysseyre
  • Patent number: 11094607
    Abstract: A heatsink retainer assembly, and components of the heatsink retainer assembly, are described. The heatsink retainer assembly includes one or more heatsink anchors mounted on a heatsink retention wire between several stops. The anchors include channels to receive the retention wire such that the anchors can slide over the retention wire between the stops. The stops retain the anchors on the retention wire. The anchors can be inserted into respective mounting holes of a carrier substrate by pressing the anchors into the mounting holes on a side of the carrier substrate carrying a heat source. A heatsink can be mounted on the heat source and the retention wire can extend over the heatsink to retain the heatsink against the heat source when the anchors are secured to the carrier substrate. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 17, 2021
    Assignee: RADIAN THERMAL PRODUCTS, INC.
    Inventors: Thierry Sin Yan Too, Andrew Richard Masto
  • Patent number: 11083103
    Abstract: An electronic module includes a circuit board having a mounting surface; a heat generating component mounted on the mounting surface; a frame supporting the circuit board; a cover covering the heat generating component and the mounting surface; and a heatsink mounted on the mounting surface. The heatsink includes at least one wall including a particular wall to which the heat generating component is attached. The heatsink further includes a shade portion provided at the at least one wall. The shade portion is located between the cover and the heat generating component in a direction perpendicular to the mounting surface.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: August 3, 2021
    Assignee: BROTHER KOGYO KA BUSH IKI KAISHA
    Inventors: Taiki Hashizume, Makoto Souda
  • Patent number: 11057985
    Abstract: A printed wiring board according to an embodiment includes a wiring board body, a first connection part and a second connection part. In the first connection part, a heat-receiving front surface is a first land formed on a front surface of the wiring board body. A heat-receiving back surface is formed on a back surface of the wiring board body. A main-heat conducting part is a through-hole that inter-connects the heat-receiving front surface and the heat-receiving back surface. In the second connection part, a second land is formed on the front surface of the wiring board body. The second land is not connected to any conductor pattern formed on the back surface of the wiring board body.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: July 6, 2021
    Assignee: DENSO TEN Limited
    Inventors: Nobuhisa Katada, Kotaro Hosogi, Yasuyuki Watanabe, Toshiyuki Tanaka
  • Patent number: 10985129
    Abstract: Multiple integrated circuit (IC) devices are connected to a top side metallization surface of a multi IC device carrier. The carrier includes resin based substrate layers and associated wiring line layers. To reduce stain of the resin layers, especially in region(s) within the carrier between the IC devices, a stiffener or stiffeners are applied to the back side metallization (BSM) surface of the IC device carrier. The stiffener(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the resin layer(s), thereby mitigating the risk for cracks forming and expanding within the resin layers.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Thomas E. Lombardi, Steve Ostrander, Krishna R. Tunga, Thomas A. Wassick
  • Patent number: 10930577
    Abstract: A device for cooling a plurality of electrical components, each having a component cooling surface to be cooled, includes a first heat sink, a second heat sink, and a plurality of fasteners. The first heat sink has a first heat-sink cooling surface, and the second heat sink has a second heat-sink cooling surface. The first and second heat-sink cooling surfaces are positioned in a planar arrangement such that the first and second heat-sink cooling surfaces face each other. The first heat-sink cooling surface is configured to receive a first sub-set of the component cooling surfaces of the plurality of electrical components, and the second heat-sink cooling surface is configured to receive a second sub-set of the component cooling surfaces. The fasteners are configured to fasten the first and second heat-sink cooling surfaces to the corresponding component cooling surfaces of the plurality of electrical components to be applied.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: February 23, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Peter Taufer, Stefan Butzmann, Bernd Eckert
  • Patent number: 10903130
    Abstract: A semiconductor apparatus 1 includes a circuit substrate 3 having a circuit pattern layer 3c on an upper principal surface, semiconductor elements 4a and 4b mounted on the circuit pattern layer 3c of the circuit substrate 3, a printed substrate 6 arranged apart from the circuit substrate 3 on the upper principal surface side of the circuit substrate 3, a housing 2 mold-sealing the upper principal surface side of the circuit substrate 3, and a block 10 provided sandwiching at least part of the housing 2 and being opposite to the circuit substrate 3, the block having a linear expansion coefficient smaller than that of the housing 2.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: January 26, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoko Nakamura, Norihiro Nashida, Yuichiro Hinata
  • Patent number: 10896866
    Abstract: The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: January 19, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Toshio Hanada
  • Patent number: 10818574
    Abstract: A plug-in type power module includes a power unit and a heat-transfer unit vertically disposed on the power unit and extending outwardly away from two sides of the power unit. A first ceramic layer is disposed between the power unit and the heat-transfer unit. Therefore, heat generated by the power unit can be transferred from the first ceramic layer to the heat-transfer unit to increase the speed of heat dissipation. A subsystem having the plug-in type power module is also provided.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: October 27, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Shu-Jung Yang, Yu-Lin Chao, Chun-Kai Liu, Ming Kaan Liang, Jiin Shing Perng
  • Patent number: 10804242
    Abstract: A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Tsung-Ding Wang, Chien-Hsun Lee
  • Patent number: 10790164
    Abstract: A method for forming a package structure is provided. The method includes forming a first die over a first substrate, and injecting a molding compound material from a first side of the first die to a second side of the first die. The molding compound material includes a plurality of first fillers, each of the first fillers has a length along a longitudinal axis and a width along a transverse direction, and the length is greater than the width. The method further includes heating the molding compound material to form a package layer over the first die, and the first fillers are substantially parallel to each other.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Yi Lin, Che-Chia Yang, Kuang-Chun Lee, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 10784255
    Abstract: A diode is provided having a plate-shaped semiconductor element that includes a first side and a second side, the first side being connected by a first connecting layer to a first metallic contact and the second side being connected by a second connecting layer to a second metallic contact, the first side having a diode element in a middle area and having a further diode element in an edge area of the first side, which has crystal defects as a result of a separating process of the plate-shaped semiconductor element, the first connecting layer only establishing an electrical contact to the diode element and not to the further diode element and, on the first side, the further diode element having an exposed contact, which may be electrically contacted by the first connecting layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: September 22, 2020
    Assignee: Robert Bosch GmbH
    Inventor: Alfred Goerlach
  • Patent number: 10763183
    Abstract: A case (6) surrounds a semiconductor chip (5). A case electrode (7) is attached to an upper face of the case (6). A wire (8) is connected to the semiconductor chip (5) and the case electrode (7). A first holding portion (10) presses down the case electrode (7) on the upper face of the case (6) outside a joint portion where the wire (8) is bonded to the case electrode (7). A second holding portion (11) presses down the case electrode (7) on the upper face of the case (6) inside the joint portion. A recess (12) is formed on the upper face of the case (6). The case electrode (7) is bent such as to fit into the recess (12). The second holding portion (11) is disposed inside the recess (12).
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: September 1, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naohiro Ogushi, Koichi Taguchi
  • Patent number: 10681811
    Abstract: Embodiments of present invention provide various device assemblies for digital communication. The device assemblies may include a main printed-circuit-board (PCB); and an OSA-on-daughter-board (OODB) directly connected to the main PCB. The OODB has an optical sub-assembly (OSA) wire-bonded onto a daughter PCB. In one embodiment, the daughter PCB includes a flexible printed-circuit (FPC) sheet connecting the OODB directly to the main PCB. In another embodiment, the main PCB includes a FPC sheet connecting the main PCB directly to the OODB. In one embodiment, the connection may be made through an anisotropic conductive film or an anisotropic conductive adhesive.
    Type: Grant
    Filed: February 10, 2019
    Date of Patent: June 9, 2020
    Inventors: Tongqing Wang, Ming Ding
  • Patent number: 10667439
    Abstract: A motor drive and a discrete power component assembly. The motor drive has a motherboard; a controller; a heat sink; and a discrete power component assembly mounted to the motherboard, the discrete power component assembly includes two discrete power components, a motherboard facing plate intermediate the motherboard and the two discrete power components, the motherboard facing plate adjacent planar surfaces of the two discrete power components, and a heat sink facing plate adjacent planar surfaces of the two discrete power components which are opposite the planar surfaces adjacent the motherboard facing plate. The heat sink is secured to the motherboard with the discrete power component assembly therebetween.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 26, 2020
    Assignee: Franklin Electric Company, Inc.
    Inventors: Wei Song, Zachary K. Foster
  • Patent number: 10631399
    Abstract: An electronic module with reduced electromagnetic interference radiation includes a multilayer printed circuit board having an electrically conductive outer layer and at least one electrically conductive inner layer, an electronic component, a heat sink and a plurality of thermal plated-through holes. The electronic component is disposed on and electrically connected to the outer layer. The heat sink is thermally connected to the multilayer printed circuit board by an electrical insulation layer. Heat generated during operation of the electronic component can be dissipated to the heat sink through the plurality of thermal plated-through holes. The plurality of thermal plated-through holes do not have an electrical connection to the outer layer.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: April 21, 2020
    Assignee: Continental Automotive GmbH
    Inventor: Anton Mayer-Dick
  • Patent number: 10582644
    Abstract: A solid-state drive device includes a first module including a first region containing a volatile main memory device and a controller device and a second region containing a first nonvolatile memory device, a second module disposed on the first module and having a third region containing a second nonvolatile memory device, the second module being connected to the first module, and a heat dissipating member disposed on the second module as vertically juxtaposed with the first and second modules. The heat dissipating member has a protruding portion protruding toward the first module and in direct thermal contact with the first region, and a plate-shaped portion having a main surface in direct thermal contact with the third region.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Chul Hur, Do Il Kong
  • Patent number: 10566303
    Abstract: A transistor includes a semiconductor region provided on a substrate and three different terminal electrodes. At least one terminal electrode has an isolated electrode structure composed of a plurality of conductor patterns. A bump, which electrically connects the plurality of conductor patterns to each other, is arranged on the terminal electrode having the isolated electrode structure. A stress-relaxing layer, which is composed of a metal material containing a high-melting-point metal, is arranged between the semiconductor region of the transistor and the bump. No current path for connecting the plurality of conductor patterns to each other is arranged between the conductor patterns and the bump.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: February 18, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Atsushi Kurokawa
  • Patent number: 10553517
    Abstract: In one general aspect, a package can include a first submodule including a first semiconductor die coupled to a first substrate and a first spacer, and disposed between the first spacer and the first substrate. The first submodule includes a second spacer disposed lateral to the first semiconductor die. The package includes a second submodule including a second semiconductor die coupled to a second substrate and a third spacer, and disposed between the third spacer and the second substrate. The second submodule includes a fourth spacer disposed lateral to the second semiconductor die. The package includes an inter-module layer disposed between the first submodule and the second submodule. The first spacer of the first submodule is electrically coupled to the fourth spacer of the second-submodule via the inter-module layer. The second spacer of the first submodule is electrically coupled to the third spacer of the second-submodule via the inter-module layer.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: February 4, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jie Chang, HuiBin Chen, Keunhyuk Lee, Jerome Teysseyre
  • Patent number: 10396006
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: August 27, 2019
    Assignee: NXP USA, Inc.
    Inventors: Audel Sanchez, Lakshminarayan Viswanathan, Fernando A. Santos, Jaynal A. Molla
  • Patent number: 10334734
    Abstract: A circuit assembly includes a circuit board provided with a connection opening, a plurality of busbars provided on a back surface of the circuit board, an electronic component provided with connection terminals that are soldered to the corresponding busbar exposed through the connection opening, and a solder restricting layer that is provided between the circuit board and the plurality of busbars and includes a pattern surrounding a soldering region of the busbar to which the connection terminals are soldered.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: June 25, 2019
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Tou Chin, Arinobu Nakamura
  • Patent number: 10262919
    Abstract: A circuit board includes a heatsink configured to be coupled to the circuit board via a first coupling mechanism, the first coupling mechanism providing an asymmetrical downward force for coupling the heatsink to the circuit board. The circuit board further includes a second coupling mechanism configured to provide a counter force to the asymmetrical downward force of the first coupling mechanism. The counter force can be configured on an overhang portion of the heatsink that does not cover a circuit on the circuit board.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: April 16, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Phil Slight, Vic Chia
  • Patent number: 10211133
    Abstract: A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: February 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Grassmann, Juergen Hoegerl, Angela Kessler, Ivan Nikitin
  • Patent number: 10199302
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 5, 2019
    Assignee: NXP USA, INC.
    Inventors: Audel Sanchez, Lakshminarayan Viswanathan, Fernando A. Santos, Jaynal A. Molla
  • Patent number: 10199804
    Abstract: A busbar locating component includes: one or more first attachments configured for attaching a busbar layer to the busbar locating component; one or more bays each configured to contain and position an assembly of transistors essentially perpendicular to the busbar layer for connection; and a plurality of slots, each slot configured to contain and position a busbar relative to the busbar layer for connection.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: February 5, 2019
    Assignee: Tesla, Inc.
    Inventors: Robert James Ramm, Dino Sasaridis, Colin Campbell, Wenjun Liu
  • Patent number: 10109556
    Abstract: Apparatuses for coupling a semiconductor device to a cooling system, methods of coupling a semiconductor device to a cooling system, and systems incorporating the apparatuses are disclosed. An apparatus includes a first frame member coupled to the cooling system, a second frame member coupled via one or more fasteners to the first frame member, and a spring assembly disposed between the first frame member and the second frame member. The semiconductor device is disposed between the spring assembly and the second frame member.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: October 23, 2018
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Shailesh N. Joshi, Masao Noguchi
  • Patent number: 10064310
    Abstract: In order to efficiently cool a heat-generating semiconductor element, it is desirable to cool a power semiconductor element from both surfaces. Therefore, in order to cool multiple power semiconductor elements, it is an effective way to alternately arrange a semiconductor component having the incorporated semiconductor element and a cooling device. A power conversion device for handling a high-power voltage needs to ensure pressure resistance between semiconductor elements or circuits inside the device. It is an effective way to seal the semiconductor component with a sealing material such as a silicone gel. Therefore, it is necessary to install the semiconductor component or the circuit having the incorporated semiconductor element, in a case from which a liquid silicone gel prior to curing does not leak even if the gel is injected.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: August 28, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Hisashi Tanie, Eiichi Ide, Hiroshi Shintani, Atsuo Nishihara
  • Patent number: 10033164
    Abstract: A power line communication apparatus includes a power plug configured to connect to a power line, and a power plug receiver configured to connect to the power plug. The power line communication apparatus also includes a power line communicator configured to receive a signal transmitted through the power line, and a power supplier configured to generate power based on power received from the power plug and supply the generated power to the power line communication apparatus. The power line communication apparatus further includes a power board on which the power plug receiver is mounted, and a heat radiator that connects to the power line communicator and radiates heat generated from the power line communicator, wherein a portion of the heat radiator overlaps a portion of the power board when viewed perpendicular to the power board, and the portion of the power board does not include the power plug receiver.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: July 24, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tomohiro Morita, Yoshimi Tokunaga, Yoshinori Kaneko, Shuichi Kuriyama
  • Patent number: 10029869
    Abstract: A sheet conveyance apparatus includes a rotation unit including a shaft portion and configured to rotate by being pushed by a sheet conveyed, a sensor configured to generate a signal according to a position of the rotation unit in a rotational direction, a first supporting portion configured to rotatably support the shaft portion, a second supporting portion configured to rotatably support the shaft portion, an elastic portion connected to the shaft portion, and configured to extend in an axial direction of the shaft portion, and be elastically deformable in a direction intersecting with the axial direction of the shaft portion, a regulation portion configured to regulate a movement of the rotation unit supported by the first supporting portion and the second supporting portion in the axial direction of the shaft portion by contacting the elastic portion.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: July 24, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tadahisa Sugiyama
  • Patent number: 10028372
    Abstract: An assembly of two or more heatspreaders is attached to a printed circuit board in a compact electronic enclosure. The heatspreaders include fins which assist in convecting heat out of the enclosure through vents. The printed circuit board is shielded from the outer case by the heatspreaders.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: July 17, 2018
    Assignee: THOMSON Licensing
    Inventors: Darin Bradley Ritter, Mark Robert Anderson
  • Patent number: 9904814
    Abstract: A secure element integrated circuit may be mounted to an underside of a bus interface integrated circuit. The bus interface integrated circuit may have a plurality of external contacts and a first plurality of internal contacts. The secure element integrated circuit may have a second plurality of internal contacts coupled to the first plurality of internal contacts.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: February 27, 2018
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Donald Gonzalez
  • Patent number: 9899345
    Abstract: An electrode terminal includes: a first drawn-out part to be bonded to a main electrode; and a second drawn-out part that is formed of a plate member in a continuous fashion from one end portion to be positioned opposite to the main electrode with a gap therebetween until another end portion to be connected to an external circuit, so that a portion in the first drawn-out part that is adjacent to a portion therein to be bonded to the main electrode, is bonded to an opposing surface to the main electrode in said one end portion; wherein the first drawn-out part is formed so that the portion to be bonded to the main electrode is away from the opposing surface; and wherein an opening portion corresponding to the main electrode is formed in the second drawn-out part.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: February 20, 2018
    Assignee: MITSUBISHI ELECTRIC COOPERATION
    Inventors: Junji Fujino, Yutaka Yoneda, Shohei Ogawa, Soichi Sakamoto, Mikio Ishihara, Miho Nagai
  • Patent number: 9875951
    Abstract: A heat sink comprises a first thermally conductive base having a first face to thermally engage a heat-generating electronic component and a second thermally conductive base with a plurality of fins on a first face and a second face to engage the first base. The fins on the second base are positionable in either of two orientations relative to the heat-generating electronic component to which the heat sink is coupled. The fins are selectively placed in the orientation that best utilizes the direction of air flow available to the heat sink. The orientable fins of the heat sink afford flexibility in arranging the heat-generating electronic component on a circuit board or in arranging a circuit board within a computer chassis.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: January 23, 2018
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Troy W. Glover, Chunjian Ni, Whitcomb R. Scott, III, Mark E. Steinke
  • Patent number: 9807909
    Abstract: A socket for an electric component includes a socket body in which a contact pin is provided in a housing part and a cover member provided so as to be rotatable with respect to the socket body. The cover member has a cover member body and a heat slug in contact with an electric component. The heat slug is configured so as to move downward and press the electric component by being pressed from above by a cooling head in a state in which the cover member is closed. In a state in which the electric component is housed in the housing part, a restricting mechanism allows the downward movement of the heat slug, whereas in a state in which the electric component is not housed in the housing part, the restricting mechanism prevents the downward movement of the heat slug.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: October 31, 2017
    Assignee: ENPLAS CORPORATION
    Inventor: Shin Kobayashi
  • Patent number: 9786572
    Abstract: A contact spring for placement in a gap between an electrical substrate opposite a lid (electrically conductive heat spreader) of an electronic device comprises a spring that both conducts heat from the substrate to the lid and electrically connects the substrate and lid. The spring comprises a flat single element configured as a plurality of polygons, providing contact points, the spring substantially lying in a plane and extending substantially in a straight line, or a spiral. The spring in an electronic device such as a flip chip ball grid array having this lid and an electrical substrate with EMI emitters: (1) provides low impedance electrical connection between the electronic circuit and lid; (2) grounds the lid to the electronic circuit; (3) minimizes EMI in the electronic circuit; (4) conducts heat from the electronic circuit to the lid; or any one or combination of the foregoing features (1)-(4).
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Martin Beaumier, Yves Dallaire, Melania C. Doll, Michael Michael Gaynes, Edward J. Yarmchuk
  • Patent number: 9762137
    Abstract: In one implementation, a semiconductor package includes a first patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the first patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the first patterned conductive carrier. The semiconductor package further includes a second patterned conductive carrier having a switch node segment situated over a control source of the control FET and over a sync drain of the sync FET, as well as an inductor coupled between the switch node segment and an output segment of the second patterned conductive carrier.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: September 12, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Dan Clavette
  • Patent number: 9741714
    Abstract: An inductor structure includes a first inductor and a second inductor. The second inductor includes a loop that surrounds the first inductor. The first inductor includes a first loop and a second loop, and a crossover section coupling the first loop to the second loop so as to cause current flowing through the first inductor to circulate around the first loop in a first rotational direction and around the second loop in a second rotational direction opposite to the first rotational direction; wherein the first and second inductors are arranged in an equilibrated configuration about a first axis that bisects the inductor structure such that the first loop is on one side of the first axis and the second loop is on a second side of the first axis, such that the magnetic interaction between the inductors due to current flow in the inductors is cancelled out.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: August 22, 2017
    Assignee: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.
    Inventors: Johan Lucas Gertenbach, Anthony Lawrence McFarthing
  • Patent number: 9668384
    Abstract: A method for assembling a power conversion device is provided. The method includes mounting an electronic component on a heat-dissipating base, and electrically connecting a printed wiring board with the electronic component mounted on the heat-dissipating base.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: May 30, 2017
    Assignee: Delta Electronics (Shanghai) Co., Ltd.
    Inventors: Pei-Ai You, Xing-Xian Lu, Gang Liu, Jin-Fa Zhang
  • Patent number: 9629282
    Abstract: An electronic device includes a substrate (101), a conductor plane (104) which is provided on an inner layer of the substrate (101), an electronic circuit (102) which is mounted on the substrate (101), a heat sink (103) which is mounted on an upper surface of the electronic circuit (102), includes a portion which does not overlap with the electronic circuit (102) when seen in a plan view, faces the conductor plane (104), and is configured of a conductive material, a conductor via (105) which is connected to the heat sink (103) on a surface of the heat sink (103) contacting the electronic circuit (102), and extends toward the conductor plane (104), and a stub (106) which is connected to the conductor via (105) and extends to face the conductor plane (104).
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: April 18, 2017
    Assignee: NEC Corporation
    Inventors: Yoshiaki Kasahara, Hiroshi Toyao
  • Patent number: 9587891
    Abstract: A heat sink and mounting bracket arrangement includes a radiation fin module including a stack of radiation fins and an insertion hole located in one end of the stack of radiation fins, and a mounting bracket made from a metal plate sheet by stamping and including a bottom panel clamped on a bottom wall of the stack of radiation fins, an angled mounting panel rearwardly extending from one end of the bottom panel, a mounting slot cut through opposing top and bottom surfaces of the mounting panel for the mounting of a fastening member to affix the mounting bracket to an external substrate, and an angled plug plate forwardly extending from the bottom panel and tightly press-fitted into the insertion hole of the radiation fin module.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: March 7, 2017
    Inventor: Tsung-Hsien Huang
  • Patent number: 9583373
    Abstract: A wafer carrier includes a base having a cavity provided at the center of the base and an outer sidewall extending along and away from an edge of the base to define the cavity. The cavity is configured to be filled with an adhesive layer. The wafer carrier is configured to be bonded to a wafer with an adhesive layer in the cavity of base such that the outer sidewall faces and is in contact with an edge of the wafer and the cavity faces a center of the wafer.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: February 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jin Lee, Pil-kyu Kang, Taeyeong Kim, Byung Lyul Park, Kyu-Ha Lee, Gilheyun Choi