In Array Having Structure For Use As Imager Or Display, Or With Transparent Electrode Patents (Class 257/72)
  • Patent number: 11181361
    Abstract: A semiconductor device inspection apparatus includes: a light sensor that detects light from a semiconductor device as a DUT to which an electric signal has been input; an optical system that guides light from the semiconductor device to the light sensor; and a control device electrically connected to the light sensor. The control device includes: a data reading unit that reads mask data indicating a mask layout of the semiconductor device; a search unit that searches for a position of a transistor in the semiconductor device on the basis of polygon data of a gate layer of the semiconductor device included in the mask data; a setting unit that sets the searched position of the transistor as an optical measurement target position; and a measurement unit that performs optical measurement for the set optical measurement target position to acquire a measurement result.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: November 23, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Akira Shimase, Kazuhiro Hotta
  • Patent number: 11183521
    Abstract: A display device includes a flexible substrate, a buffer layer on the flexible substrate and including an inorganic material, a display area including a plurality of pixels on the buffer layer and each including a pixel circuit including a first thin film transistor (TFT), a second TFT, and a storage capacitor and a display device connected to the pixel circuit, and a non-display area that is adjacent to the display area. The flexible substrate includes at least one base layer, at least one inorganic barrier layer, and a shielding layer including a portion having a certain area and an opening adjacent to the portion.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: November 23, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Daewon Lee, Hyesong Kwun, Kyongtae Park, Donghoon Jeong, Kyusik Cho
  • Patent number: 11183546
    Abstract: A thin film transistor and its manufacturing method, a display panel, and a display device are provided. The thin film transistor includes an insulating layer on an active layer; the insulating layer includes m sub-insulating layers which are alternately stacked, and any two adjacent sub-insulating layers in the m sub-insulating layers have different refractive indexes, and m is an integer not less than 2.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: November 23, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Chuni Lin
  • Patent number: 11183518
    Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: November 23, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yu-Gwang Jeong, Hyun Min Cho, Su Bin Bae, Shin Il Choi, Sang Gab Kim
  • Patent number: 11181788
    Abstract: The present invention provides a display panel including a plurality of sub-pixels. Each of the sub-pixels includes a main region and a sub-region. Each of the sub-pixels includes pixel electrodes disposed in the main region and the sub-region. Each of the pixel electrodes includes a backbone portion and a plurality of branch portions connected to the backbone portion. One of the sub-pixels in each of the pixel units includes a shared electrode and a light shielding layer. The shared electrode extends from the main region of the one of the sub-pixels to the sub-region of the one of the sub-pixels. The light-shielding layer is disposed in the main region and the sub-region of the one of the sub-pixels.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: November 23, 2021
    Inventors: Yinfeng Zhang, Yunglun Lin, Xuan Li, Yihe Zhang, Wu Cao
  • Patent number: 11183515
    Abstract: A display device may include a thin film transistor disposed on a substrate, and a display element electrically connected to the thin film transistor. The thin film transistor may include an active pattern including polycrystalline silicon, a gate insulation layer disposed on the active pattern, and a gate electrode disposed on the gate insulation layer. An average value of grain sizes of the active pattern may be in a range of about 400 nm to about 800 nm. An RMS value of a surface roughness of the active pattern may be about 4 nm or less. A method of manufacturing a polycrystalline silicon layer may include cleaning an amorphous silicon layer with hydrofluoric acid, rinsing the amorphous silicon layer with hydrogenated deionized water, and irradiating the amorphous silicon layer with a laser beam having an energy density of about 440 mJ/cm2 to about 490 mJ/cm2.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: November 23, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong-Sung Lee, Jongoh Seo, Byung Soo So, Dong-min Lee, Yeon Hee Jeon, Jonghoon Choi
  • Patent number: 11175554
    Abstract: A liquid crystal display (LCD) panel is provided and includes: a plurality of data lines, a plurality of scan lines, and a plurality of pixel units formed from the data lines and the scan lines. Each of the pixel units is formed from three sub-pixel units. Each of the sub-pixel units has half of a star-shaped structure or half of a square doughnut-shaped structure. A plurality of first light-shielding electrodes and a plurality of second light-shielding electrodes are parallelly arranged on the data lines in an array manner, are respectively connected to a high potential and a low potential, and are alternately disposed.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 16, 2021
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Yinfeng Zhang
  • Patent number: 11177293
    Abstract: A fabricating method of an array substrate includes: forming a first semiconductor pattern and a first insulating layer on a substrate; forming a first gate pattern and a second gate pattern isolated from each other; forming a second insulating layer; forming a second semiconductor pattern; forming a first metal pattern and a second metal pattern and a third metal pattern respectively lap-jointed with the second semiconductor pattern; forming a third insulating layer; and forming a first via hole, a second via hole, first source and drain electrodes, and second source and drain electrodes, where the first source and drain electrode are respectively connected to the first semiconductor pattern through the first via hole, and the second source and drain electrodes are respectively connected to the second semiconductor pattern through the second via hole.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: November 16, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Haixu Li, Jianguo Wang
  • Patent number: 11177297
    Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a base substrate and a thin film transistor on the base substrate; a light shielding layer is disposed between the thin film transistor and the base substrate, and the light shielding layer includes a light shielding metal layer and a light reflection adjusting layer which are stacked on the base substrate, the light reflection adjusting layer covers the light shielding metal layer, and a reflectance of the light reflection adjusting layer is lower than a reflectance of the light shielding metal layer.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: November 16, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Bin Zhang, Yu Cheng Chan, Tingting Zhou, Xiaolong He
  • Patent number: 11171160
    Abstract: An array substrate, a method of manufacturing the same, and a display panel are provided. The method includes: providing a base substrate including a display area and a wiring area at a periphery of the display area; in the process of forming a connection electrode in the wiring area, remaining a first photoresist layer for performing the patterning process and covering the connection electrode; depositing a film of reflective pixel electrode layer on the base substrate and performing a patterning process on the film of reflective pixel electrode layer to form a reflective pixel electrode layer in the display area and to remove the film of reflective pixel electrode layer in the wiring area to expose the first photoresist layer; removing a second photoresist layer for patterning the thin film of reflective pixel electrode layer on the reflective pixel electrode layer with the first photoresist layer in the wiring area.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 9, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Lei Su, Zhengdong Zhang, Gang Zhou, Xiaofei Yang, Ke Dai
  • Patent number: 11164895
    Abstract: The present disclosure relates to an array substrate, a method for manufacturing the same, a display panel, and a display device. The array substrate includes: a gate metal layer, disposed on the substrate and the gate metal layer including a grounding wire located in the peripheral region; a gate insulating layer, at least covering the gate metal layer; and a conductive layer structure, disposed over the gate insulating layer and including an auxiliary grounding wire located in the peripheral region, wherein the auxiliary grounding wire is connected to the grounding wire. The present disclosure can prevent ESD more effectively.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: November 2, 2021
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Xiaofang Gu, Xiaoye Ma, Xiping Wang
  • Patent number: 11163204
    Abstract: An array substrate, a display panel including the same, and a display device are provided. The array substrate includes: a base substrate and a planarization layer on the base substrate. A first conductive layer is disposed on a side of the planarization layer away from the base substrate. A first passivation layer is disposed on a side of the first conductive layer and the side of the planarization layer not being covered by the first conductive layer, away from the base substrate, and provided with a plurality of stress release openings. An insulating layer is disposed in the stress release openings and on a side of the first passivation layer away from the planarization layer. A second conductive layer is disposed on a side of the insulating layer away from the planarization layer.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: November 2, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hong Liu, Yezhou Fang, Fengguo Wang, Xinguo Wu, Zhixuan Guo, Haidong Wang, Liang Tian, Kai Li, Bo Ma
  • Patent number: 11156884
    Abstract: Provided is a light transmissive-type liquid crystal display device including a first substrate, a second substrate, and a liquid crystal layer, wherein the first substrate includes a base member, a wiring, a switching element, a pixel electrode, and a first insulator having translucency, the first insulator overlapping in the plan view with the wiring and being arranged between the base member and the pixel electrode, a second insulator having translucency, the second insulator overlapping in the plan view with the pixel electrode and being arranged between the base member and the pixel electrode to be in contact with the first insulator, the second insulator having a refractive index higher than a refractive index of the first insulator, and a light-shielding body provided along an outer periphery of a surface of the second insulator on the base member side, the light-shielding body being arranged in contact with the second insulator.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: October 26, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Satoshi Ito
  • Patent number: 11158655
    Abstract: A display device is disclosed. In one aspect, the display device includes a substrate including a display area, the display area including a plurality of pixels configured to display an image and a pad area adjacent to the pad area and configured to transfer electrical signals. At least a portion of the pad area is bendable. The display device also includes an insulating layer formed over the substrate and including a bending groove in the pad area. The bending groove includes a sidewall. A plurality of peripheral wires is formed over the insulating layer, and a cutoff portion is connected to the sidewall and disposed between adjacent peripheral wires.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: October 26, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Won Kyu Kwak, Jae Yong Lee
  • Patent number: 11152511
    Abstract: A thin-film transistor and a display panel are provided in which current characteristics of the thin-film transistor are improved by a dual gate electrode structure, and the output characteristics of the thin-film transistor are improved by dividing the top gate electrode (or bottom gate electrode) of the dual gate electrode into two electrodes and applying a back bias voltage to the top gate electrode adjacent to a source region. A high-resolution display panel or a transparent display panel is realized by increasing the aperture ratio (or transmittance) of the display panel using the highly integrated high-current device.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: October 19, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: SunWook Ko, KumMi Oh
  • Patent number: 11150524
    Abstract: According to one embodiment, a display device includes a base substrate, a switching element including a semiconductor layer, a power supply line, a pixel electrode electrically connected to the switching element, a capacitance electrode positioned between the base substrate and the pixel electrode and electrically connected to the power supply line, a first interlayer insulating film positioned between the pixel electrode and the capacitance electrode, a common electrode, and an electrophoretic element positioned between the pixel electrode and the common electrode. An edge of the capacitance electrode overlaps the pixel electrode over the entire periphery thereof.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: October 19, 2021
    Assignee: Japan Display Inc.
    Inventors: Yoshitaka Ozeki, Tadayoshi Katsuta, Koji Ishizaki, Takahiro Takeuchi, Koshiro Moriguchi
  • Patent number: 11144094
    Abstract: A display device includes a lower substrate that includes a side surface having a first inclined surface. An upper substrate is disposed on the lower substrate and includes a side surface having a second inclined surface. A first electrode is disposed on a surface of at least one of the lower substrate or the upper substrate. An auxiliary electrode is disposed on the first inclined surface of the lower substrate and the second inclined surface of the upper substrate. The auxiliary electrode includes a first portion corresponding to the first inclined surface, a second portion corresponding to the second inclined surface, and a bent portion bent at a predetermined angle with respect to the first and second inclined surfaces. The first electrode may be in contact with the bent portion on the first exposed surface to electrically connect to the auxiliary electrode.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 12, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Young-Cheol Jeong
  • Patent number: 11145649
    Abstract: A semiconductor device with low parasitic capacitance comprises a substrate. The semiconductor device also comprises a gate region on the substrate. The semiconductor device further comprises a contact region on the substrate, wherein the contact region comprises a first portion and a second portion, wherein the first portion is in contact with the substrate and has a first surface above the substrate, and wherein the second portion is in contact with the substrate and has a second surface above the substrate different from the first surface.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: October 12, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Haining Yang, Junjing Bao
  • Patent number: 11139316
    Abstract: The present disclosure provides an LTPS array substrate and a method for manufacturing the same. The method includes forming a polysilicon pattern by a first mask process; performing a doping treatment on the polysilicon pattern and forming a gate electrode by a second mask process; forming a source electrode through-hole and a drain electrode through-hole and a pixel electrode by a third mask process; forming a source electrode and a drain electrode and a touch control signal line by a fourth mask process; forming a touch control electrode through-hole by a fifth mask process; and forming a touch control electrode by a sixth mask process.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: October 5, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Chao Tian, Juncheng Xiao
  • Patent number: 11133333
    Abstract: A thin film transistor according to an embodiment of the present invention includes: a gate electrode supported by a substrate; a gate insulating layer covering the gate electrode; a silicon semiconductor layer being provided on the gate insulating layer and having a crystalline silicon region, the crystalline silicon region including a first region, a second region, and a channel region located between the first region and the second region, such that the channel region, the first region, and the second region overlap the gate electrode via the gate insulating layer; an insulating protection layer disposed on the silicon semiconductor layer so as to cover the channel region and allow the first region and the second region to be exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region. The channel region is lower in crystallinity than the first region and the second region.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 28, 2021
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Yuta Sugawara, Masakazu Tanaka, Nobutake Nodera, Takao Matsumoto
  • Patent number: 11133367
    Abstract: A thin film transistor includes: a substrate base; a first gate electrode at a side of the substrate base; an active layer at a side of the first gate electrode away from the substrate base; a second gate electrode at a side of the active layer away from the substrate base; and a source/drain electrode at a side of the second gate electrode away from the substrate base. An orthographic projection of the source/drain electrode on the substrate base is at least partially overlapped with an orthographic projection of the second gate electrode on the substrate base.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 28, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ling Wang, Yicheng Lin, Cuili Gai, Pan Xu
  • Patent number: 11133419
    Abstract: An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: September 28, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11133196
    Abstract: A gate electrode and a method for manufacturing the same, and a method for manufacturing an array substrate are provided. The method for manufacturing a gate electrode may include: providing a substrate, wherein the substrate includes a gate electrode region and a non-gate electrode region; and forming a gate electrode layer on the substrate, wherein the gate electrode layer includes a conductive portion corresponding to the gate electrode region and a transparent portion corresponding to the non-gate electrode region. According to the gate electrode and the method for manufacturing the same, and the method for manufacturing an array substrate, step difference can be eliminated, thereby avoiding an influence of the step difference on the crystallization property of a polysilicon material when an Excimer Laser Annealing (ELA) process is performed on the amorphous silicon layer, and obtaining a better crystallization effect.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: September 28, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Bin Zhang, Chienhung Liu, Yucheng Chan, Xuefei Sun, Tingting Zhou
  • Patent number: 11126045
    Abstract: A curved display panel and a display device. The curved display panel (400) includes a substrate; the substrate includes a pixel region, an integrated circuit region, and a fan-out region located between the pixel region and the integrated circuit region. The pixel region includes signal lines. The integrated circuit region includes an integrated circuit driver. A driving chip is provided in the integrated circuit driver. The fan-out region includes a fan-out line. The wiring parameters of the fan-out line and the signal line change along with the change of a target curvature of the substrate where the fan-out line and the signal line are located.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: September 21, 2021
    Assignees: HKC Corporation Limited, Chongqing HKC Optoelectronics Technology Co., Ltd.
    Inventor: Yu-Jen Chen
  • Patent number: 11127935
    Abstract: Disclosed are a display panel, a preparation method thereof and a display device. The display panel includes a display region and a non-display region. The preparation method includes: providing a base substrate; preparing a first metal layer on a side of the base substrate; preparing a first insulation layer on a side of the first metal layer; performing a patterning process on the first insulation layer by using a mask plate to form a plurality of first via holes; preparing a passivation layer on a side of the first insulation layer; performing the patterning process on the passivation layer by using the same mask plate to form a plurality of second via holes, where a vertical projection of each of the first via holes on a plane where the base substrate is located covers a vertical projection of one of the second via holes on the plane.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: September 21, 2021
    Assignee: Shanghai AVIC OPTO Electronics Co., Ltd.
    Inventor: Wenjun Dai
  • Patent number: 11127808
    Abstract: An active device substrate and a manufacturing method thereof are provided. The active device substrate includes a substrate, first and second scan lines, a data line, first and second active devices and first and second pixel electrodes. The first active device includes a first semiconductor channel layer, a first gate, a first source and a first drain. The first gate is electrically connected to the first scan line. The first pixel electrode is electrically connected to the first drain. The second active device includes a second semiconductor channel layer, a second gate and a second drain. The first semiconductor channel layer is connected to a source region of the second semiconductor channel layer. The first semiconductor channel layer and the second semiconductor channel layer belong to same layer. The second gate is electrically connected to the second scan line. The second pixel electrode is electrically connected to the second drain.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: September 21, 2021
    Assignee: Au Optronics Corporation
    Inventors: Ming-Yao Chen, Kuo-Yu Huang, Wen-Yi Hsu
  • Patent number: 11121205
    Abstract: A display panel measures a contact resistance of an adhesive portion to evaluate adhesion quality of an integrated circuit mounted thereon. The display panel includes a plurality of light-emitting elements, a first pad part including a plurality of first effective pads electrically connected to the light-emitting elements, and n (n being a natural number equal to or greater than 2) first measuring pads insulated from the light-emitting elements, a conductive adhesive film on the first pad part and including a plurality of conductive balls, an integrated circuit on the conductive adhesive film, and including an internal line electrically connected to the first measuring pads by the conductive balls, and a second pad part including a plurality of second effective pads electrically connected to the first effective pads, and 2n second measuring pads electrically connected to the first measuring pads.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: September 14, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Daegeun Lee, Kyung-Mok Lee, Wuhyen Jung
  • Patent number: 11119536
    Abstract: Provided are a flexible electronic device and a manufacturing method thereof. The flexible electronic device (200) comprises a flexible substrate (210) and a device layer formed on the flexible substrate (210). The device layer comprises a semiconductor structure (220) and a wire structure (230) connected to the semiconductor structure, the wire structure (230) having an extension direction same to a channel direction of the semiconductor structure (220). The extension direction of the first wire structure (230) forms an included angle smaller than 90° with respect to a stretching direction of the flexible substrate (210).
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: September 14, 2021
    Assignees: KUNSHAN NEW FLAT PANEL DISPLAY TECHNOLOGY CENTER CO., LTD., KUNSHAN GO-VISIONOX OPTO-ELECTRONICS CO., LTD.
    Inventors: Qi Shan, Kun Hu, Li Lin, Shixing Cai, Shengfang Liu
  • Patent number: 11121213
    Abstract: A method includes forming isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a hard mask strip over the isolation regions and a semiconductor strip, wherein the semiconductor strip is between two neighboring ones of the isolation regions. A dummy gate strip is formed over the hard mask strip, wherein a lengthwise direction of the dummy gate strip is perpendicular to a lengthwise direction of the semiconductor strip, and wherein a portion of the dummy gate strip is aligned to a portion of the semiconductor strip. The method further includes removing the dummy gate strip, removing the hard mask strip, and recessing first portions of the isolation regions that are overlapped by the removed hard mask strip. A portion of the semiconductor strip between and contacting the removed first portions of the isolation regions forms a semiconductor fin.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen
  • Patent number: 11114649
    Abstract: A light-emitting display device is provided. The light-emitting display device includes a first substrate, a first electrode layer on the first substrate, a bank layer that has openings exposing part of the first electrode layer, an emissive layer on the first electrode layer, bank grooves formed by recessing the bank layer, a second electrode layer on the emissive layer, and a low-reflectivity layer that lies on the second electrode layer and is positioned to correspond to the bank grooves.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 7, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Dongyoung Kim, Changhwa Jun, Yongbaek Lee, Jang Jo, Jiho Ryu, Hyejin Gong, Yeonsuk Kang
  • Patent number: 11114468
    Abstract: A thin film transistor (TFT) array substrate is provided. The TFT array substrate includes a display device plate and a semiconductor layer disposed on the display device plate. A thickness of the semiconductor layer is less than or equal to 35 nm.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: September 7, 2021
    Inventors: Xin Zhang, Lisheng Li, Peng He
  • Patent number: 11107877
    Abstract: An organic light emitting diode display includes: a substrate including a display area and a non-display area adjacent to the display area; a pixel thin film transistor positioned in the display area of the substrate; a first data wire positioned on the pixel thin film transistor; a second data wire positioned on the first data wire; an organic light emitting element positioned on the second data wire and electrically connected to the pixel thin film transistor through the first data wire and the second data wire; a circuit unit positioned in the non-display area of the substrate and including a circuit thin film transistor electrically connected to the pixel thin film transistor; and a common power supply line overlapping at least part of the circuit unit, electrically connected to the organic light emitting element, and formed on a same layer as the second data wire.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 31, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyong Tae Park, Sung Ho Cho, Seong Yeun Kang
  • Patent number: 11107759
    Abstract: A chip package includes a lower substrate, a first silicon nitride substrate, a bonding layer, an upper substrate, a first functional layer, a transparent conductive layer, an isolation layer, and a first conductive pad. The supporting layer is located between the lower substrate and the first silicon nitride substrate, and is made of a material including Benzocyclobutene (BCB). The upper substrate is located on the first silicon nitride substrate. The first functional layer is located between the upper substrate and the first silicon nitride substrate. The transparent conductive layer is located on the upper substrate. The isolation layer covers the upper substrate and the transparent conductive layer. The first conductive pad is located in the isolation layer and in electrical contact with the transparent conductive layer.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 31, 2021
    Assignee: XINTEC INC.
    Inventors: Wei-Luen Suen, Jiun-Yen Lai, Hsing-Lung Shen, Tsang-Yu Liu
  • Patent number: 11108024
    Abstract: A display apparatus includes a display panel having a display unit. A touch sensor layer is disposed on the display panel. A window layer is disposed on the touch sensor layer. The window layer has a first refractive index and includes a first surface and a second surface opposite the first surface. An insulation layer is disposed between the window layer and the touch sensor layer. The insulation layer has a second refractive index that is greater than the first refractive index.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: August 31, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Chulhyun Choi, Hyungue Song
  • Patent number: 11101294
    Abstract: An array substrate includes pixel electrodes, switching components, a line, a common electrode, and a common line. The switching components are connected to the pixel electrodes. The line is connected to the switching components. The common electrode includes common electrode segments provided for the pixel electrodes, respectively. The common electrode segments are disposed to overlap at least sections of the pixel electrodes, respectively, via an inter-electrode insulator but not to overlap the line. The common line extends to straddle the common line segments. The common line is connected to the common electrode segments. The common line is a section of a conductive film that includes a section configured as the line.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: August 24, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Masahiro Yoshida
  • Patent number: 11099615
    Abstract: A display panel, a manufacturing method thereof, and a display device are provided. The display panel includes: a display substrate, a COF film disposed on a side of the display substrate; a plurality of signal lines disposed on another side of the display substrate, an insulation layer located between the signal lines and the display substrate, a plurality of connection holes penetrating at least the display substrate, the signal lines and the insulation layer and a conductive material filled in the connection holes. The signal lines are connected to connection terminals disposed on the COF film by the conductive material; the insulation layer has recesses each of which surrounds the respective connection holes.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: August 24, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Benlian Wang, Xiangdan Dong, Weiyun Huang, Young Yik Ko
  • Patent number: 11094721
    Abstract: The present disclosure provides a method for manufacturing an array substrate, an array substrate, and a display device. The method for manufacturing the array substrate includes: forming a light-shielding layer and a buffer layer in sequence on a base substrate; forming an active layer on the buffer layer, and forming a first via hole in the active layer; forming an interlayer dielectric layer on the active layer; forming a second via hole in the interlayer dielectric layer at a position corresponding to the first via hole and a third via hole in the buffer layer at a position corresponding to the first via hole by a single patterning process; forming a source/drain electrode layer on the interlayer dielectric layer, in which the source/drain electrode layer is electrically connected to the light-shielding layer through the second via hole, the first via hole and the third via hole in sequence.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 17, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Song, Guoying Wang
  • Patent number: 11094752
    Abstract: A display panel and a preparation method thereof, the display panel includes a substrate layer, a passivation layer, a plurality of color resisting units, a plurality of anodes, a pixel definition layer, a light emitting layer and a cathode. The present disclosure through makes at least one of the color resisting units partially cover a projection of the light emitting layer on the color resisting units to overcome the problem that part of the light emitted from the light emitting layer passing through the color resistance unit for adjusting a color gamut, and the brightness of part of the unadjusted light will not lost, thus, at last, the display panel has lack of display brightness due to adjusting the color gamut of the display and using the color resistance unit.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 17, 2021
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Kunpeng He, Jia Tang
  • Patent number: 11094904
    Abstract: A light emitting display apparatus includes a substrate, a first planarization layer on the substrate, a metal layer having an uneven surface and disposed on the first planarization layer, a second planarization layer covering the metal layer on the first planarization layer, and a light emitting element on the second planarization layer, wherein the second planarization layer is disposed between a bottom layer of the light emitting element and the metal layer so as to separate the bottom layer of the light emitting element from the metal layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: August 17, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventor: NamSu Kim
  • Patent number: 11088078
    Abstract: A semiconductor device includes a substrate, a semiconductor layer positioned above the substrate, and a blocking structure positioned between the substrate and the semiconductor layer. A dimension of the blocking structure is greater than a dimension of the semiconductor layer. The blocking structure may suppress diffusion of impurities from layers below the blocking structure.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: August 10, 2021
    Assignee: Nanya Technology Corporation
    Inventor: Chin-Ling Huang
  • Patent number: 11088129
    Abstract: A display apparatus includes a substrate, a first circuit layer, a first adhesive layer, a second circuit layer, a first conductive element and a display element layer. The first circuit layer is disposed on the substrate. The first adhesive layer is disposed on the first circuit layer. The second circuit layer is disposed on the first adhesive layer. The first conductive element is disposed on the second circuit layer and is electrically connected to the second circuit layer. The first adhesive layer has a first via, and the first conductive element is electrically connected to the first circuit layer through the first via of the first adhesive layer. The display element layer is disposed on the second circuit layer and is electrically connected to the second circuit layer.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 10, 2021
    Assignee: Au Optronics Corporation
    Inventor: Tsung-Ying Ke
  • Patent number: 11088233
    Abstract: A display device includes hole patterns of upper and lower conductive layers that are disposed in a peripheral area of the display device and are asymmetric with respect to an opening of an insulating layer of the display device. A first one of the hole patterns may coincide with a second one of the hole patterns in a part of the peripheral area, while the first one of the hole patterns may cross the second one of the hole patterns in another part of the peripheral area.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Youngtaeg Jung, Wonkyu Kwak, Wonmi Hwang, Jaewon Cho, Geurim Lee
  • Patent number: 11081504
    Abstract: The present invention provides a display device, including: a display region; a non-display region surrounding the display region; multiple signal lines distributed in the display region; multiple drive chips distributed in the non-display region, each of the drive chips being provided with at least one signal output end; and at least one fan-out line, one end of each fan-out line being connected to the signal output end of one of the drive chips, the other end of each fan-out line being connected to each signal line. The at least one fan-out line is entirely or partially placed over the drive chips. The invention can effectively solve the problems of low reliability of left and right bezels of the display panel and weak antistatic capability, and can make the left and right bezel narrower.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: August 3, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yantao Lu
  • Patent number: 11081066
    Abstract: An electro-optic display including an array of pixel electrodes, where each row of pixel electrodes is associated with a source line, and that source line is connected to a drive chip with a T-wire that connects from the back of the substrate to the front of the substrate through a via. The vias are spaced out, such as in a zig-zag pattern or a pseudo-random pattern to reduce the capacitive coupling between the T-wires when adjacent pixels are driven, for example when presenting text characters.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: August 3, 2021
    Assignee: E Ink Corporation
    Inventors: Chih-Hsiang Ho, Yi Lu, Yuval Ben-Dov, Teck Ping Sim
  • Patent number: 11075362
    Abstract: A display panel includes a base substrate including a front surface and a rear surface and having first and second holes, and a pixel layer on the base substrate. A display area is defined in the front surface. The first hole overlaps with the display area and penetrates the front and rear surfaces. The second hole overlaps with the display area, is adjacent to the first hole, and is recessed from the front surface. The base substrate includes a first base layer including the rear surface, a first barrier layer on the first base layer and including first inorganic films having a first refractive index, and second inorganic films having a second refractive index, a second base layer on the first barrier layer, and a second barrier layer on the second base layer and including the front surface. The first and second inorganic films are alternately stacked.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: July 27, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Junghan Seo, Wooyong Sung
  • Patent number: 11069876
    Abstract: An organic electroluminescence display device has a plurality of pixels, each of the pixels including a first portion and a second portion. The first portion has an organic light emitting element and is configured to display images. The second portion is a transparent transmission area through which an external object is visible and includes a foreign substance collecting member. The foreign substance collecting member is made of a ferromagnetic substance and is configured to receive electric current from an external current source through a connecting line and an electric field application pad. When electric current is applied to the electric field application pad, a magnetic field is applied to the foreign substance collecting member, and foreign substance in the first portion is collected by the foreign substance collecting member in the second portion, preventing the foreign substance from being deposited in the first portion.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: July 20, 2021
    Assignee: LG Display Co., Ltd.
    Inventor: Sungsoo Gil
  • Patent number: 11068029
    Abstract: A flexible display apparatus includes a flexible substrate including an active area and an inactive area, the inactive area including a first area disposed adjacent to the active area, a second area where a circuit board is disposed, and a bending area disposed between the first area and the second area, a first support layer disposed beneath the active area and the first area, and a second support layer disposed beneath the second area, and a guide disposed at a lower surface of the flexible substrate. The guide includes a first section and a second section. The first section is on a lower surface of the first support layer. The second section is disposed to cover a portion of the substrate that extends from the bending area. Accordingly, defects generated during bezel bending are reduced.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: July 20, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Hae-Yong Jeong, Dong-Soo Shin
  • Patent number: 11063093
    Abstract: An organic light emitting diode display device includes a substrate, a buffer layer, a first circuit structure, a sub-pixel structure, and a first signal wire. The substrate includes a display region including a plurality of sub-pixel regions and a peripheral region surrounding the display region. The buffer layer is disposed in the display region and peripheral region on the substrate. The first circuit structure is disposed in the peripheral region on the buffer layer. The sub-pixel structure is disposed in each of the sub-pixel regions on the first circuit structure. The first signal wire is disposed in the peripheral region between the substrate and the buffer layer, and overlaps the first circuit structure when viewed from a plan view in a thickness direction of the substrate.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Heena Kim, Myounggeun Cha, Sang Jin Park, Young Seok Baek
  • Patent number: 11063068
    Abstract: A display apparatus includes a substrate having a first substrate, a second substrate, and an inorganic insulating layer between the first substrate and the second substrate. A first buffer layer is on the substrate, wherein the first buffer layer includes n+1 layers, and ‘n’ is 0 or an even number. A first thin film transistor, a second thin film transistor, and a storage capacitor are each on the first buffer layer. The first thin film transistor includes a first active layer formed of a low temperature poly silicon material. The second thin film transistor includes a second active layer formed of an oxide semiconductor material. The storage capacitor includes a first capacitor electrode and a second capacitor electrode.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: July 13, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: JinChae Jeon, SoYoung Noh, UiJin Chung, Eunsung Kim, HyunSoo Shin, Wonkyung Kim, Jeihyun Lee
  • Patent number: 11063128
    Abstract: A semiconductor device includes a fin having a first semiconductor material, the fin having a source/drain (S/D) region and a channel region, the S/D region providing a top surface and two sidewall surfaces; an isolation structure surrounding a bottom portion of the fin, wherein the S/D region of the fin above the isolation structure has a step profile in each of the two sidewall surfaces; a semiconductor film over the S/D region and having a doped second semiconductor material, the semiconductor film providing a top surface and two sidewall surfaces over the top and two sidewall surfaces of the fin respectively, wherein the doped second semiconductor material is different from the first semiconductor material; and a metal contact over the top and two sidewall surfaces of the semiconductor film and operable to electrically communicate with the S/D region.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yee-Chia Yeo, Carlos H. Diaz, Chih-Hao Wang, Ling-Yen Yeh, Yuan-Chen Sun