Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: Integrate circuit die terminal arrangements and configurations for mounting an integrate circuit die on a package substrate to reduce package transmission paths. In one embodiment, terminals for signals sensitive to trace length outside a die are arranged at the corners of the die. The die is mounted on a package substrate in an angle with respect to a package substrate to point the corners of the die at the edges of the package substrate to reduce trace length outside the die. The center of the die may or may not coincide with the center of the substrate. In one embodiment, when compare to a centered, non-rotated die mounting position, mounting a die with corners pointing at the edges of the package substrate does not cause significant differences in substrate warpage.

Abstract: In one embodiment, the present invention includes a semiconductor package having a plurality of fan blades embedded within a first surface of the package, where a first group of the fan blades extend from a first side of the package and a second group of the fan blades extend from a second side of semiconductor package. The fan blades may be powered by piezoelectric devices to cause motion of the fan blades. Other embodiments are described and claimed.

Abstract: A carrier assembly for an integrated circuit is described. The assembly includes a retainer for receiving the integrated circuit, and island defining portions surrounding the retainer. Each island defining portion is connected to neighboring island defining portions through a serpentine member. This arrangement allows resilient deflection between the island defining portions.

Abstract: The present invention is a MEMS-based two-phase LHP (loop heat pipe) and CPL (capillary pumped loop) using semiconductor grade silicon and microlithographic/anisotrophic etching techniques to achieve a planar configuration. The principal working material is silicon (and compatible borosilicate glass where necessary), particularly compatible with the cooling needs for electronic and computer chips and package cooling. The microloop heat pipes (?LHP™) utilize cutting edge microfabrication techniques. The device has no pump or moving parts, and is capable of moving heat at high power densities, using revolutionary coherent porous silicon (CPS) wicks. The CPS wicks minimize packaging thermal mismatch stress and improves strength-to-weight ratio. Also burst-through pressures can be controlled as the diameter of the coherent pores can be controlled on a sub-micron scale. The two phase planar operation provides extremely low specific thermal resistance (20-60 W/cm2).

Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.

Abstract: A power semiconductor module 3 for mounting on a cooling element 4 has at least one substrate 2, on which one or more components 5, 6, 7 are mounted and a module housing 40. The module housing 40 surrounds at least partially the at least one substrate 2. The module housing 40 has opposite sides with a first side facing the cooling element 4, and a second side 42 having one or more openings and a surface turned away from the power semiconductor module 3. Each of the one or more openings has a border, which is sealed by an internal contact 16, 17, 18, 27, 28, which is electrically connected to the one or more components 5, 6, 7. The internal contact protrudes the module housing 40, such that the internal contact not extends beyond said surface of the second side 42 of the module housing 40.

Abstract: A power feed device for an electrical component which improves the quality of transmission and reduces the mounting density of a printed circuit board in the power feed device or reduces the thickness of the printed circuit board and thereby realizes smaller size, provided with a power supply for supplying power, a printed circuit board having built-in signal line patterns, and a power bar having conductive projections provided in shapes and at positions corresponding to the shapes and positions of electrodes of the electrical component and provided outside of the printed circuit board, power from the power supply being supplied through the conductive projections of the power bar to electrodes of the electrical component.

Abstract: The present disclosure describes microfeature workpieces, microelectronic component packages, and methods of forming microelectronic components and microelectronic component packages. In one particular example, a microelectronic component package includes a substrate and a microelectronic component that has a first surface with a surface area greater than that of a second surface. A cementitious material, e.g., a die attach paste, may attach the second surface of the microelectronic component to a mounting surface of the substrate, with the cementitious material extending outwardly beyond a perimeter of the second surface and covering a surface area of the mounting surface that is no greater than the surface area of the first surface. Such a microelectronic component package may be formed with a smaller footprint or, alternatively, may include a microelectronic component having larger dimensions in a microelectronic component package of the same size.

Abstract: A MEMS package and methods for its embodiment are described. The MEMS package has at least one MEMS device mounted on a flexible and foldable substrate. A metal cap structure surrounds the at least one MEMS device wherein an edge surface of the metal cap structure is attached to the flexible substrate and wherein a portion of the flexible substrate is folded under itself thereby forming the MEMS package. A meshed metal environmental hole underlying the at least one MEMS device provides enhanced EMI immunity.

Abstract: Electrode plates acting as a heat sink are arranged to sandwich a power transistor and a diode. Electrode plates at their surfaces opposite cooling elements at a portion opposite power transistor and diode are formed to be smaller in thickness at a portion adjacent to power transistor and diode substantially at the center than at a periphery. Cooling elements are disposed geometrically along electrode plates to sandwich electrode plates.

Abstract: A semiconductor chip 36 is mounted on a package substrate 30 with its circuit side facing to a board 38. Heat is dissipated from an upper side of the semiconductor chip 36 opposite to the circuit side. A sealing resin 32 seals around the periphery of the semiconductor chip 36 so that the upper side of the semiconductor chip 36 is exposed to atmosphere. A fixing member 34 is buried in the sealing resin 32 so that a hook 40 formed on the tip of the fixing member 34 extends above the upper side of the semiconductor chip 36. A spreader 10 dissipates heat emitted from the semiconductor chip 36. A guiding slot 12 is formed on the side facing to the package substrate 30 of the spreader 10. The hooks 40 of the fixing members 34 are inserted into the guiding slots 12 respectively, and then the spreader 10 is rotated by predetermined angle against the package substrate 30. Then, the hooks 40 travel along the slots 12.

Abstract: An alphanumeric display includes a substrate that has top and bottom surfaces, a plurality of electrical contacts on the top surface, a plurality of light-emitting electronic devices mounted on the top surface, and a plurality of electrical pads on the bottom surface. The electrical contacts are connected to at least one light-emitting electronic device, and each of the light-emitting electronic devices is electrically connected with corresponding ones of the electrical contacts. The electrical pads are electrically connected to corresponding ones of the electrical contacts for communicating to the light-emitting electronic devices external sources of electrical power and control signals. The electrical pads on the bottom surface are arranged in a pattern to facilitate connections to the device using a conductive adhesive.

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract: An area array device has a grid array of primary electrical contacts coupled to a coupling surface of the device and configured to carry data signals between the area array package and a circuit board. The area array device also has an additional series of secondary electrical contacts coupled to the coupling surface of the device and configured to carry power signals between the area array package and the circuit board. The additional series of secondary electrical contacts provides a relatively large amount of power to the area array package while allowing a manufacturer to maintain the number of primary electrical contacts of the grid array configured to carrying data signals and therefore maintain the overall performance of the area array package.

Abstract: A semiconductor device with a damascene wiring structure which can prevent short-circuits between a seal ring and a wiring line or electrode pad. An upper layer barrier layer made from a conductive barrier material film is formed on an interlayer insulating film groove sidewall of the semiconductor device. Embedded in the groove is an upper layer seal ring wiring line with thickness of approximately 10 micrometers for instance, in which a plurality of isolated pockets of insulators are disbursed. These isolated pockets of insulators are formed using the interlayer insulating film which forms the damascene wiring line. Additionally, a first upper layer groove wiring line and a second upper layer groove wiring line are formed in an element forming region, and an upper layer barrier layer is formed on the outside perimeter. The upper layer seal ring wiring line and both upper layer wiring lines all have damascene wiring structures.

Abstract: Aiming at providing a semiconductor device advanced in performance of transistors, and improved in reliability, a semiconductor device of the present invention has a semiconductor element, a frame component provided over the semiconductor element, while forming a cavity therein, and a molding resin layer covering around the frame component, wherein the frame component is composed of a plurality of resin films (a first resin film and a second resin film) containing the same resin, and the cavity allows the active region of the semiconductor element to expose therein.

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises an integrated circuit die having a plurality of solder bumps; and a substrate comprising a first plurality of contact pads on a first surface and a second plurality of contact pads on a second surface. The plurality of solder bumps on the integrated circuit die is coupled to the first plurality of contact pads on the first surface of the substrate, wherein at least one edge of the substrate is formed after the integrated circuit die is attached to the substrate. According to one embodiment of the invention, the at least one edge of the substrate is formed after excess substrate material is detached at designated areas. According to another aspect of the invention, an assembly fixture is disclosed. An apparatus and method for assembling an integrated circuit package are also disclosed.

Abstract: The microcavity is delineated by a cover, comprising a first layer, in which at least one hole is formed. A second layer hermetically seals the microcavity. A third layer is arranged between the first and the second layer. An additional microcavity, communicating with the hole, is arranged between the first and the third layer. At least one additional hole, adjacent to the additional microcavity, formed in the third layer and offset with respect to the hole, is sealed by the second layer, after sacrificial layers have been removed through the additional hole. The microcomponent includes at least one mechanically stressed layer arranged above the first layer.

Abstract: A semiconductor chip having a thickness of 130 micrometers or less includes a mechanically ground bottom surface corresponding to a central circuit area, and a polished bottom surface corresponding to a peripheral scribe area. The mechanically ground bottom surface prevents heavy metals attached onto the bottom surface of the wafer from diffusing toward the source/drain regions of the semiconductor substrate and thereby from degrading the transistor characteristics.

Abstract: A semiconductor device includes: a substrate having a main surface, a rear surface and four side surfaces; a semiconductor element formed on the main surface of the substrate; a notch formed in at least one bottom part of the side surfaces of the substrate; and a curved surface provided at an intersection of a side surface of the notch and the rear surface of the substrate.

Abstract: A semiconductor device is provided that includes wiring patterns on a substrate formed of an organic insulating film, and a semiconductor chip mounted on the substrate. A liquid crystal display panel and a PW board are electrically connected to each other with an anisotropic conductive adhesive. At least one surface of the insulating film is treated with a silicon coupling material. The silicon coupling material contains silicon (Si) at a surface element density of 0.5 atomic percent to 12.0 atomic percent on a surface of the insulating film.

Abstract: A semiconductor device in which a plurality of semiconductor chips is stacked. A first semiconductor chip is stacked in a region, on a second semiconductor chip, in which a circuit that generates noise is not disposed within said second semiconductor chip, and a wire of a circuit that easily receives noise within said first semiconductor chip is disposed so as not to extend over said circuit that generates noise.

Abstract: A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. A semiconductor device assembly or package includes a semiconductor device, a redistribution layer over an active surface of the semiconductor device, and dielectric material coating at least portions of an outer periphery of the semiconductor device. Peripheral sections of contacts are located on the peripheral edge and electrically isolated therefrom by the dielectric coating. The contacts may also include upper sections that extend partially over the active surface of the semiconductor device. The assembly or package may include any type of semiconductor device, including a processor, a memory device, and emitter, or an optically sensitive device.

Abstract: A module (100, 200, 300, 400, 500, 600, 900) may be electrically connected to a PCB (18, 918) residing in a device (14) or may be joined to the device (14) to form a portion of the housing (16, 916) of the device (14). The module may include a housing (102, 202, 302, 402, 502, 602) having at least one layer, a surface mountable component, such as a surface mountable acoustic transducer (110, 210, 310, 410, 510, 610, 910) having a connecting surface (114, 214, 314, 414, 514, 614, 914), and at least one acoustic port (124, 224, 324, 424, 524, 624, 924) to couple a surface of the surface mountable acoustic transducer to the exterior of the device (14). The module (100, 200, 300, 400, 500, 600, 900) may further include a secondary mounting structure (654) electrically connected to the connecting surface (114, 214, 314, 414, 514, 614, 914) of the surface mountable acoustic transducer (110, 210, 310, 410, 510, 610, 910).

Abstract: Disclosed is a semiconductor device package. The semiconductor device package includes at least one semiconductor device acting as a heating source, a package substrate having an upper surface on which the semiconductor device is mounted, the package substrate at least having a higher heat conductivity than that of the semiconductor device, and a fiber-reinforced polymer composite formed to surround a side surface of the package substrate, the polymer composite including fibers acting as a reinforcing material and a resin mass embedding the fibers therein.

Abstract: A semiconductor device including a semiconductor substrate having a plurality of electrodes, a resin protrusion formed on the semiconductor substrate, and an interconnect electrically connected to the electrodes and formed to extend over the resin protrusion. A depression is formed in a top surface of the resin protrusion. The interconnect has a cut portion disposed over at least part of the depression.

Abstract: A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.

Abstract: A method of molding provides two molds (102, 104) formed of semiconductor material. The molds (102, 104) have substantially planar working faces (108, 110) into which recesses (106, 112) are formed. In use the molds (102, 104) are pressed together with the working faces (108, 110) opposed so the recesses (106, 112) form mold cavities. The molds (102, 104) only contact each other in the plane of the working faces (108, 110). A thermoplastic sheet placed between the molds is heated to deform the sheet into the mold cavities.

Abstract: The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.

Abstract: A circuit element having a heat-conducting body having top and bottom surfaces, and a die having an electronic circuit thereon is disclosed. The die includes first and second contact points for powering the electronic circuit. The die is in thermal contact with the heat-conducting body, the die having a bottom surface that is smaller than the top surface of the heat-conducting body. The first contact point on the die is connected to a first trace bonded to the top surface of the heat-conducting body. An encapsulating cap covers the die. The first trace has a first portion that extends outside of the encapsulating cap and a second portion that is covered by the encapsulating cap. The heat-conducting body is preferably constructed from copper or aluminum and includes a cavity having an opening on the first surface in which the die is mounted. The die preferably includes a light-emitting device.

Abstract: As part of a first configured laser operation, a smooth, more reflective marking area is formed at a surface of a substrate (e.g., integral heat spreader, or IHS). In a second configured laser operation, a mark is formed at the surface of the substrate within the marking area. The mark contrasts strongly with the reflective surface of the substrate in the marking area. As a result, the mark may be read with an optoelectronic imaging system with a higher rate of reliability than marks disposed at a substrate surface having a microtopographical profile with greater variation from a nominal surface plane. An IHS with a mark so disposed provides benefits when include as a portion of an integrated circuit package, which in turn provides benefits when included as a portion of an electronic system.

Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allow the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.

Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allowed the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.

Abstract: Side terminals 3 at respective corners of a package are higher than side terminals 4 on each side of the package. Thus, even if the side terminals 4 on each side are lower than those according to the conventional art owing to miniaturization or the like, when a device is mounted on a mounting substrate by soldering, a solder fillet 11 of a sufficient size can be formed between each of the corner side terminals 3, which significantly affect reliability, and a corresponding terminal on the mounting substrate. Thus, the device can be more reliably mounted on the mounting substrate by soldering.

Abstract: A wireless communication device such as a cell phone is rendered temporarily inoperable by enclosing the device in a container such as a heat sealable bag (1) which has been metallized so that when the device (2) is sealed in the container (1) it is surrounded by a metal layer (9) which blocks signals to and from the device (3) to thereby render it inoperable. The device is sealed within the container (1) by a seal such as a heat seal which will reveal any attempt to remove the device from the container.

Abstract: An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region.

Abstract: A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluorethylene, filled with fibers which may be glass fibers or ceramic fibers.

Abstract: The invention of the present application provides a heat radiation structure of a semiconductor device, and includes a substrate having, on a surface thereof, a first area on which the semiconductor device is mounted, and a second area which surrounds the first area. The semiconductor device has a first surface and a second surface opposite to the first surfaces, and is formed with a plurality of terminals provided on the first surface. The semiconductor device is mounted on the substrate in such a manner that the first surface is opposite to the surface of the substrate. A first heat radiating film is formed on the second area of the substrate, and a second heat radiating film is formed on the second surface of the semiconductor device, with the second heat radiating film being spaced apart from the first heat radiating film.

Abstract: A method and device for 3-dimensional input finger control of different functions in electronic consumer devices is provided. Certain versions of the Present Invention provide a 3-dimensional input finger interface control device for cell phones, portable gamers, digital cameras, and other consumer devices. Certain alternate versions of the Present Invention exhibit one or more of the qualities of smallness, low-cost, high reliability, and/or high stability. Certain still alternate versions of the Present Invention provide a 3-dimensional input finger force control device that (1.) accommodates a required ratio between X, Y and Z sensitivities, (2.) has low cross-axis sensitivity, (3.) allows process integration with other sensors and CMOS, (4.) is scalable, (5.) allows convenient solutions for applying an external force, and/or (6.) allows economic manufacturability for high volume consumer markets.

Abstract: To provide a semiconductor package mounting method, with excellent work efficiency, wherein the direction of a semiconductor package can be verified by a simple method before mounting. One corner of a square shaped display section provided on the surface of a semiconductor package body is chamfered such that the chamfer dimensions are different from those of the other corners. If image recognition by a camera determines that this chamfered part is located correctly, the orientation of a semiconductor package is determined to be correct. On the other hand, if image recognition determines that it is not located correctly, the orientation of the semiconductor package is adjusted until it is correct.

Abstract: A flip-chip package structure with stiffener includes a substrate, a first stiffener positioned on a surface of the substrate, a chip having a plurality of bumps adopted to electrically connect the substrate and the chip, and a second stiffener positioned on the surface of the substrate and connected with the first stiffener. The first stiffener is positioned outside of the second stiffener.

Abstract: A power semiconductor device package utilizes integral fluid conducting micro-channels, one or more inlet ports for supplying liquid coolant to the micro-channels, and one or more outlet ports for exhausting coolant that has passed through the micro-channels. The semiconductor device is mounted on a single or multi-layer circuit board having electrical and fluid interconnect features that mate with the electrical terminals and inlet and outlet ports of the device to define a self-contained and self-sealed micro-channel heat exchanger.

Abstract: An electrical interconnect assembly for electrically interconnecting terminals on a first circuit member with terminals on a second circuit member. The electrical interconnect includes a housing having a plurality of through openings extending between a first surface and a second surface. A plurality of composite contacts are positioned in a plurality of the through openings. The composite contacts include a conductive member having a central portion and at least first and second interface portions. One or more polymeric layers extend along at least the central portion conductive member. One or more coupling features on the composite contacts engage with the housing. At least one engagement feature formed in the polymeric layers proximate the first interface portion mechanically couples with the terminals on the first circuit member.

Abstract: A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second metal foil and the dielectric interposer with a portion of the first metal foil as its bottom. A die is mounted within the recessed cavity and makes thermal contact with the first metal foil. A build-up material layer covers the second metal foil and an active surface of the die. The build-up material layer also fills the gap between the die and the dielectric interposer. At least one interconnection layer is provided on the build-up material layer and is electrically connected with a bonding pad disposed on the active surface of the die via a plated through hole.

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract: A semiconductor package has: a semiconductor chip having first and second main electrodes arranged on two principal surfaces being opposite to each other; a first main wiring plate connected to the first main electrode and having a first external connection terminal; a second main wiring plate connected to the second main electrode and having a second external connection terminal; a first shell connected through an insulating film to at least a part of a second principal surface of the first main wiring plate, the second principal surface of the first main wiring plate being opposite to a first principal surface of the first main wiring plate that is connected to the first electrode; and a second shell connected through an insulating film to at least a part of a second principal surface of the second main wiring plate, the second principal surface of the second main wiring plate being opposite to a first principal surface of the second main wiring plate that is connected to the second electrode.

Abstract: A semiconductor device has a semiconductor substrate with an inclined through hole extending between its two major surfaces in a peripheral part of the substrate, providing an electrical interconnection between the two surfaces. The opening of the inclined through hole on the first major surface, on which electronic components are formed, is closer to the edge of the substrate than is the opening on the second major surface. Reliability is therefore enhanced because cracks forming at the edge of the second major surface are less likely to propagate to the through hole. An electrically conductive path in the through hole is formable by spraying conductive material onto its inner wall, using an ink-jet system.