Abstract: A radiation plate structure includes a radiation plate, and a solder resist disposed on a main surface of the radiation plate and having at least one opening. The solder resist is made of any of polyimide (PI), polyamide (PA), polypropylene (PP), polyphenylene sulfide (PPS), a resin containing particulate ceramic (e.g., aluminum nitride (AlN), silicon nitride (Si3N4), or aluminum oxide (Al2O3)), and a high-melting-point insulator made of, for instance, glass.

Abstract: Microelectronic systems having embedded heat dissipation structures are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the steps or processes of obtaining a substrate having a tunnel formed therethrough, attaching a microelectronic component to a frontside of the substrate at a location covering the tunnel, and producing an embedded heat dissipation structure at least partially within the tunnel after attaching the microelectronic component to the substrate. The step of producing may include application of a bond layer precursor material into the tunnel and onto the microelectronic component from a backside of the substrate. The bond layer precursor material may then be subjected to sintering process or otherwise cured to form a thermally-conductive component bond layer in contact with the microelectronic component.

Abstract: The present disclosure provides a stacked-type solid electrolytic capacitor package structure and a method of manufacturing the same. The capacitor package structure includes a capacitor unit, a solder unit, a package unit and a conductive unit. The capacitor unit includes a plurality of first stacked capacitors. Each first stacked capacitor includes a first positive portion and a first negative portion. The first positive portion has at least one first through hole. The first through holes of the first positive portions are in communication with each other to form a first communication hole. The solder unit includes a first connection solder for filling the first communication hole so as to connect the first positive portions with each other. The package unit includes a package body for enclosing the capacitor unit and the solder unit. The conductive unit includes a first conductive terminal and a second conductive terminal.

Abstract: There is provided a wiring board. The wiring board includes: a first insulating layer; a plurality of wiring patterns on the first insulating layer so as to be spaced apart from each other; a plating layer on at least one of the wiring patterns; a second insulating layer containing silicone therein and having an opening, wherein an outermost surface of the plating layer is exposed from the opening and serves as a connection pad; and a silica film on the outermost surface of the plating layer.

Abstract: A semiconductor package includes a substrate, a ground circuit supported by the substrate, at least one semiconductor chip disposed on the substrate and a carbon-containing heat-dissipating part disposed on the substrate and electrically connected to the ground circuit. The heat-dissipating part may include carbon fibers and/or carbon cloth.

Abstract: A sealing member is disclosed, which includes a first structure and a second structure. The first structure includes a groove with an opening towards the outside of the sealing member, wherein the second structure is disposed in the groove. The first structure includes a first material, and the second structure includes a second material, wherein the water absorption rate of the second material is greater than the water absorption rate of the first material. Also, an electronic device using the sealing member is disclosed.

Abstract: A flip chip microelectronic package having a heat spreader is provided. In one embodiment, the microelectronic package comprises a die having a first surface and a second surface, the first surface being coupled to a substrate; a thermal interface material disposed in thermal conductive contact with the second surface of the die; and a heat spreader adapted for dissipating heat from the die, the heat spreader disposed in thermal conductive contact with the thermal interface material. The heat spreader includes a lid having an inner chamber therein defined by a first wall and a second wall, the second wall securely joined to the first wall to seal the chamber, the lid being mounted to the substrate and a wick layer positioned in the chamber.

Abstract: A multi-wavelength semiconductor laser device includes a block having a V-shaped groove with two side faces extending in a predetermined direction; and laser diodes with different light emission wavelengths mounted on the side faces of the groove in the block so that their laser beams are emitted in the predetermined direction.

Abstract: One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.

Abstract: There are provided an electrode foil which has all the functions of a supporting base material, an electrode and a reflective layer and also has a superior thermal conductivity; and an organic device using the same. The electrode foil comprises a metal foil, wherein the electrode foil has at least one outermost surface which is an ultra-smooth surface having an arithmetic average roughness Ra of 10.0 nm or less as measured in accordance with JIS B 0601-2001.

Abstract: A stackable integrated circuit package system including mounting an integrated circuit device over a package carrier, mounting a stiffener over the package carrier and mounting a mountable package carrier over the stiffener with a vertical gap between the integrated circuit device and the mountable package carrier.

Abstract: A multi-wavelength semiconductor laser device includes a block having a rectangular groove with a bottom face and two side faces extending in a predetermined direction; and laser diodes with different light emission wavelengths mounted on the bottom face and the side faces of the groove in the block so that their laser beams are emitted in the predetermined direction.

Abstract: A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a first radiator member arranged on and thermally coupled to the semiconductor element, and a second radiator member arranged on and thermally coupled to the first radiator member. The second radiator member includes projections which project out toward the first radiator member. The projections are formed on a circumference of a concentric circle with respect to a center point of the second radiator member. The first radiator member includes grooves in which the projections are movable. The grooves are formed on a circumference of a concentric circle with respect to a center point of the first radiator member. The projections are fitted to terminating ends of the grooves with the center point of the first radiator member and the center point of the second radiator member coincided.

Abstract: A hybrid integrated optical device includes a substrate comprising a silicon layer and a compound semiconductor device bonded to the silicon layer. The device also includes a bonding region disposed between the silicon layer and the compound semiconductor device. The bonding region includes a metal-semiconductor bond at a first portion of the bonding region. The metal-semiconductor bond includes a first pad bonded to the silicon layer, a bonding metal bonded to the first pad, and a second pad bonded to the bonding metal and the compound semiconductor device. The bonding region also includes an interface assisted bond at a second portion of the bonding region. The interface assisted bond includes an interface layer positioned between the silicon layer and the compound semiconductor device, wherein the interface assisted bond provides an ohmic contact between the silicon layer and the compound semiconductor device.

Abstract: A balance filter packaging chip having a balun mounted therein and a manufacturing method thereof are provided. The balance filter packaging chip includes a device substrate; a balance filter mounted on the device substrate; a bonding layer stacked on a certain area of the device substrate; a packaging substrate having a cavity formed over the balance filter, and combined with the device substrate by the bonding layer; a balun located on a certain area over the packaging substrate; and an insulator layer for passivating the balun. Accordingly, the present invention can reduce an element size and simplify a manufacturing process.

Abstract: A composite integrated optical device includes a substrate including a silicon layer and a waveguide disposed in the silicon layer. The composite integrated optical device also includes an optical detector bonded to the silicon layer and a bonding region disposed between the silicon layer and the optical detector. The bonding region includes a metal-assisted bond at a first portion of the bonding region. The metal-assisted bond includes an interface layer positioned between the silicon layer and the optical detector. The bonding region also includes a direct semiconductor-semiconductor bond at a second portion of the bonding region.

Abstract: A storage battery control device detects an overhead wire supply current value showing a sum of a current value output from a storage battery and a current value output from a transformer substation, and charging or discharging of the storage battery is controlled so that a charging rate of the storage battery becomes a charging rate target value when the detected overhead wire supply current value is less than a first threshold. In addition, charging or discharging of the storage battery is controlled so that the output voltage of the storage battery control device is maintained at a constant voltage control mode when the detected overhead wire supply current value is greater than or equal to the first threshold.

Abstract: A semiconductor laser device includes a Si(100) substrate in which a recess having an opening and a bottom face surrounded by inner wall surfaces is formed, a semiconductor laser element placed on the bottom face, and a translucent sealing glass, mounted on top of the Si(100) substrate, which seals the opening. The laser light emitted from the semiconductor laser element is reflected by a metallic reflective film formed on the inner wall surface and then transmits through the sealing glass so as to be emitted externally.

Abstract: A packaging structure having an embedded semiconductor element includes: a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; a first metallic frame disposed around the periphery of the opening on the first surface; a semiconductor chip received in the opening and having an active surface formed with a plurality of electrode pads and an opposite inactive surface; two first dielectric layers formed on the active surface and the inactive surface of the chip, respectively; a first wiring layer formed on the first dielectric layer of the first surface; and a first built-up structure disposed on the first dielectric layer and the first wiring layer. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate.

Abstract: A conductive structure for a semiconductor integrated circuit is provided. The semiconductor integrated circuit comprises a pad, and a passivation layer partially overlapping the pad, which jointly define an opening portion. The conductive structure is adapted to be electrically connected to the pad through the opening portion. The conductive structure comprises an under bump metal (UBM). A first conductor layer formed on the under bump metal is electrically connected to the under bump metal. A second conductor layer formed on the first conductor layer and electrically connected to the first conductor layer and a cover conductor layer. Furthermore, the under bump metal, the first conductor layer, and the second conductor jointly define a basic bump structure. The cover conductor layer is adapted to cover the basic bump structure.

Abstract: An RF package includes a substrate mountable on a base plate, a non-conductive cover overlying the substrate, and quasi-serpentine stepped source leads attached to an upper surface of the substrate and extending from at least one of a pair of opposite sides of the upper surface of the substrate to tapered lower surfaces of the cover. The cover includes a recess to receive the substrate. The recess includes stress distribution surface areas to engage and press outer edge portions of opposite sides of the substrate against a base plate or heat sink. The tapered lower surfaces of the cover engage with and press against the stepped source leads when securing the RF package to the base plate or heat sink using one or more fasteners or bolts. The cover includes structural features to improve preferential deformation when a mounting force is applied.

Abstract: The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus includes a semiconductor die having an upper surface, a first capacitor deployed above the upper surface of the semiconductor die, a separation layer deployed above the first capacitor, and a bond pad deployed above the separation layer such that at least a portion of the bond pad lies above the first capacitor.

Abstract: A multi-wavelength semiconductor laser device includes a block having a rectangular groove with a bottom face and two side faces extending in a predetermined direction; and laser diodes with different light emission wavelengths mounted on the bottom face and the side faces of the groove in the block so that their laser beams are emitted in the predetermined direction.

Abstract: A semiconductor device and method of manufacturing has a substrate having a plurality of metal layers. At least one metal layer is exposed on at least one side surface of the semiconductor device. A die is coupled to the substrate. A mold compound encapsulates the die and a top surface of the substrate. A conductive coating is applied to the mold compound and to at least one metal layer exposed on at least one side surface of the substrate.

Abstract: Embodiments of a microelectronic package are generally described herein. A microelectronic package may include a die having a first side and a second side, opposite the first side, a flange coupled to the first side of the die, and a lead frame proximately positioned relative to the die and coupled to the second side of the die. Other embodiments may be described and claimed.

Abstract: A power semiconductor module system. One embodiment provides a power semiconductor module and a mounting adapter. The mounting adapter and the power semiconductor module can be latched to one another in two different latching stages such that a contact element of the power semiconductor module makes electrical contact with a contact element of the mounting adapter assigned to the contact element in a second one of the latching stages but not in a first one of the latching stages.

Abstract: A sealed semiconductor power module that may include a rectifier, such as a silicon controlled rectifier (SCR), is provided. The module includes an AlN substrate having a bottom surface positioned on a metallic base plate and a top surface that includes a first pad and a second pad, the substrate including a copper body on both of the two major surfaces. The module also includes a first die and a second die positioned on top of the first and second pads, respectively, the first die and the second die each including a main contact area on a top surface thereof, the first die including an isolated gate area on the top surface to which is coupled a gate terminal; and first and second power terminals in direct wirebondless electrical connection via molybdenum tabs with the main contact areas of the die.

Abstract: An integrated circuit package system includes: providing a tie bar and a lead adjacent thereto; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield connected to the tie bar; and encapsulating the integrated circuit and the shield. An integrated circuit package system also includes: forming a lead and a support structure with substantially the same material as the lead and elevated above the lead; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield on the support structure; and encapsulating the integrated circuit and the shield.

Abstract: The invention relates to a flip-chip module with a semiconductor chip with contact posts, wherein the contact posts are connected electrically and mechanically to a substrate. Provided between the substrate and the semiconductor chip is a spacer, which is coupled mechanically to the substrate and/or the semiconductor chip. By this means, thermal stresses in the flip-chip module are absorbed by the spacer and kept away from the semiconductor chip. The invention also relates to a method for the production of a flip-chip module, in which firstly a spacer is located between the semiconductor chip and the substrate, after which the contact posts are soldered to the contact points of the substrate. Through the provision of the spacer the distance between the semiconductor chip and the substrate is set precisely, thereby improving the quality of the soldering points.

Abstract: According to one embodiment, a power transistor package includes an electrically conductive flange configured to be connected to a source of a power transistor device. The package further includes a first terminal mechanically fastened to the flange and configured to be electrically connected to a gate of the power transistor device and a second terminal mechanically fastened to the flange and configured to be electrically connected to a drain of the power transistor device. The package also includes a bus bar mechanically fastened to the flange which extends between and connects at least two different DC bias terminals mechanically fastened to the flange. The bus bar is configured to be electrically connected to the drain via one or more RF grounded connections.

Abstract: An embodiment of a die assembly includes a flange, lip walls, and leads for electrical contact with one or more die mounted on the flange. The flange has first and second opposed flange surfaces and flange sidewalls extending between the surfaces. The lip walls have first and second opposed lip surfaces and lip sidewalls extending between the first and second lip surfaces. The lip sidewalls are positioned adjacent to the flange sidewalls. The leads, which have inboard end portions and outboard end portions, are configured to preserve a seating plane. The seating plane is spaced apart from a plane of the second flange surface. The inboard end portions of the leads are embedded in the lip walls, and extend from the seating plane upward through the lip walls toward the first lip surfaces. The outboard end portions are aligned substantially within the seating plane.

Abstract: An RF power amplifier including a single piece heat sink and an RF power transistor die mounted directly onto the heat sink.

Abstract: A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion that extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member that substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface.

Abstract: An integrated circuit package system includes: a substrate; a first device attached to the substrate; a shield attached to the substrate and surrounding the first device; apertures formed within the shield; the shield configured to block electromagnetic energy that passes through the apertures; and an encapsulation material deposited through the apertures.

Abstract: A semiconductor module includes a first metal foil; an insulating sheet mounted on a top surface of the first metal foil; at least one second metal foil mounted on a top surface of the insulating sheet; at least one semiconductor device mounted on the second metal foil; and a resin case for surrounding the first metal foil, insulating sheet, second metal foil, and semiconductor device. A bottom end of a peripheral wall of the resin case is located above a bottom surface of the first metal foil. A resin is provided inside the resin case to fill the inside of the resin case. The bottom surface of the first metal foil and the resin form a flat bottom surface so that the flat bottom surface contacts an external mounting member.

Abstract: A semiconductor package with enhanced mobility of ball terminals is revealed. A chip is attached to the substrate by a die-attaching material where the substrate has at least a stepwise depression on the covered surface to make the substrate thickness be stepwise decreased from a central line of the die-attaching area toward two opposing sides of the substrate. The die-attaching material is filled in the stepwise depression. Therefore, the thickness of the die-attaching material under cross-sectional corner(s) of the chip becomes thicker so that a row of the ball terminals away from the central line of the die-attaching area can have greater mobility without changing the appearance, dimensions, thicknesses of the semiconductor package, nor the placing plane of the ball terminals. Accordingly, the row of ball terminals located adjacent the edges or corners of the semiconductor package can withstand larger stresses without ball cracks nor ball drop.

Abstract: A power semiconductor device has a power field effect transistors connected in a bridge circuit (16), parallel circuit or series circuit (18), the power semiconductor device (30) having a base power semiconductor chip (1) with large-area external contacts (S1, D1) on the top side (31) and rear side (32) and carrying at least one stacked power semiconductor chip (2). The stacked power semiconductor chip (2) is surface-mounted with at least one large-area external electrode (D2) on a correspondingly large-area external electrode (S1) of the top side (31) of the base power semiconductor chip (1). At least one metallic structured spacer (33) is arranged between the surface-mounted external electrodes (S1, D2) of the base power semiconductor chip (1) and the stacked power semiconductor chip (2). The structure of the spacer (33) has at least one cutout (34) for a non-surface-mountable connecting element (35) of the base power semiconductor chip (1).

Abstract: An infrared detector comprises: first and second container members bonded to each other along an annular bonding portion to define a vacuum-sealed inner space, where the second container member has an infrared-transmissive property; an infrared detecting element disposed in the inner space; a first annular metallization layer formed on the bonding portion of the first container member; a second annular metallization layer formed on the bonding portion of the second container member; a solder metal for air-tightly bonding the first metallization layer and the second metallization layer; and a third metallization layer formed in a vicinity of one of the first and second metallization layers such that the third metallization layer overlaps the other of the first and second metallization layers at least partly.

Abstract: A semiconductor chip has an active face in which an integrated circuit region is implanted. The chip includes an inclined lateral contact pad extending beneath the plane of the active face and electrically linked to the integrated circuit region. An electronic module includes a substrate having a cavity in which the chip is arranged. The module can be applied to the production of thin contactless micro-modules for smart cards and contactless electronic badges and tags.

Abstract: A power semiconductor module includes a housing, a substrate carrier with a circuit thereon and electrical connection elements extending therefrom. The carrier has a cutout between its inner surface (facing the interior of the module) and its outer surface. The cutout is smaller at the inner surface than at the outer surface. The housing has an extension that reaches into the cutout and may be deformed to form a riveted connection. The method comprises: forming a housing with at least one extension which extends towards the exterior of the module, wherein the extension projects through the cutout and beyond the outer surface of the carrier; and deforming the end of the extension so that it widens and forms a riveted connection and at the same time lies below the outer surface of the carrier.

Abstract: A method of manufacture of an integrated circuit package system which includes providing a substrate and attaching a first device to the substrate. Attaching a shield to the substrate. Processing the shield to form apertures and configuring the shield to block electromagnetic energy that passes through the apertures.

Abstract: A power semiconductor module and a method of manufacture thereof includes a lead frame carrying lead having inner and outer lead portions. The outer lead portions, which are connected by soldering to semiconductor chips simultaneously, eliminate the need for using bonding wires. Since no bonding wire is used for connecting the leads and the semiconductor chips, a sufficient current capacity is obtained. The bonding between an insulating circuit board and the semiconductor chips and the bonding between the semiconductor chips and the leads can be made simultaneously in a single step of reflow-soldering. As a result, the mounting time can be shortened and the power semiconductor module can be manufactured more efficiently.

Abstract: A semiconductor apparatus having improved thermal fatigue life is provided by lowering maximum temperature on jointing members and reducing temperature change. A jointing member is placed between a semiconductor chip and a lead electrode, and a thermal stress relaxation body is arranged between the chip and a support electrode. Jointing members are placed between the thermal stress relaxation body and the chip and between the thermal stress relaxation body and the support electrode. A second thermal stress relaxation body made from a material having a thermal expansion coefficient between the coefficients of the chip and the lead electrode is located between the chip and the lead electrode. The first thermal stress relaxation body is made from a material which has a thermal expansion coefficient in between the coefficients of the chip and the support electrode, and has a thermal conductivity of 50 to 300 W/(m·° C.).

Abstract: A semiconductor element and a passive element are embedded in an insulating resin film by thermocompression bonding. After formation of a interconnection, a layered film which contains a film insulating between elements and is provided with a recess or penetrated portion is pressure-bonded followed by formation of a member with a high resistance or a high dielectric constant by embedding a material of a member constituting an element such as a resistor and a capacitor in the recess. Furthermore, after formation of the upper layer insulating resin film, a photoimageable solder resist layer containing the cardo type polymer is formed, and interconnection formation and solder electrode formation are performed.

Abstract: A microcircuit package having a ductile layer between a copper flange and die attach. The ductile layer absorbs the stress between the flange and semiconductor device mounted on the flange, and can substantially reduce the stress applied to the semiconductor device. In addition, the package provides the combination of copper flange and polymeric dielectric with a TCE close to copper, which results in a low stress structure of improved reliability and conductivity.

Abstract: In one embodiment, a method for forming a molded flat pack style package includes attaching electronic chips to an array lead frame, which includes a plurality of elongated flag portions with tab portions and a plurality of leads. The method further includes connecting the electronic chips to specific leads, and then molding the array lead frame while leaving portions of the leads exposed to form a molded array structure. The molded array structure is then separated to provide molded flat pack style packages having exposed leads for insertion mount and exposed tab portions. In an alternative embodiment, the separation step produces a no-lead configuration with exposed tab portions.

Abstract: An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region.

Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluorethylene, filled with fibers which may be glass fibers or ceramic fibers.

Abstract: A microcircuit package having a ductile layer between a copper flange and die attach. The ductile layer absorbs the stress between the flange and semiconductor device mounted on the flange, and can substantially reduce the stress applied to the semiconductor device. In addition, the package provides the combination of copper flange and polymeric dielectric with a TCE close to copper, which results in a low stress structure of improved reliability and conductivity.