Flanged Mount Patents (Class 257/732)
  • Patent number: 7518227
    Abstract: Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction or heat removal for semiconductor devices and the methods for the stacking thereof are disclosed.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: April 14, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 7518238
    Abstract: A substrate may receive an integrated circuit and a flex circuit on the same side in the same vertical direction. In addition, in some embodiments, a flex circuit adapter and the integrated circuit may be surface mounted in one operation.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: April 14, 2009
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Henning Braunisch
  • Patent number: 7508063
    Abstract: Disclosed herein is a device package that comprises a device having a top substrate that is disposed on a supporting surface of a package substrate. A package frame contacts the top surface of the top substrate and top surface of the package substrate, and hermetically seals the device between the top surfaces of the top substrate and package substrate. The device can be a semiconductor device, a microstructure such as a microelectromechanical device, or other devices.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: March 24, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Duboc, Terry Tarn
  • Patent number: 7504670
    Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: March 17, 2009
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Satoshi Shiraishi, Yoichi Kazama
  • Patent number: 7425758
    Abstract: Chip-scale packages and assemblies thereof and methods of fabricating such packages including Chip-On-Board, Board-On-Chip, and vertically stacked Package-On-Package modules are disclosed. The chip-scale package includes a core member of a metal or alloy having a recess for at least partially receiving a die therein and includes at least one flange member partially folded over another portion of the core member. Conductive traces extend from one side of the package over the at least one flange member to an opposing side of the package. Systems including the chip-scale packages and assemblies are also disclosed.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: September 16, 2008
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Chin Hui Chong, Choon Kuan Lee
  • Patent number: 7416332
    Abstract: A temperature sensing system for a flange mounted device is provided. The temperature sensing system (100) can be comprised of a flexible wiring board (102). The temperature sensing system can be further comprised of a temperature sensing device (122) mounted to the flexible wiring board. The flexible wiring board can have one or more conductive traces (114a, 114b, 114c) disposed thereon. The conductive traces can form an electrical connection with the temperature sensing device. The temperature sensing system can also comprise a thermal pad directly connected to the temperature sensing device. The thermal pad can be formed of a thermal conductor. The thermal pad can also have a thermal contact surface. The thermal contact surface can be sized and shaped for direct physical contact with a portion of the device (302), wherein thermal energy is communicated directly from the thermal pad to the temperature sensing device. A method for sensing a temperature of a flange mounted device is also provided.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: August 26, 2008
    Assignee: Harris Corporation
    Inventors: Timothy D. Rountree, Thomas D. O'Brien, Kenneth Beghini
  • Publication number: 20080142963
    Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluorethylene, filled with fibers which may be glass fibers or ceramic fibers.
    Type: Application
    Filed: November 19, 2007
    Publication date: June 19, 2008
    Applicant: KYOCERA AMERICA, INC.
    Inventors: Jeffrey VENEGAS, Paul GARLAND, Joshua LOBSINGER, Linda LUU
  • Patent number: 7361880
    Abstract: A digital camera module (100) includes a holder, an image sensor chip package (30), a number of conductive elements (24) and a circuit board (40). The holder defines a receiving portion. The holder is mounted on the image sensor chip package. The image sensor chip package has a number of outer pads. The outer pads are positioned in the receiving portion of the holder. The conductive elements are received in the receiving portion. One end of each of the conductive elements is connected to the inner pads, the other end of each of the conductive elements is connected to the circuit board.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: April 22, 2008
    Assignee: Altus Technology Inc.
    Inventor: Steven Webster
  • Patent number: 7358106
    Abstract: A swage hermetic sealing of a MEMS or microdevice or nanodevice package using high force. A cutting and flowing edge 430 is formed on a package cover which is pressed into a mating , integral gasket 425 on a package base. A material extension of the package cover 450 is simultaneously folded under the package base to supply force maintenance for permanent hermaticity. The swage hermetic sealing of single or an array of covers to an extended wafer or substrate is accomplished by a cutting and flowing edge 560. Permanent force maintenance is achieved through a re-entrant cavity 565 and annular ring 535 on the wafer or substrate.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: April 15, 2008
    Assignee: Stellar Micro Devices
    Inventor: Curtis Nathan Potter
  • Patent number: 7329947
    Abstract: When a two-division structure heat treatment jig for semiconductor substrate that includes a silicon first jig that comes into direct contact with a semiconductor substrate that is heat treated and supports the semiconductor substrate, and a second jig (holder) that holds the first jig and is mounted on a heat treatment boat is adopted as a heat treatment boat of a vertical heat treatment furnace, the stress concentrated during the heat treatment on a particular portion of the semiconductor substrate can be reduced; in the case of a semiconductor substrate large in the tare stress and having an outer shape of 300 mm being heat treated, or even in the case of the heat treatment being carried out under very high temperature conditions, the slips can be suppressed from occurring. The present invention can be widely applied as a stable heat treatment method of semiconductor substrates.
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: February 12, 2008
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Naoshi Adachi, Kazushi Yoshida, Yoshiro Aoki
  • Patent number: 7298046
    Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluoroethylene, filled with fibers which may be glass fibers or ceramic fibers.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: November 20, 2007
    Assignee: Kyocera America, Inc.
    Inventors: Jeffrey Venegas, Paul Garland, Joshua Lobsinger, Linda Luu
  • Patent number: 7282793
    Abstract: Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction or heat removal for semiconductor devices and the methods for the stacking thereof are disclosed.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: October 16, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 7253520
    Abstract: A semiconductor device comprises a semiconductor chip which has a first surface, a pad which is formed directly on the first surface, an oxide film which is formed on the first surface, an insulating film which is formed on the oxide film and a part of the pad, a conductive film which is formed on the insulating film and the pad, a sealing material which covers a part of the conductive film and the insulating film and a bump which is formed over the conductive film, wherein the bump is exposed from a surface of the sealing material.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: August 7, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hideaki Yoshida, Tae Yamane
  • Patent number: 7242085
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10A). A metal base (10A) can have side portions (12) with connection electrodes (15A) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The connection electrode (15A) can be formed on a projecting piece (16) that is bent outward away from remaining portions of the side portion (12). The semiconductor device can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: July 10, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Futoshi Hosoya
  • Patent number: 7138713
    Abstract: A chip-type solid electrolytic capacitor comprises capacitor elements. A cathode terminal comprising a plate-like conductor is interposed between cathode layers of the capacitor elements. The capacitor elements are bonded to each other by a bonding agent such as a solder or a conductive adhesive. The cathode terminal is provided with a through hole formed at a portion to be brought into contact with each of the capacitor elements. Bonding surfaces of the capacitor elements are directly connected at the through hole.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: November 21, 2006
    Assignees: NEC Tokin Corporation, NEC Tokin Toyama, Ltd.
    Inventors: Fumio Kida, Makoto Nakano
  • Patent number: 7102228
    Abstract: A semiconductor device comprising a substrate, a semiconductor element mounted on the substrate, an inner annular stiffener provided on the substrate in an outer side of the semiconductor element, and an outer annular stiffener provided on the substrate in an outer side of the inner annular stiffener. The inner annular stiffener and the outer annular stiffener are made of different materials. Particularly, the thermal expansion coefficient of the inner annular stiffener is selected to be smaller than that of the substrate, and the thermal expansion coefficient of the outer annular stiffener is selected to be larger than that of the substrate. The amount of deformation of the substrate is thus decreased.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: September 5, 2006
    Assignee: Fujitsu Limited
    Inventor: Takashi Kanda
  • Patent number: 7095098
    Abstract: An electrically isolated and thermally conductive double-sided pre-packaged IC component, stamped lead members, drain pads, source pads, gate runner, and a MOSFET, IGBT, etc. are positioned between a pair of ceramic substrate members. Layers of solderable copper material are directly bonded to the inner and outer surfaces of the substrate members.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: August 22, 2006
    Assignee: Delphi Technologies, Inc.
    Inventors: Erich William Gerbsch, Ralph S. Taylor
  • Patent number: 7061101
    Abstract: Carrier module including a carrier module body for seating a semiconductor device on an underside thereof, having a pass through hole from an upper part to the underside the semiconductor device is seated thereon, a housing over the carrier module body, a supplementary housing fitted in a lower part of the housing to be movable in up/down directions, for elastic contact with the carrier module body by a first elastic member fitted inside of the housing, a vacuum tube in the supplementary housing so as to be in communication with the pass through hole in the carrier module body, at least one pair of latches in a lower part of the carrier module body to move apart or close in an outer or inner side, for holding or releasing the semiconductor device seated on the carrier module body, a latch button fitted in an upper part of the carrier module body so as to be movable in up/down directions, and coupled to the latch with a connection pin for moving in up/down directions by an external force, to making the latch t
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: June 13, 2006
    Assignee: Mirae Corporation
    Inventors: Chul Ho Ham, Byoung Dae Lee, Ho Keun Song, Young Geun Park
  • Patent number: 7030477
    Abstract: A laser device includes a can package of a laser diode having a lead terminal secured to a through hole in a stem by a sealant, and a flexible substrate having a transmission line on a front surface of a polyimide film. The lead terminal of the can package and one end of a transmission line of the flexible substrate are connected by soldering. A resistor for matching the impedance of the transmission line and the impedance of the lead terminal is located in the vicinity of a connection of the transmission line and the lead terminal.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: April 18, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Eitaro Ishimura
  • Patent number: 7012331
    Abstract: A semiconductor package is mounted to a support plate through a base. The base is inserted between a rear face of the semiconductor package and a front face of the support plate. An electrical connection mechanism is provided to connect the semiconductor package to the support plate pass. This mechanism passes through the base. The mounting of the semiconductor package is accomplished by a variety of structures to fasten the package onto the said support plate. These structures cooperate with and are placed below the rear face of the semiconductor package.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: March 14, 2006
    Assignee: STMicroelectronics S.A.
    Inventors: Rémi Brechignac, Kevin Channon, Juan Exposito
  • Patent number: 6992375
    Abstract: An anchor to hold getter materials in place within a micromechanical device package substrate. First and second cavity faces define an anchor cavity and mechanically retain a getter away from a region holding the micromechanical device. The getter anchor may be formed in a substrate comprised of at least three layers. The layers form a cavity in the substrate with a wide bottom portion—formed in the middle layer and a relatively narrower top portion—formed by the top layer. The narrow portion helps to retain the getter in the cavity by creating a mechanical lock on the wide portion of getter in the bottom of the cavity.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: January 31, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Roger A. Robbins, Jwei Wien Liu, Jack C. Smith, Edward Carl Fisher, Joyce Wong Holton
  • Patent number: 6911723
    Abstract: Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction or heat removal for semiconductor devices and the methods for the stacking thereof are disclosed.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: June 28, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 6909182
    Abstract: A spherical semiconductor device includes a spherical semiconductor element having one or more electrodes on its surface. Spherical conductive bumps are formed at the positions of the electrodes. The electrodes are so arranged as to contact a common plane. Spherical bumps constituting a group to be connected to the outside protrude above the spherical semiconductor element such that a predetermined gap is formed between a plane or a spherical surface capable of contacting the spherical bumps and the surface of the spherical semiconductor element. The spherical semiconductor device is connected to various circuit boards or another semiconductor device through the spherical bumps. This affords easy and accurate electrical connections to the outside.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: June 21, 2005
    Assignees: Nippon Steel Corporation, Ball Semiconductor Corporation
    Inventors: Kohei Tatsumi, Kenji Shimokawa, Eiji Hashino, Nobuo Takeda, Atsuyuki Fukano
  • Patent number: 6891259
    Abstract: A semiconductor package including a dam and a method for fabricating the same are provided. The semiconductor package comprises a package substrate, a semiconductor chip attached to the substrate, a TIM formed on the semiconductor chip, a dam that substantially surrounds the TIM, and a lid placed over the TIM to contact a surface thereof. Thus, a TIM can be prevented from flowing down from the original position at high temperatures. Therefore, the performance of the semiconductor package does not deteriorate even at high temperatures.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: May 10, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Hyeok Im, Young-Hoon Ro
  • Patent number: 6882040
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: April 19, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Futoshi Hosoya
  • Patent number: 6879033
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: April 12, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Futoshi Hosoya
  • Patent number: 6878875
    Abstract: A small form factor transceiver module that incorporates an externally modulated laser (EML). The transceiver module has a transmitter optical subassembly with a header assembly having a base with a platform extending through. The platform has a plurality of conductive traces extending through the platform for making connections on both sides of the base. A thermoelectric cooler (TEC) is used to dissipate heat from a laser within the header assembly. The TEC dissipates heat sufficiently to allow the EML to be used in the header assembly. In this manner, EMLs can be used in relatively small optical devices, including small form factor transceivers that comply with the XFP standard. The XFP modules with EMLs can be used for longer links than XFPs without EMLs. In addition, EMLs can be stabilized using TECs so that XFP modules can be used for DWDM-type applications.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: April 12, 2005
    Assignee: Finisar Corporation
    Inventors: Lewis B. Aronson, Giorgio Giaretta, Stefano Schiaffino, Dev E. Kumar, T. G. Beck Mason
  • Patent number: 6864573
    Abstract: A two piece electronic component heat sink and device package comprising a first piece configured to retain electronic components, and a second piece having a hinge region configured to moveably connect the second piece to the first piece, and a snap lock region opposite the hinge region, the snap lock region configured to secure the second piece to the first piece. A two piece electronic component heat sink and device package for a circuit board comprising: a first piece having an index slot for retaining said circuit board, and a second piece having a hinge region configured to pivotably connect the second piece and the first piece, and a snap lock region configured to secure the second piece to the first piece.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: March 8, 2005
    Assignee: DaimlerChrysler Corporation
    Inventors: Michael F Robertson, Gary L Brown
  • Patent number: 6853066
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: February 8, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Futoshi Hosoya
  • Patent number: 6849947
    Abstract: The semiconductor device of the invention includes transistors for a driver and dummy patterns formed to be adjacent to the end portion of each output bit group constituting a cathode driver, anode drivers and anode drivers.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: February 1, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshinori Hino, Naoei Takeishi
  • Patent number: 6841865
    Abstract: A semiconductor device that has a semiconductor die having at least two opposing major electrodes and a control electrode. Conductive clips, each having a base portion and a contact portion, are connected to respective electrodes at their bases by a respective layer of conductive material. A passivation layer is disposed on at least one of the electrodes and surrounds the layers of conductive material. The base portion and the contact portion of one of the clips are connected by an extension, which extends between the major surfaces of the semiconductor die.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: January 11, 2005
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Publication number: 20040251558
    Abstract: A chip-type solid electrolytic capacitor comprises capacitor elements. A cathode terminal comprising a plate-like conductor is interposed between cathode layers of the capacitor elements. The capacitor elements are bonded to each other by a bonding agent such as a solder or a conductive adhesive. The cathode terminal is provided with a through hole formed at a portion to be brought into contact with each of the capacitor elements. Bonding surfaces of the capacitor elements are directly connected at the through hole.
    Type: Application
    Filed: June 10, 2004
    Publication date: December 16, 2004
    Applicants: NEC TOKIN CORPORATION, NEC TOKIN TOYAMA, LTD.
    Inventors: Fumio Kida, Makoto Nakano
  • Patent number: 6825558
    Abstract: The present invention relates to a carrier module for micro-BGA (&mgr;-BGA) type device which is capable of testing a produced device without damaging to a solder ball thereunder after being rapidly connected to a test socket. A carrier module for a &mgr;-BGA type device according to the present invention comprises: an upper and lower carrier module body formed with protrusions at the upper and lower portions thereof; a device receiving unit inserted to the upper carrier module body for receiving a &mgr;-BGA type device; and a spring secured elastically to the upper and lower protrusions by being inserted thereto.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: November 30, 2004
    Assignee: Mirae Corporation
    Inventor: Sang Jae Yun
  • Patent number: 6812553
    Abstract: An electrically isolated and thermally conductive double-sided pre-packaged IC component, stamped lead members, drain pads, source pads, gate runner, and a MOSFET, IGBT, etc. are positioned between a pair of ceramic substrate members. Layers of solderable cooper material are directly bonded to the inner and outer surfaces of the substrate members.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: November 2, 2004
    Assignee: Delphi Technologies, Inc.
    Inventors: Erich William Gerbsch, Ralph S. Taylor
  • Patent number: 6806561
    Abstract: An electronic apparatus of the present invention comprises an electronic circuit board; an electrically conductive casing for encasing the electronic circuit board; a semiconductor element module electrically connected to the electronic circuit board; and a resin fixture intervening between the electrically conductive casing and the semiconductor element module, the resin fixture mounted with the semiconductor element module and fitted to the electrically conductive casing. As a result, the resin fixture can suppress a transfer of heat generated in the electronic circuit board to the semiconductor element module.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: October 19, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Akihiro Kondoh
  • Publication number: 20040195662
    Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluorethylene, filled with fibers which may be glass fibers or ceramic fibers.
    Type: Application
    Filed: January 10, 2003
    Publication date: October 7, 2004
    Applicant: KYOCERA AMERICA, INC.
    Inventors: Jeffrey Venegas, Paul Garland, Joshua Lobsinger, Linda Luu
  • Patent number: 6791184
    Abstract: A support assembly for supporting an integrated circuit package with an array of solder columns extending from a bottom surface of the integrated circuit package to a circuit board preferably includes: a pair of shims for supporting the integrated circuit package, the shims being positioned along opposite edges of the integrated circuit package and placed between and abutting the integrated circuit package and the circuit board; and a retention clip for aligning and securing in place the pair of shims.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: September 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeffrey L Deeney, Laszlo Nobi, Joseph D. Dutson
  • Patent number: 6787900
    Abstract: A semiconductor module (18) includes a ring-shaped metal frame (13) having a bottom surface for contact with a top surface of an external heat sink (11) and serving as a mounting surface. The ring-shaped metal frame (13) has a flange (20) along an inner periphery thereof for engagement with an outer peripheral part of an insulating substrate (17) at a first main surface of a ceramic plate (1). The metal frame (13) is fastened to the external heat sink (11) by screws (12) or bonded to the external heat sink (11) with an adhesive. The flange (20) of the metal frame (13) fastened or bonded to the external heat sink (11) presses the outer peripheral part of the insulating substrate (17) toward the external heat sink (11). This pressing force holds the insulating substrate (17) in pressure contact with the external heat sink (11). The semiconductor module (18) avoids the problem of a decreasing pressing force resulting from deformation to ensure a satisfactory heat dissipating property over a long period of time.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: September 7, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Shinohara, Akira Fujita, Takanobu Yoshida
  • Publication number: 20040159940
    Abstract: This is a semiconductor power module provided with: a ceramic substrate; a metallic plate bonded to a surface of this substrate; a cylindrical metallic flange which is hermetically bonded to a surface of substrate or the metallic plate; a ceramic housing for hermetically sealing an opening of the metallic flange; and at least one or more semiconductor chips soldered to the metallic plate. The metallic flange is made of metal with a low thermal expansion coefficient. A hermetically sealed container is created by welding the metallic flange, the ceramic substrate and the housing with silver brazing. Moreover, external collector, emitter and gate electrodes are bonded on the housing by using the silver brazing. The collector, emitter and gate conductive pillars are respectively connected to the external collector, emitter and gate electrodes with calking. Thus, this hermetically sealed container is strong in mechanical strength and high in explosion-proof durability and excellent in moisture resistance.
    Type: Application
    Filed: February 19, 2004
    Publication date: August 19, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Michiaki Hiyoshi
  • Patent number: 6756667
    Abstract: This is a semiconductor power module provided with: a ceramic substrate; a metallic plate bonded to a surface of this substrate; a cylindrical metallic flange which is hermetically bonded to a surface of substrate or the metallic plate; a ceramic housing for hermetically sealing an opening of the metallic flange; and at least one or more semiconductor chips soldered to the metallic plate. The metallic flange is made of metal with a low thermal expansion coefficient. A hermetically sealed container is created by welding the metallic flange, the ceramic substrate and the housing with silver brazing. Moreover, external collector, emitter and gate electrodes are bonded on the housing by using the silver brazing. The collector, emitter and gate conductive pillars are respectively connected to the external collector, emitter and gate electrodes with calking. Thus, this hermetically sealed container is strong in mechanical strength and high in explosion-proof durability and excellent in moisture resistance.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: June 29, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Michiaki Hiyoshi
  • Publication number: 20040119161
    Abstract: The present invention provides an economical package for housing semiconductor chip that allows a semiconductor chip to operate normally and stably over long periods by efficiently transferring heat generated during the operation of the semiconductor chip to the package mount substrate.
    Type: Application
    Filed: December 2, 2003
    Publication date: June 24, 2004
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., A.L.M.T. CORP.
    Inventors: Hirohisa Saito, Takashi Tsuno, Chihiro Kawai, Shinya Nishida, Motoyoshi Tanaka
  • Publication number: 20040099940
    Abstract: A semiconductor device that has a semiconductor die having at least two opposing major electrodes and a control electrode. Conductive clips, each having a base portion and a contact portion, are connected to respective electrodes at their bases by a respective layer of conductive material. A passivation layer is disposed on at least one of the electrodes and surrounds the layers of conductive material. The base portion and the contact portion of one of the clips are connected by an extension, which extends between the major surfaces of the semiconductor die.
    Type: Application
    Filed: November 22, 2002
    Publication date: May 27, 2004
    Applicant: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 6742169
    Abstract: In the driver for driving display having an anode driver, a cathode driver, and memory portions of a semiconductor device of the invention, anode driver regions connected to the memory portions are laid out equally in the chip, and SRAMs and are arranged equally in the vicinity of each of anode driver regions so that drawing of wiring becomes easy and size of the chip is miniaturized.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: May 25, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshitaka Haraguchi, Naoei Takeishi, Yoshinori Hino
  • Patent number: 6734548
    Abstract: A system for providing electrical contacts between a die and an electrical device includes a package having a first major surface, a second major surface, a first scalloped edge, a second scalloped edge, and a solid end adapted for insertion into a slot. The solid end for carries power to the die or input/output signals. The scalloped edges also carry power. The package includes a plurality of electrical pins which carry input/output signals as well as power. The socket of the system includes a base having an opening therein adapted to receive the package. A cover with openings for receiving the pins covers the base. A power contact unit includes a pair of scalloped edges and a slot. The power contact unit and the cover moves with respect to the base of the socket.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: May 11, 2004
    Assignee: Intel Corporation
    Inventor: Donald T. Tran
  • Publication number: 20040036183
    Abstract: A semiconductor package including a dam and a method for fabricating the same are provided. The semiconductor package comprises a package substrate, a semiconductor chip attached to the substrate, a TIM formed on the semiconductor chip, a dam that substantially surrounds the TIM, and a lid placed over the TIM to contact a surface thereof. Thus, a TIM can be prevented from flowing down from the original position at high temperatures. Therefore, the performance of the semiconductor package does not deteriorate even at high temperatures.
    Type: Application
    Filed: August 21, 2003
    Publication date: February 26, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yun-Hyeok Im, Young-Hoon Ro
  • Publication number: 20040021216
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Application
    Filed: July 3, 2003
    Publication date: February 5, 2004
    Inventor: Futoshi Hosoya
  • Patent number: 6677669
    Abstract: A co-package semiconductor device including an outer clip in the form of a metal can includes also two semiconductor dies, at least one of which uses the outer clip as an electrical connector. An inner clip is used to dispose one of the dies within the outer clip. The inner clip may be insulated from the outer clip by an insulating layer.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: January 13, 2004
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 6670698
    Abstract: A packaged electronic device includes connection contacts that are formed on the contact pads on the second surface of the substrate. In contrast to the prior art, the connection contacts are not solder contacts but are formed of nickel/aluminum plated copper and are therefore harder and less malleable and subject to deformation than prior art solder balls. The connection contacts are formed to align with, and contact, attachment pads formed on the motherboard or other system component. A tension device is then used to mechanically attach the packaged electronic device of the invention to the motherboard.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: December 30, 2003
    Assignee: Amkor Technology, Inc.
    Inventors: Thomas P. Glenn, Steven Webster, Roy Dale Hollaway
  • Patent number: 6657294
    Abstract: A data carrier (1) includes an IC module (3), having a substrate (4), and a conductor configuration (5) connected to the substrate (4), and an IC (2) connected to the substrate (4), and connecting leads (10, 11) between the conductor configuration (5) and the IC (2), and a cover (12) of an electrically insulating material, which cover (12) shrouds the IC (2) and the connecting leads (10, 11) and the portions (13, 14, 15) of the conductor configuration (5) The data carrier (1) is equipped with a protection mechanism (20) that provides protection against damage to at least a part of the IC module (3) when the IC module (3) is bent or twisted, which protection mechanism (20) forms a part of the IC module (3), consists of a ductile material, and is formed by a layer-shaped, preferably net-like, cap which is encased in the cover (12) up to the substrate means (4).
    Type: Grant
    Filed: May 23, 2001
    Date of Patent: December 2, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Marcus Toth, Joachim Heinz Schober, Peter Schmallegger, Veronika Sauer
  • Patent number: 6624448
    Abstract: A semiconductor device having a supporting member that reduces a resonance phenomenon. A pair of reinforcing members is fixed on a gate drive substrate with spacers interposed there between and upright portions of the pair of reinforcing members are fastened with screws on a side wall of a cathode flange. A spacer is fixed on the gate drive substrate and a projection of the spacer is inserted in an engaging member fixed on the bottom of the cathode fin electrode and thus fixed on the bottom of the cathode fin electrode. The pair of upright portions as the first and second supporting points and the projection of the spacer as the third supporting point stably support the gate drive substrate on the cathode fin electrode without freedom of rotation at the three positions arranged to surround an opening.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: September 23, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazunori Taguchi, Kazuhiro Morishita, Kenji Oota