Abstract: A miniature semiconductor apparatus is outstanding in reflow resistance, temperature cycle property, and PCT resistance corresponding to high density packing, high densification, and speeding up of processing. The semiconductor apparatus has at least one stress cushioning layer on a semiconductor element with an electrode pad formed, having a conductor on the stress cushioning layer, having a conductor for conducting the electrode pad and conductor via a through hole passing through the stress cushioning layer between the electrode pad and the conductor, having an external electrode on the conductor, and having a stress cushioning layer in an area other than the area where the external electrode exists and a conductor protection layer on the conductor, wherein the stress cushioning layer includes crosslinking acrylonitrile-butadiene rubber having an epoxy resin which is solid at 25° C. and a carboxyl group.

Abstract: The present invention relates to a carrier module for micro-BGA(&mgr;-BGA) type device which is capable of testing a produced device without damaging to a solder ball thereunder after being rapidly connected to a test socket. A carrier module for a &mgr;-BGA type device according to the present invention comprises: an upper and lower carrier module body formed with protrusions at the upper and lower portions thereof; a device receiving unit inserted to the upper carrier module body for receiving a &mgr;-BGA type device; and a spring secured elastically to the upper and lower protrusions by being inserted thereto.

Abstract: Microelectronic assemblies are encapsulated using disposable frames. The microelectronic assemblies are disposed within an aperture defined by a frame. The aperture is covered by top and bottom sealing layers so that the frame and sealing layers define an enclosed space encompassing the assemblies. The encapsulant is injected into this closed space. The frame is then separated from the encapsulation fixture and held in a curing oven. After cure, the frame is cut apart and the individual assemblies are severed from one another. Because the frame need not be held in the encapsulation fixture during curing, the process achieves a high throughput.

Abstract: A microelectronic device structure includes a package flange with a body having a body upper surface, a substantially circular body interior sidewall defining an opening in the body upper surface, and a substantially circular inlay made of CVD diamond. The inlay is received into the substantially circular opening and has an inlay exterior sidewall which is adjacent to the body interior sidewall and is brazed thereto. The inlay has an inlay upper surface that is substantially coplanar with the body upper surface. A microelectronic device is affixed to the inlay upper surface.

Abstract: A substrate has a top surface for receiving a semiconductor die. An antenna is patterned on the bottom surface of the substrate. The antenna is accessible by coupling it to a via and, through the via, to a substrate signal bond pad and a semiconductor die signal bond pad. In one embodiment, there is at least one via in the substrate. The at least one via provides an electrical connection between a signal bond pad of the semiconductor die and the printed circuit board. The at least one via provides an electrical connection between a substrate bond pad and the printed circuit board. The at least one via also provides an electrical connection between the signal bond pad of the semiconductor die and a land that is electrically connected to the printed circuit board.

Abstract: The present invention relates to a capsule (1) for at least one high power transistor chip (17) for high frequencies, comprising an electrically and thermally conductive flange (10), at least two electrically insulating substrates (15), and at least two electrical connections (16), and a cover member, where the high power transistor chip (17) is arranged on the flange (10). The high power transistor chip (17) and the electrically insulating substrates (15) are arranged on the flange (10). The electrical connections (16) are arranged on electrically insulating substrates (15) and the electrically insulating substrates (15) are connected to the flange (10) and open and separate from the high power transistor chip (17).

Abstract: A heatsink assembly and method of fabrication and use for high power RF LDMOS transistors such as those used in mobile telephone basestation pre-antenna amplifiers wherein die attachment to the heatsink flange occurs prior to leadframe/spacer-to-flange bonding. Various bonding methods are disclosed which do not compromise the die-to-flange attachment bond. A unique leadframe/spacer/flange heatsink package is also disclosed which automatically properly orients attachment of the leadframe/spacer to the flange, and provides for a thickened spacer. A unique leadframe having contact projections also avoids later wire bonding. A unique leadframe/spacer/lid combination is disclosed which allows in one step the bonding of the leadframe to the flange, electrically contacting the die, and encapsulation.

Abstract: An LDMOS power package includes a mounting substrate having a surface with one or more alignment pedestals extending therefrom. Each alignment pedestal has a mounting surface facing away from the substrate surface to provide for uniform positioning of various semiconductor elements, e.g., a transistor die or impedance matching capacitors, relative to the substrate surface. The respective pedestal mounting surfaces are preferably conductive, and are electrically coupled to the flange surface, so as to electrically couple the respective capacitor and electrode ground terminals to the flange.

Abstract: A packaged integrated circuit device includes a substrate including a first circuit component mounted thereon, a first conductor extending from the first circuit component, and a dielectric lid. The dielectric lid includes a component mounting surface, a second circuit component mounted on the component mounting surface, and a second conductor extending from the second circuit component. The dielectric lid is adapted to engage with the substrate such that the first circuit component is in electrical communication with the second circuit component. The second circuit component may comprises an impedance matching circuit. The circuit device may also include fastening means for securing the lid to the substrate. The fastening means may comprise an adhesive, solder, or a spring biased member.

Abstract: An object is to suppress resonance phenomenon. A pair of reinforcing members (18) are fixed on a gate drive substrate (7) with spacers (37) interposed therebetween and upright portions (40) of the pair of reinforcing members (18) are fastened with screws on a side wall of a cathode flange. A spacer (118) is fixed on the gate drive substrate (7) and a projection (118a) of the spacer (118) is inserted in an engaging member (119) fixed on the bottom of the cathode fin electrode (5) and thus fixed on the bottom of the cathode fin electrode (5). The pair of upright portions (40) as the first and second supporting points and the projection (118a) as the third supporting point stably support the gate drive substrate (7) on the cathode fin electrode (5) without freedom of rotation at the three positions arranged to surround an opening (49).

Abstract: A hard mask, e.g., a silicon dioxide or silicon nitride film, is used to avoid organic polymer materials in copper plasma etch applications. The hard mask would be deposited as a blanket layer on the Cu metal layer and itself be patterned and etched with a conventional photolithographic resist pattern. The hard mask etch is stopped shortly before the Cu surface is exposed. Halting the hard mask etch before the Cu surface is exposed facilitates the use of conventional cleaning processes following the hard mask etch. The remaining thin layer of hard mask can be etched through during the beginning of the Cu metal etch process. Any remaining hard mask deposited on the Cu metal layer can form a part of a new dielectric layer.

Abstract: Multiple integrated circuit devices in a stacked configuration that uses a spacing element for allowing increased device density and increased thermal conduction or heat removal for semiconductor devices and the methods for the stacking thereof.

Abstract: A very high power semiconductor device package has a heavy flat conductive terminal which carries a semiconductor die. A thin conductive tab is disposed to be continuous with but insulated from the terminal and lies in a plane above the heavy flat terminal. A top electrode of the die is connected to the tab and an insulation housing encloses portions of the adjacent ends of the tab and terminal as well as the die and its connector leads. The free end of the tab may have printed circuit connection fingers. Two notches are cut into the sides of the thin tab at a location closely spaced from the surface of the housing through which the tab extends to provide stress relief for the insulation housing through which the tab extends.

Abstract: The present invention relates to a capsule (1) for at least one high power transistor chip (17) for high frequencies, comprising an electrically and thermally conductive flange (10), at least two electrically insulating substrates (15), and at least two electrical connections (16), and a cover member, where the high power transistor chip (17) is arranged on the flange (10). The high power transistor chip (17) and the electrically insulating substrates (15) are arranged on the flange (10). The electrical connections (16) are arranged on electrically insulating substrates (15) and the electrically insulating substrates (15) are connected to the flange (10) and open and separate from the high power transistor chip (17).

Abstract: A push-in type semiconductor chip has a semiconductor device, a support electrode body bonded to one of the end portions of the semiconductor chip and supported by, and fixed to, a heat spreader at a support fixing portion thereof, a lead electrode body bonded to the other end portion of the semiconductor chip and an insulating/sealing member disposed at the bond portion between the semiconductor chip and the support electrode body and at the bond portion between the semiconductor chip and the lead electrode body. The support electrode body includes a first portion having an outer diameter different from that of the support fixing portion at which the support electrode body is supported and fixed by the heat spreader. By setting a predetermined relationship between the outer diameters of the first portion and the support fixing portion, deformation and breakage of the semiconductor chip during assembly can be prevented.

Abstract: In a housing of a semiconductor device there are provided a plurality of semiconductor chips captivated in a preformed sub-assembly and arranged to present contact areas for connection to anode and emitter electrodes of the semiconductor housing. Electrically conductive contact pin arrangements project from electrically insulated channels in the preformed sub-assembly, an inward end of each of the pin arrangements being so arranged, when urged into its channel, as to provide an electrical connection to a part of the surface of a semiconductor chip. There is a sheet of electrically conductive material, resting on a base level of an inner surface of the emitter electrode and electrically isolated therefrom by an electrically insulating insert, as a means for distributing an electrical signal and making simultaneous contact with the opposite ends of the pin arrangements.

Abstract: An apparatus package for high temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.

Abstract: This is a semiconductor power module provided with: a ceramic substrate; a metallic plate bonded to a surface of this substrate; a cylindrical metallic flange which is hermetically bonded to a surface of substrate or the metallic plate; a ceramic housing for hermetically sealing an opening of the metallic flange; and at least one or more semiconductor chips soldered to the metallic plate. The metallic flange is made of metal with a low thermal expansion coefficient. A hermetically sealed container is created by welding the metallic flange, the ceramic substrate and the housing with silver brazing. Moreover, external collector, emitter and gate electrodes are bonded on the housing by using the silver brazing. The collector, emitter and gate conductive pillars are respectively connected to the external collector, emitter and gate electrodes with calking. Thus, this hermetically sealed container is strong in mechanical strength and high in explosion-proof durability and excellent in moisture resistance.

Abstract: Microelectronic assemblies are encapsulated using disposable frames. The microelectronic assemblies are disposed within an aperture defined by a frame. The aperture is covered by top and bottom sealing layers so that the frame and sealing layers define an enclosed space encompassing the assemblies. The encapsulant is injected into this closed space. The frame is then separated from the encapsulation fixture and held in a curing oven. After cure, the frame is cut apart and the individual assemblies are severed from one another. Because the frame need not be held in the encapsulation fixture during curing, the process achieves a high throughput.

Abstract: A mounting substrate and related mounting method for a semiconductor device. The mounting substrate includes a mounting area to which the semiconductor device is to be mounted and fixed by an adhesive, a peripheral channel formed in the mounting substrate so as to surround the mounting area, and radial channels extending radially from the center towards the periphery of the mounting area. An adhesive is applied at least to either the center of the mounting surface of the semiconductor device or the center of the mounting area of the mounting substrate. The semiconductor device is placed on the mounting area and the adhesive flows outwardly along the radial channels, with the adhesive then being cured. The peripheral channel provides control of the amount of adhesive which flows to the outside of the semiconductor device and the mounting area. The adhesive overflow can be adjusted such that adhesive climbs up the sides of the semiconductor device but not reach the upper surface of the device.

Abstract: Large size multi-chip module packages are fitted with a new lid (1) formed of a Kovar™ (5) framed sheet of Alumina (3) no less than 0.04 inches thick to form a new “postless” MCM package 2 (FIG. 4 and FIG. 6) that is tolerant of differential pressures of at least one atmosphere and is reworkable. The rigidity of the Alumina sheet avoids the problem of excess deflection found in the prior lids for the package. It also permits elimination of internal lid support posts, freeing internal area within the MCM package that may be used to seat additional electronic circuitry and/or components.

Abstract: A resin-molded semiconductor device includes: signal leads; a die pad with a central portion elevated above a peripheral portion thereof; support leads, each including a raised portion higher in level than the other portions; and DB paste for use in die bonding. All of these members are encapsulated within a resin encapsulant. The lower part of each of these signal leads protrudes downward out of the resin encapsulant and functions as an external electrode. Each of the support leads is provided with two bent portions to cushion the deforming force. By forming a half-blanked portion in the die pad, the central portion is elevated above the peripheral portion, thus preventing the semiconductor chip from being hampered by the support leads. Accordingly, the size of the semiconductor chip mounted can be selected from a broader range and the humidity resistance of the device can also be improved.

Abstract: A semiconductor component (31) and a method for coupling a semiconductor device (36) to a substrate (81). The semiconductor component (31) includes a saddle (34) and the semiconductor device (36). The saddle (34) has a plurality of sides (51, 52, 53, 54, 55) that form a semiconductor device receiving area (58). The semiconductor device (36) is inserted into the semiconductor device receiving area (58) and secured in the semiconductor device receiving area (58) using tabs (66, 67). The saddle (34) is coupled to the substrate (81) by fasteners (82,83).

Abstract: A semiconductor device includes a semiconductor substrate having front and back surfaces and a heat dissipating metal layer on the back surface. The semiconductor substrate includes side surfaces covering a metal layer. The side surfaces are outwardly tapered and include a pair of upper side surfaces and lower side surfaces. A protrusion bearing semiconductor elements extends from the front surface of the substrate in a direction opposite the back surface of the substrate. The side surfaces of the protrusion are not metal covered. Thus, short-circuiting between wires connected to the semiconductor elements and the metal layer covering the side surfaces is avoided.

Abstract: In order to simplify handling and mounting of chips or chip-like structures/micro-blocks, a method and a device have been developed, by which, depending on the area of use, one or more chips can be assembled to act together and/or act together with other chip-like structures such as micromechanical building elements or microoptical elements. The actual retention of a micro-building-block (1) is achieved by micromechanical tongues (4) acting across holes or cavities (2) in a carrier material (3). Silicon tongues can, for example, be both flexible and sufficiently strong to retain a chip. In this manner, there is assured both precise vertical and horizontal positioning and mechanical retention. Electrical connection to the chip can be effected either by thin film technology or by more conventional wire-bonding.

Abstract: A semiconductor device assembly with a gap to be filled has thermal vias formed in the supporting substrate. After the semiconductor device is connected to the substrate and fill material positioned about the gap to create a seal, a vacuum is drawn through the thermal vias and a pressure applied to the fill material to urge the fill material into the interior of the gap.

Abstract: A power semiconductor switching device comprises a mounting board (110) on which a reverse bias driving circuit (20) for applying a reverse bias between the control electrode and one of two main electrodes of a GTO element (11) housed in a flat package is contained. The mounting board (110) has a through hole through which the main electrode of the GTO element (11) penetrates so that the flat package is located in the proximity of the through hole and the perimeter of the through hole partially surrounds the flat package, and a conducting member formed on one surface of the mounting board (110) and electrically connected to the control electrode of the GTO element (11).

Abstract: A thermally enhanced semiconductor package includes a sheet metal cap having flexible flanges provided with solder contacts for reliable attachment to a circuit board. The package assembly further includes a semiconductor chip with a contact-bearing front surface facing forwardly, and chip bonding contacts overlying the front face of the chip. The flange bonding contacts are coplanar with the chip bonding contacts, or can be brought into coplanar alignment by flexure of the cap. The package can be surface-mounted to a circuit board by placing the package onto pads of solder paste, and then heating the assembly to melt the solder paste in order to join the bonding contacts on the chip and on the flange to corresponding contacts on the circuit board.

Abstract: In a gate unit (47) for a hard-driven GTO (10), at least some of the electronic components (37, . . , 42) needed for driving are arranged on a printed circuit board (34). The printed circuit board (34) encloses the GTO (10), in order to achieve low-inductance contact, in a plane lying between the anode side and the cathode side of the GTO (10) parallel to the semiconductor substrate (17) of the GTO (10) and is directly connected to the cathode contact (14) and the gate connection (22) of the GTO (10). A compact structure with, at the same time, improved mechanical stability is achieved in such a gate unit in that the components (37, . . , 42) are arranged on the printed circuit board (34) around the GTO (10), in the immediate vicinity of the GTO (10).

Abstract: Terminal pins with two lateral portions and a bridge-shaped elevated middle portion are provided. The terminal pin and perpendicularly rising hybrid circuit typically together have an inverted T shape. On the one hand, the hybrid circuit stands on its own on the substrate without further means of assistance and can be soldered. On the other hand, the bridge-shaped construction effects a sufficient elasticity and carrying capacity relative to swivellings, or respectively, accelerations, as well as effecting the presence of two defined support surfaces whose co-planarity is guaranteed by the springing configuration of the terminal pins.

Abstract: A high-power high-voltage transistor has four or more semiconductor dies mounted in thermal contact on a metal flange. Each die has a flat lower surface with a drain (collector) region formed over at least 80 percent of its lower surface. A gate (base) region and a source (emitter) region are formed respectively on upper surfaces of the die. The drain region is seated in direct electrical and thermal contact with the flange, so that the flange serves as a drain lead for the transistor die. The die has a drain-source breakdown voltage or collector-emitter breakdown voltage) on the order of one kilovolt or higher and an area of one hundred thousand square mils or larger. Molybdenum tabs between the drain (collector) region and the flange protect the die from thermally-induced stresses. The dies can be MOSFET power transistors, bipolar junction transistors or other solid-state devices. An oval lead frame can be employed for connecting to the source regions.

Abstract: A method of producing a semiconductor device having a heat dissipating metal layer wherein the number of patterning steps is reduced, laser dicing produces a better profile, and first and second matal layers are prevented from separating from each other, and a semiconductor device produced by the method. The number of patterning steps is reduced by employing a flat exposure step for photoresist with mask alignment, A better appearance is obtained by forming the metal layers which connect the semiconductor devices with each other from a first metal layer having a lower melting point and a second metal layer having a higher melting point and severing the first metal layer and the second metal layer successively, from the first metal layer side. A second metal layer is prevented from peeling by preventing oxidation of the plated feeder layer through plating of the second metal layer.

Abstract: An apparatus includes a circuit positioned in a housing, which circuit includes an input/output module having a parasitic power sub-module. The circuit further includes a scratchpad memory, coupled to the input/output module; a programmable memory, coupled to the scratchpad memory; and a control module, coupled to the input/output module, the scratchpad memory and the programmable memory. In certain variations, the input/output module further includes at least one of a one-wire bus and a three-wire bus in addition to a bus arbitrator.

Abstract: An electronic device cooling arrangement includes a heat sink bonded to a substrate above a chip on the substrate, the heat sink having a mounting section bonded to the substrate, a face panel section suspended above the chip and defining a tapered center through hole, and a supporting frame section connected between the face panel section and the mounting section, and a tapered heat conductive block mounted in the tapered center through hole and bonded to the chip for quick dissipation of heat from the chip.

Abstract: Substrates having a wide range of thickness, and intended to be overmolded with a plastic package body, are accommodated in a common mold. The top surface of the substrate is provided with a dam structure, which may be formed as an additional layer on the substrate, and which is preferably in the form of a square ring. A groove (channel) is machined (e.g., by routing) into the surface of the dam structure. The top mold half, having a cavity for forming the package body, is provided with a sealing structure at the periphery of the cavity. The sealing structure has a ridge fitting into the channel of the dam structure. The depth of the groove in the dam structure is readily adjusted to ensure uniform clamping pressure of the top mold half on the substrate, so that liquid molding compound is contained within the cavity and so that undue pressure is not exerted on the substrate.

Abstract: An RF power transistor package is configured for mounting to a heat sink in a multi-layer pc board, and includes a direct top side electrical ground path from a transistor chip located atop a ceramic substrate to a mounting flange, without passing through the ceramic substrate by way of metal plating an outer surface of the ceramic substrate to electrically connect a top mounted metal lead to the flange. A direct ground path from the transistor chip to the mounting flange is also provided by way of plated via holes through the ceramic substrate. The top side ground path is also configured to connect with the middle ground reference layer of the multi-layer pc board when the mounting flange is secured to the heat sink, so that a unified ground potential is seen by the transistor at both the middle layer and heat sink.

Abstract: A semiconductor die is attached to a transistor package by a plurality of resilient clamping members, which are bonded at one end to a top surface of the semiconductor die and at another end to a stable surface, such as an emitter, collector, or base lead frame, of the transistor package. The shape and composition of the clamping members provides a resilient force that causes a bottom surface of the die to make and maintain substantially uniform and constant contact with the die attach area of the transistor package, e.g., a mounting flange or non-conductive substrate. The clamping members are preferably conductive and can conduct current from respective transistor cell locations on the die to the respective lead frames to which the clamping members are bonded.

Abstract: A top surface of a protective cover of an IC component package is provided with a centered-protrusion, e.g., such as a cylindrical peg, that extends above the cover. A retaining-spring is formed by twisting a resilient (e.g., metal) metal strip into a ribbon-like shape having opposing ends that extend from a curvelinear bottom surface. The bottom surface of the retaining-spring is provided with an opening configured to mate with the centered protrusion on the package cover, such that the opposing ends of the retaining-spring extend away from the package cover at substantially the same, albeit reverse angles. In order to mount the IC package to a heat sink, the bottom surface of the retaining-spring may be compressively mated onto the package cover at the same time the package is inserted between two substantially parallel walls protruding from the heat sink surface, wherein the walls are distanced from each other.

Abstract: An integral semiconductor package and mounting structure in which a lid for sealing a semiconductor chip on a platform includes flanges extending beyond the platform with the flanges having holes for receiving screws for mounting the package to a heat sink. The flanges are flexed into engagement with a heat sink thereby maintaining the package in yieldable pressure engagement with the heat sink.

Abstract: A package for relatively high power transistors including heat conducting mounting flange having a relatively large "footprint" relative to the area covered by at least one active chip supported thereby and comprised of a plurality of bipolar silicon-carbide transistors. The transistors are located on a dielectric substrate brazed to the flange. A plurality of screw mounting holes, preferably eight in number, are included in the mounting flange adjacent the outer edge of the dielectric substrate so as to surround the chip. Mounting screws in the eight mounting holes together with a relatively large flange/ground plane interface significantly improves heat dissipation for the heat generated by the silicon carbide transistors by promoting radial heat spreading through the heat conductive metal flange.

Abstract: A resin molded type semiconductor device having a structure, by which a semiconductor element can be accurately positioned on the heat sink and simultaneously a scrubbing operation is performed on the semiconductor element. This resin molded type semiconductor device has a heat sink, a semiconductor element fixed to the heat sink with a thermal conductive adhesive agent, an electrode electrically connected to the semiconductor element, a plurality of projections on the heat sink, and a sealing resin sealing the heat sink, the semiconductor element, and the electrode. The plurality of projections are used for positioning the semiconductor element and are loosely in contact with at least two sides of the semiconductor element on the heat sink.

Abstract: A serial-port memory is positioned in a substantially token-shaped body. The substantially token-shaped body has a perimeter and a flange extending from a portion of the perimeter. The serial-port memory comprises a serial port, a scratchpad memory coupled to the serial port, a second memory coupled to the scratchpad memory; and control logic coupled to the serial port and the scratchpad and second memories. The control logic transfers information from the scratchpad memory to the second memory as a block pursuant to a block transfer command received at the serial port.

Abstract: An optical device is disclosed which comprises a base including a lower cylindrical base member having a common central line and a first diameter and having top and bottom surfaces, a first electrode layer formed on the top surface of the lower base member, a dielectric layer formed on the first electrode, a second electrode layer formed on the dielectric layer, and an upper base member formed on the second electrode layer, the upper base member including a first cylindrical member having the common central line and the first diameter and having top and bottom surfaces, the bottom surface of the first cylindrical member faced on the second electrode layer and a second cylindrical member having the common central line and a second diameter smaller than the first diameter and having a top surface and a bottom surface faced on the top surface of the first cylindrical member; elongated leads supported by the base, the leads being elongated so as to protrude from the bottom surface of the lower base member; a ring

Abstract: A communication module comprises a substantially token-shaped body with first and second electrically conductive surface areas. The first and second surface areas are electrically isolated from each other and circuitry is positioned in the cavity within the substantially token-shaped body, and has connections to said first and second areas. The substantially token-shaped body has a perimeter around it. The first and second electrically conductive surface areas form a substantial portion of the substantially token-shaped body. The first and second electrically conductive surface areas form a cavity. One of the surface areas forming a flange around the perimeter of the substantially token-shaped body. The flange preferably resides in one geometric plane. The circuitry provides for the receipt and transmission of digital signals that are determined as voltage differences between said first and second areas.

Abstract: A semiconductor IC device has an input/output circuit and an internal logic circuit connected with the input/output circuit formed in a main surface of a semiconductor substrate of a generally rectangular shape. The input/output circuit is divided into at least two input/output circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in a direction substantially parallel with a pair of opposite sides of the substrate. The internal logic circuit is divided into at least three logic circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in the above-mentioned direction. Each of the input/output circuit blocks is sandwiched by and electrically connected with adjacently arranged two of the logic circuit blocks.

Abstract: A high-power RF feedback resistor assembly includes a flat film resistor or other flat device mounted in thermal communication onto a bushing which is, in turn, mounted directly onto a cooling flange of an associated power transistor. A bushing has a vertical bolt hole through it to receive a threaded screw. The bushing can have a cutout beneath the flat vertical surface on which the resistor is mounted to provide clearance for a printed circuit board.

Abstract: In a .[.semicondur.]. .Iadd.semiconductor .Iaddend.device comprising a semiconductor element, a pair of electrodes provided on the opposite sides of the semiconductor element, and a cylindrical member provided to surround the semiconductor element and to be in engagement with the pair of electrodes, each of the electrodes has a thread portion on its outer perphery, and the cylindrical member has a thread portion on its inner peripheral surface screwed onto each of the thread portions of the electrodes, thereby to provide a hermetic seal for the semiconductor element.