Abstract: An integrated conductive polymer-solder ball structure is provided. The integrated conductive polymer-solder ball structure comprises a sputter seed layer applied to a wafer structure, one or more conductive polymer pad structures applied to the sputtered seed layer at locations on the wafer structure where one or more solder ball structures will be formed, an electroplating layer applied to portions of the one or more conductive polymer pad structures where a photoresist layer has been exposed, and a solder ball formed on each of the electroplating layers thereby forming the one or more solder ball structures.

Abstract: The present invention aims to provide electroconductive microparticles which are less likely to cause disconnection due to breakage of connection interfaces between electrodes and the electroconductive microparticles even under application of an impact by dropping or the like and are less likely to be fatigued even after repetitive heating and cooling, and an anisotropic electroconductive material and an electroconductive connection structure each produced using the electroconductive microparticles. The present invention relates to electroconductive microparticles each including at least an electroconductive metal layer, a barrier layer, a copper layer, and a solder layer containing tin that are laminated in said order on a surface of a core particle made of a resin or metal, the copper layer and the solder layer being in contact with each other directly, the copper layer directly in contact with the solder layer containing copper at a ratio of 0.

Abstract: A semiconductor device, a semiconductor package, and a package stack structure include a semiconductor substrate, a first bonding pad disposed on a first surface of the semiconductor substrate, and a first pillar disposed on the first bonding pad. An upper surface of the first pillar has a concave shape. Side surfaces of the first pillar are substantially planar.

Abstract: A microelectronic assembly includes units superposed on one another to form at least one stack having a vertical direction. Each unit includes one or more microelectronic devices and has top and bottom surfaces. Top unit terminals are exposed at the top surfaces and bottom unit terminals are exposed at the bottom surfaces. The top and bottom unit terminals are provided at a set of ordered column positions. Each top unit terminal of the set, except the top unit terminals at the highest ordered column position, is connected to a respective bottom unit terminal of the same unit at a next higher ordered column position. Each bottom unit terminal of the set, except the bottom unit terminals of the lowest unit in the stack, is connected to a respective upper unit terminal of the next lower unit in the stack at the same column position.

Abstract: An electroless plating process includes providing a semiconductor substrate which has a substrate and a copper pillar disposed on the substrate; providing a tin-silver plating solution includes 0.1-50 wt % tin and 1×105-2 wt % silver; and performing a reduction reaction, wherein the semiconductor substrate is disposed in the tin-silver plating solution for making tin and silver of the tin-silver plating solution deposit jointly on the copper pillar surface to form a tin-silver co-deposition layer. The tin-silver co-deposition layer is able to enhance the coupling strength between the copper pillar of the semiconductor substrate and the other semiconductor substrate and is also able to reduce the time and cost of the process performing tin-plating and silver-plating separately.

Abstract: A semiconductor device includes a first substrate including a surface, and a pad array on the surface of the substrate, wherein the pad array comprises a first type pad and a second type pad located on a same level. The semiconductor device further includes a conductive bump connecting either the first type pad or the second type pad to a second substrate and a via connected a conductive feature at a different level to the first type pad and the via located within a projection area of the first type pad and directly contacting the first type pad. The semiconductor device also has a dielectric in the substrate and directly contacting the second type pad, wherein the second type pad is floated on the dielectric.

Abstract: Provided is a wireless module whose size can be made smaller. The wireless module includes: a first substrate on which an antenna is mounted; a second substrate which opposes the first substrate and on which an electronic component is mounted; and a plurality of electric conductors which connect the first substrate and the second substrate and which transmit a signal between the antenna and the electronic components, wherein the plurality of electric conductors are disposed between the first substrate and the second substrate in series in a substantially vertical direction with respect to mounting surfaces of the first substrate and the second substrate.

Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

Abstract: A cylindrical molding compound supported RDL for IC package is disclosed wherein a central cavity is formed in the center of the molding compound. A plurality of metal pillar is embedded in the molding compound, a redistribution layer is configured on bottom of the plurality of metal pillar; at least one passive element such as a capacitor can be mounted in the central cavity. The bottom of the package is adaptive for at least one chip to mount so that the passive element is close to the chip and therefore simultaneous switching noise (SSN) can be reduced to a minimum at the initial first stage when a power is turned on.

Abstract: A package structure includes an insulation layer, a first conductive layer, a second conductive layer, at least one electronic component, and at least one thermal conduction structure. At least one first conductive via and at least one second conductive via are formed in the insulation layer. The first conductive layer is disposed on a top surface of the insulation layer and contacted with said at least one first conductive via. The second conductive layer is disposed on a bottom surface of the insulation layer and contacted with the second conductive via. The electronic component is embedded within the insulation layer, and includes plural conducting terminals. The plural conducting terminal is electrically connected with the first conductive layer and the second conductive layer through said at least one first conductive via and said at least one second conductive via. Said at least one thermal conduction structure is embedded within the insulation layer.

Abstract: A method includes forming a first plurality of Redistribution Lines (RDLs) over a carrier, and bonding a device die to the first plurality of RDLs through flip-chip bonding. The device die and the first plurality of RDLs are over the carrier. The device die is molded in a molding material. After the molding, the carrier is detached from the first plurality of RDLs. The method further includes forming solder balls to electrically couple to the first plurality of RDLs, wherein the solder balls and the device die are on opposite sides of the first plurality of RDLs.

Abstract: Some of the embodiments of the present disclosure provide a Quad Flat No-Lead package comprising: an outer row of outer peripheral leads disposed on an outer periphery of a bottom surface of the Quad Flat No-Lead package; and an inner row of inner peripheral leads disposed on an inner periphery of the bottom surface of the Quad Flat No-Lead package, wherein each of the inner peripheral leads has a substantially rectangular shape, and wherein the substantially rectangular shape has two rounded corners adjacent to the outer row of outer peripheral leads.

Abstract: A semiconductor device is made by providing a temporary carrier and providing a semiconductor die having a plurality of bumps formed on its active surface. An adhesive material is deposited as a plurality of islands or bumps on the carrier or active surface of the semiconductor die. The adhesive layer can also be deposited as a continuous layer over the carrier or active surface of the die. The semiconductor die is mounted to the carrier. An encapsulant is deposited over the die and carrier. The adhesive material holds the semiconductor die in place to the carrier while depositing the encapsulant. An interconnect structure is formed over the active surface of the die. The interconnect structure is electrically connected to the bumps of the semiconductor die. The adhesive material can be removed prior to forming the interconnect structure, or the interconnect structure can be formed over the adhesive material.

Abstract: In an embodiment, an electronic component includes a dielectric core layer, one or semiconductor dies comprising a first major surface, a first electrode arranged on the first major surface and a second major surface that opposes the first major surface. One or more slots are arranged within the dielectric core layer adjacent the semiconductor die and a redistribution structure electrically couples the first electrode to a component contact pad arranged adjacent the second major surface of the semiconductor die. The semiconductor die is embedded in the dielectric core layer and a portion of the redistribution structure is arranged on side walls of the slot.

Abstract: A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

Abstract: A semiconductor package includes a passivation layer overlying a semiconductor substrate, a pillar bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer.

Abstract: A method for forming a package structure is provided, which includes: providing a pre-packaged panel including a first encapsulation layer, which includes multiple integrating units each including at least one semiconductor chip with multiple first pads, and first metal bumps are disposed on the first pads; providing a circuit board including a first surface and a second surface, where the circuit board includes multiple carrying units each including multiple input pads on the first surface and multiple output pads on the second surface; mounting the pre-packaged panel on the first surface to form multiple package units; forming a filling layer by filling a space between the first surface and the pre-packaged panel; forming second metal bumps on the output pads on the second surface; cutting the structure based on the multiple package units to form multiple independent package structures. Accordingly, the package structure improves package efficiency.

Abstract: There is provided a semiconductor device. The semiconductor device includes: a first board; a second board joined to the first board; a connection terminal provided between the first board and the second board and electrically connecting the first board and the second board; and an electronic component on at least one of the first board and the second board. The connection terminal serves as an antenna.

Abstract: A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.

Abstract: A semiconductor device includes a wiring substrate, a sealing resin layer formed on the wiring substrate out of a filler-containing resin and having a one-sided filler content ratio, and at least one semiconductor chip mounted on the wiring substrate such that the semiconductor chip is located offset to be closer to an area where the filler content ratio is relatively low in the sealing resin layer and is sealed in its offset location in the sealing resin layer.

Abstract: A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate and have different cross-sectional areas in a direction parallel or substantially parallel to the principal surface. One of the first and second bumps having a smaller cross-sectional area includes a height adjustment layer disposed in a direction perpendicular or substantially perpendicular to the principal surface.

Abstract: A thermal interface material (TIM) pad is disclosed for dissipating heat from a component. The TIM pad includes a plurality of thermal interface material layers and at least one graphene layer interposed between the plurality of TIM layers. A method for forming the TIM pad includes stacking the plurality of TIM layers with at least one graphene layer interposed between the plurality of TIM layers to reach a length for the TIM pad. The stacked layers are cut corresponding to a thickness for the TIM pad for compression against the component.

Abstract: Embodiments of the invention relates to a method and apparatus for rework of a BGA package. Memory shape material is placed adjacent to a plurality of solder joints of the package. Stimulation is applied to the material, with the stimulation causing the material to change from a non-stimulated shape to a stimulated shape. This stimulation causes an expansion of the material. As the material expands, it exerts a tensile force on the BGA package and an adjacently positioned carrier, causing a separation of the two components, while mitigating collateral heat of adjacently positioned components.

Abstract: Embodiments of the invention relates to a method for rework of a BGA package. Memory shape material is placed adjacent to a plurality of solder joints of the package. Stimulation is applied to the material, with the stimulation causing the material to change from a non-stimulated shape to a stimulated shape. This stimulation causes an expansion of the material. As the material expands, it exerts a tensile force on the BGA package and an adjacently positioned carrier, causing a separation of the two components, while mitigating collateral heat of adjacently positioned components.

Abstract: The present invention relates to a packaging method including the steps: a cementing layer is formed on a carrier board; the functional sides of chips and passive devices are attached to the cementing layer; a sealing material layer is formed on the side of the carrier board to which the chips and the passive devices are attached, and packaging and curing are performed; and the carrier board and the cementing layer are removed. Compared to the prior art, the system-level fan-out wafer packaging method claimed by the present invention first integrates chips and passive devices and then packages the chips and the passive devices together, thereby forming a final packaged product having not single-chip functionality but integrated-system functionality.

Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and a first set of die pads on the device are exposed by forming openings of a first diameter in the photoresist. Pillars of the first diameter are formed by electroplating metal onto the exposed die pads. Then a second photoresist deposited over the first photoresist covers the pillars of the first diameter. Openings of a second diameter are formed in the first and second photoresists to expose a second set of die pads. Pillars of the second diameter are formed by electroplating metal onto the exposed die pads. The photoresists are then removed along with conductive layers on the device used as part of the plating process.

Abstract: A method for fabrication a metal pillar bump packaging structure is provided. The method includes providing a semiconductor substrate; and forming a metal interconnect structure and a dielectric layer exposing a portion of the metal interconnect structure on the semiconductor substrate. The method also includes forming a photoresist layer having an opening with an undercut with a bottom area greater than a top area at the bottom of the opening to expose the metal interconnect structure and a portion of the dielectric layer on the semiconductor substrate; and forming a metal pillar bump structure having a pillar body and an extension part with an enlarged bottom area in the opening and the undercut. Further, the method includes forming a soldering ball on the metal pillar bump structure.

Abstract: A package structure includes a chip, a substrate, wires and a molding compound. The chip includes an active surface, a back surface and bonding pads disposed on the active surface. The substrate includes first and second solder masks, first and second patterned circuit layers and a core layer having a first surface and a second surface. The first patterned circuit layer is disposed on the first solder mask. The core layer disposed on the first solder mask with the first surface partially exposes the first patterned circuit layer. The substrate disposed on the active surface with the first solder mask exposes the bonding pads. The second patterned circuit layer disposed on the second surface. The second solder mask partially covers the second patterned circuit layer. The wires are connected between the first patterned circuit layer and the bonding pads. The molding compound covers the chip, the wire and the substrate.

Abstract: This invention relates to a pressure transmission apparatus for bonding a plurality of chips to a substrate. The pressure transmission apparatus includes a pressure body for applying a bonding force which acts in the bonding direction (B) to the chip. The pressure body has a first pressure side and an opposite second pressure side, both oriented to be transverse to the bonding direction (B). Fixing means are provided to attach to the periphery of the pressure transmission apparatus for fixing of the pressure transmission apparatus on a retaining body in the bonding direction (B). A sliding layer is provided for sliding motion of the pressure body transversely to the bonding direction (B).

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a mask coating over a carrier, coupling an integrated circuit die over the mask coating, and disposing a molding compound around the integrated circuit die. The method includes forming an interconnect structure over the integrated circuit die and the molding compound.

Abstract: An integrated circuit package system includes: providing an internal device; encapsulating the internal device with an encapsulation having an outer surface; and forming a redistribution line having connection points on the outer surface of the encapsulation.

Abstract: A method and apparatus for a reinforced package are provided. A package component may be electrically coupled to a device through a plurality of electrical connections. A molding underfill may be interposed between the package component and the device and may encapsulate the plurality of electrical connections or a subset of the plurality of electrical connections between the package component and the device. The package component may also include a molding compound. The plurality of the electrical connections may extend through the molding compound with the molding underfill interposed between the molding compound and the device to encapsulate the plurality of electrical connections or a subset of the plurality of electrical connections between the package component and the device. The molding underfill may extend up one or more sides of the package component.

Abstract: A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.

Abstract: Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.

Abstract: A chip scale package (CSP) includes a die and a first lead mechanically and electrically coupled to a first surface of the die at a first surface of the first lead. The first surface of the first lead forms a first plane. A second lead is mechanically coupled to a second surface of the die at a first surface of the second lead. The first surface of the second lead forms a second plane. A mold compound at least partially encapsulates the die, forming a CSP. The first plane and the second plane are oriented substantially perpendicularly to a third plane formed by a motherboard surface when the CSP is coupled to the motherboard surface. The CSP includes no wirebonds and the first lead and second lead are on opposing surfaces of the CSP. The third plane of the motherboard may be a largest planar surface of the motherboard.

Abstract: Disclosed herein is an interconnect apparatus comprising a substrate having a land disposed thereon and a passivation layer disposed over the substrate and over a portion of the land. An insulation layer is disposed over the substrate and has an opening disposed over at least a portion of the land. A conductive layer is disposed over a portion of the passivation layer and in electrical contact with the land. The conductive layer has a portion extending over at least a portion of the insulation layer. The conductive layer comprises a contact portion disposed over at least a portion of the land. The insulation layer avoids extending between the land and the contact portion. A protective layer may be disposed over at least a portion of the conductive layer and may optionally have a thickness of at least 7 ?m.

Abstract: Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract: A method for the attachment of a formed adhesive element (34,34?) to a hot bonding part (10) in a practical and efficient way is disclosed. The formed adhesive element may be attached to the hot bonding part by the end-user prior to attachment of the hot bonding part to the substrate. In order to attach the formed adhesive element (34,34?) to the bonding part according to the disclosed invention, the bonding part (10) is heated then is moved in position over the formed adhesive element positioned on a detent of a matrix plate (36). Thereafter the hot bonding part is moved into contact with the formed adhesive element or the formed adhesive element is moved against the hot bonding part. The bonding part, now having the formed adhesive element attached, is ready for attachment to the substrate. One or more formed adhesive elements may be attached to the bonding part. Attachment of the formed adhesive elements to the bonding part may be done manually or mechanically.

Abstract: Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad disposed on a first surface of a first substrate, the interconnect comprising a conductive material, optionally solder or metal, the interconnect avoiding the sides of the mounting pad. A molding compound is applied to the first surface of the first substrate and molded around the interconnect to covering at least a lower portion of the interconnect and a second substrate may be mounted on the interconnect. The interconnect may comprise an interconnect material disposed between a first and second substrate and a molding compound disposed on a surface of the first substrate, and exposing a portion of the interconnect. A sidewall of the interconnect material contacts the mounting pad at an angle less than about 30 degrees from a plane perpendicular to the first substrate.

Abstract: A structure comprises a plurality of connectors formed on a top surface of a first semiconductor die, a second semiconductor die formed on the first semiconductor die and coupled to the first semiconductor die through the plurality of connectors and a first dummy conductive plane formed between an edge of the first semiconductor die and the plurality of connectors, wherein an edge of the first dummy conductive plane and a first distance to neutral point (DNP) direction form a first angle, and wherein the first angle is less than or equal to 45 degrees.

Abstract: A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.

Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.

Abstract: An IC chip package and a chip-on-glass structure using the same are provided. The IC chip package includes an IC chip having a circuit surface, and plural copper (Cu) bumps formed on the circuit surface. Moreover, a non-conductive film (NCF) could be formed on the circuit surface to cover the Cu bumps. The chip-on-glass structure includes a glass substrate, plural electrodes such as aluminum (Al) electrodes formed on the glass substrate, and a conductive film formed on the electrodes. The conductive film contains a number of conductive particles. When the IC chip package is coupled to the glass substrate, the Cu bumps can be coupled to the corresponding electrodes via conductive particles.

Abstract: A packaging substrate includes a holder, a first conductive pad disposed on the holder, a core layer disposed on the holder, a circuit layer disposed on the core layer, a plurality of conductive vias disposed in the core layer, and an insulating protection layer disposed on the core layer, wherein the first electrical pad is embedded in the core layer. By combining the holder on one side of the packaging substrate, cracks due to over-thinness can be prevented during transferring or packaging. A method of fabricating the packaging substrate, a package structure having a holder, a method of fabricating the package structure are also provided.

Abstract: Provided is a semiconductor package including a package substrate having lands, a first semiconductor device mounted on the package substrate and having a bottom surface on which first lines are disposed, and solder balls respectively electrically connected to the lands of the package substrate with the first lines of the first semiconductor device. The first semiconductor device includes a first substrate, and through-substrate via (TSV) plugs that vertically pass through the first substrate. The TSV plugs are respectively vertically aligned with the first lines, overlap first regions corresponding to 70% or less of diameters of the solder balls from central axes of the solder balls, and do not overlap second regions corresponding to the remaining 30% or more of diameters of the solder balls from the central axes of the solder balls. Adjacent ones of the TSV plugs are arranged at irregular intervals with respect to each other.

Abstract: In a semiconductor package, a circuit pattern is arranged in a circuit board and contact pads on the circuit board are connected with the circuit pattern. Contact terminals contact external contact elements on a first surface of the circuit board. An integrated circuit (IC) chip structure is mounted on the circuit board and electrically connected to the inner circuit pattern. An operation controller on the circuit board controls operation of the semiconductor package according to the package users' individual choice.

Abstract: An interposer structure containing a first set of solder balls is placed in proximity to a vacuum distribution plate which has a planar contact surface and a plurality of openings located therein. A vacuum is then applied through the openings within the vacuum distribution plate such that the first set of solder balls are suspended within the plurality of openings and the interposer structure conforms to the planar contact surface of the vacuum distribution plate. A semiconductor chip containing a second set of solder balls is tacked to a surface of the interposer structure. A substrate is then brought into contact with a surface of the interposer structure containing the first set of solder balls, and then a solder reflow and underfill processes can be performed. Warping of the interposer structure is substantially eliminated using the vacuum distribution plate mentioned above.