Abstract: A method of manufacturing a semiconductor device includes providing a layered structure having a hard dielectric layer containing a first dielectric material having a Young's modulus greater than 10 GPa in a central portion of a main surface of a main body comprising a single crystalline semiconductor body, and providing a dielectric stress relief layer containing a second dielectric material having a lower Young's modulus than the first dielectric material, the stress relief layer covering the layered structure and extending beyond an outer edge of the layered structure.

Abstract: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.

Abstract: A substrate for use in semiconductor device assembly has an electrically insulating body with a die mounting surface and an opposite grid array surface. An array of external electrical connection pads is located in the grid array surface. Substrate bond padsare located in the die mounting surface. Interconnects in the insulating body selectively interconnect the substrate bond padsto the external electrical connection pads. Tertiary bond pads are located in the die mounting surface and are electrically isolated from the external electrical connection pads.

Abstract: Provided herein is a bump including a diffusion barrier bi-layer, the bump having: a conductive layer; a first diffusion barrier layer formed on or above the conductive layer, and comprising an alloy of nickel and phosphorus; a second diffusion barrier formed on or above the first diffusion barrier layer, and comprising copper; and a solder layer formed on or above the second diffusion barrier layer. A manufacturing method for producing a bump is also provided.

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first die coupled to the substrate, a first encapsulation layer coupled to the substrate and the first die, and a second encapsulation layer in the first encapsulation layer. The second encapsulation layer includes a set of wires configured to operate as vias. In some implementations, the integrated device includes a set of vias in the first encapsulation layer. In some implementations, the integrated device further includes a second die coupled to the substrate. In some implementations, the second encapsulation layer is positioned between the first die and the second die. In some implementations, the integrated device further includes a cavity in the first encapsulation layer, where the second encapsulation layer is positioned in the cavity. In some implementations, the cavity has a wall that is non-vertical. In some implementations, at least one of the wires is non-vertical.

Abstract: A structure of a semiconductor chip with substrate via holes and metal bumps and a fabrication method thereof. The structure comprises a substrate, at least one backside metal layer, at least one first metal layer, at least one electronic device, and at least one metal bump. The substrate has at least one substrate via hole penetrating through the substrate. The at least one first metal layer and electronic device are formed on the front side of the substrate. The at least one metal bump is formed on the at least one first metal layer. The at least one backside metal layer is formed on the backside of the substrate covering the inner surface of the substrate via hole and at least part of the backside of the substrate and connected to the first metal layer on the top of the substrate via hole.

Abstract: Disclosed herein is a method for manufacturing a semiconductor package. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip.

Abstract: Dual interface modules, and methods for manufacturing the same, are described. A substrate layer is provided with at least one dual interface section. At least two first through-holes are formed in the substrate in each dual interface section. A first connection element is arranged in each first through-hole. Each first connection element is connected to a contact pad that is arranged on a first side of the substrate. Each first connection element is connected to a connection pad that is arranged on a second side of the substrate. At least one electronic element is arranged on the second side of the substrate in each dual interface section. Two second through-holes are formed in the substrate in each dual interface section. Two soldering pads with a first side and a second side are arranged on the second side of the substrate layer.

Abstract: A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate.

Abstract: A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer.

Abstract: Provided is a semiconductor package which may include a package substrate which includes a power supply region and an interconnection region around the power supply region, a plurality of ground terminals and a plurality of power terminals, which are disposed in the power supply region with a dielectric interposed between the ground terminals and the power terminals, wherein the ground terminals and the power terminals extend from a top surface of the package substrate to a bottom surface of the package substrate, and at least one semiconductor chip mounted on the package substrate, the semiconductor chip includes a plurality of ground pads which are commonly connected to a ground terminal of the ground terminals and a plurality of power pads which are commonly connected to a power terminal of the power terminals.

Abstract: A solder powder having an average particle diameter of, for example, 0.05 ?m or more and less than 3 ?m is obtained by a method of producing a solder powder, including the steps of: putting solid or liquid metal, a non-aqueous solvent, and crushing balls having a diameter of 0.05 mm to 5 mm into a container to obtain a mixture; heating the mixture to 150° C. or higher and stirring the mixture; separating the crushing balls from the mixture after the stirring to obtain a mixture of the solder powder and the non-aqueous solvent; and performing solid-liquid separation on the mixture of the solder powder and the non-aqueous solvent to obtain a solder powder.

Abstract: The present invention relates to a printed circuit board which includes: a solder pad on which a solder ball is mounted; an insulator formed on the solder pad; and a protrusion formed under the insulator to support the solder ball when mounting the solder ball and can stably mount the solder ball.

Abstract: A semiconductor device may include a substrate including a first surface and a second surface, a through electrode penetrating the substrate to include a protrusion that protrudes from the second surface of the substrate, and a front side bump electrically coupled to the through electrode and disposed on the first surface of the substrate. The semiconductor device may include a first passivation pattern disposed on the first surface of the substrate to substantially surround a sidewall of the front side bump and may be formed to include an uneven surface, and a second passivation pattern disposed on the second surface of the substrate to include an uneven surface. The protrusion of the through electrode may penetrate the second passivation pattern to protrude from the uneven surface of the second passivation pattern.

Abstract: A method including identifying a first connection location on a chip having a first connection type and a second connection location on the chip having a second connection type, applying a first solder alloy to the first connection location, heating the first solder alloy to a temperature sufficient to cause the first solder alloy to reflow, applying a second solder alloy to the second connection location, and heating the second solder alloy to a temperature sufficient to cause the second solder alloy to reflow.

Abstract: A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior region. A first set of through substrate vias are located within the periphery region, and a second set of through substrate vias are located within the interior region, wherein the second set of through substrate vias are part of a power matrix. The second set of through substrate vias bisect the substrate into a first part and a second part.

Abstract: A semiconductor device includes an extended semiconductor chip including a first semiconductor chip and an extension outwardly extending from a side surface of the first semiconductor chip; and a second semiconductor chip connected to the extended semiconductor chip through a plurality of bumps and electrically connected to the first semiconductor chip. The first semiconductor chip is smaller than the second semiconductor chip. At least one external terminal is provided on the extension.

Abstract: The present application provides an electronic apparatus including a substrate including a first electrode pad, a second electrode pad and an intermediate pad each disposed on one surface of the substrate and separated from one another. An electronic device is disposed on the substrate and including a first electrode unit and a second electrode unit. The first electrode unit has an adhesion surface facing the first electrode pad and the intermediate pad. The second electrode unit has an adhesion surface facing the second electrode pad.

Abstract: In a semiconductor device where a metal circuit layer is disposed over a main planar surface of an insulating substrate, a semiconductor chip is connected by way of a solder over the metal circuit layer, and a metal wiring is connected over the metal circuit layer, in which a solder flow prevention area comprising a linear oxide material is formed between the semiconductor chip and the ultrasonic metal bonding region over the metal circuit layer.

Abstract: A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

Abstract: There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).

Abstract: An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart from one another defining an isolation region between them. A substrate has second vias. Third interconnects and the second interconnects are respectively coupled on opposite surfaces of the package substrate. A first portion of the first vias and a first portion of the second vias are both in the isolation region and are coupled to one another with a first portion of the second interconnects.

Abstract: The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

Abstract: A package substrate includes a core layer having a first surface and a second surface which are opposite to each other, a ball land pad disposed on the first surface of the core layer, an opening that penetrates the core layer to expose the ball land pad, and a dummy ball land disposed on the second surface of the core layer to surround the opening. The dummy ball land includes at least one sub-pattern and at least one vent hole. Related semiconductor packages and related methods are also provided.

Abstract: The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.

Abstract: An integrated circuit package includes a ball arrangement that includes transmitter contact pairs arranged in a first portion of a ball grid array disposed in the integrated circuit package. Each of the transmitter contact pairs include transmitter differential signal contacts. Pairs of the transmitter contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes receiver contact pairs arranged in a second portion of the ball grid array. Each of the receiver contact pairs include receiver differential signal contacts. Pairs of the receiver contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes voltage supply contacts arranged at least between every two pairs of the transmitter contact pairs and the receiver contact pairs.

Abstract: Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a silicon interposer, a fixture mounted to the wafer carrier and comprising a layer of material to provide mechanical support to the die side of the silicon interposer, the fixture being patterned to fill spaces between integrated circuit dies mounted on an interposer; and an adhesive tape disposed on a surface of the fixture for adhering to the surface of a silicon interposer. Additional alternative apparatuses are disclosed.

Abstract: A semiconductor device is provided, which comprises a first semiconductor package, a second semiconductor package, and a connection structure. The first semiconductor package includes a first substrate. The first substrate includes a first region and a second region. The second semiconductor package is mounted on the first semiconductor package. The connection structure electrically connects the second semiconductor package and the first semiconductor package. The connection structure comprises first connection patterns at the first region. The first connection patterns provide a data signal at the first region. The connection structure further comprises second connection patterns at the second region. The second connection patterns provide a control/address signal at the second region. A number of the second connection patterns is less than a number of the first connection patterns.

Abstract: A wiring board includes a first multilayer wiring board having first conductive layers and having a surface, a second multilayer wiring board having second conductive layers and positioned such that the second multilayer wiring board has a surface facing the surface of the first multilayer wiring board, and an adhesive layer including an adhesive sheet and interposed between the first multilayer wiring board and the second multilayer wiring board such that the adhesive layer is adhering the first multilayer wiring board and the second multilayer wiring board. The first multilayer wiring board has a first pad on the surface of the first multilayer wiring board, the second multilayer wiring board has a second pad on the surface of the second multilayer wiring board, and the first pad and the second pad are positioned such that the first pad and the second pad face each other across the adhesive layer.

Abstract: Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.

Abstract: An array of bonding pads including a set of reactive materials is provided on a first substrate. The set of reactive materials is selected to be capable of ignition by magnetic heating induced by time-dependent magnetic field. The magnetic heating can be eddy current heating, hysteresis heating, and/or heating by magnetic relaxation processes. An array of solder balls on a second substrate is brought to contact with the array of bonding pads. A reaction is initiated in the set of magnetic materials by an applied magnetic field. Rapid release of heat during a resulting reaction of the set of reactive materials to form a reacted material melts the solder balls and provides boding between the first substrate and the second substrate. Since the magnetic heating can be localized, the heating and warpage of the substrate can be minimized during the bonding process.

Abstract: A semiconductor device includes a substrate, a sealing portion, a controller, a semiconductor chip, and a plurality of differential signal balls. The substrate has a first surface and a second surface positioned on a side opposite to the first surface. The sealing portion is formed on the first surface of the substrate. The controller is covered with the sealing portion. The semiconductor chip is electrically connected to the controller, and is covered with the sealing portion. The plurality of differential signal balls are formed on the second surface of the substrate. At least some of the plurality of differential signal balls are arranged substantially parallel to one side of the substrate.

Abstract: A curable composition including: an epoxy resin; and an amine curing component including: an aromatic amine curing agent; and a solubilizer including an aliphatic amine, a cycloaliphatic amine, a non-volatile primary alcohol, non-volatile solvent or a mixture thereof. An electronic assembly including: a substrate; an underfill including a cured product of the curable composition on the substrate; and a ball grid array on the underfill is also disclosed.

Abstract: Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.

Abstract: A semiconductor device includes a semiconductor chip, a wiring formed on the semiconductor chip, a passivation film coating the wiring and having an opening for partially exposing the wiring from the passivation film an interposing film formed on a portion of the wiring and facing the opening, and a post bump raisedly formed on the interposing film and with a peripheral edge portion thereof protruding away from the opening more than a peripheral edge of the interposing film in a direction parallel to a surface of the passivation film.

Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

Abstract: According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board includes a first surface and a second surface opposite to the first surface. The controller and the semiconductor chip are covered with the sealing portion. The solder balls are on the second surface of the board. The solder balls include a plurality of solder ball sets each corresponding to a pair of differential input and differential output signals, and the plurality of solder ball sets are arranged substantially parallel to a side of the board.

Abstract: A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a pre-solder treatment. The pre-solder treatment improves the adhesion between the exposed traces (e.g., the non-BOT traces) and a solder resist layer.

Abstract: A semiconductor package substrate includes an insulating substrate, a circuit pattern on the insulating substrate, a protective layer formed on the insulating substrate to cover the circuit pattern on the insulating substrate, a pad formed on the protective layer while protruding from a surface of the protective layer, and an adhesive member on the pad.

Abstract: An assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact being electrically connected with the terminal; a first element having a first surface facing the first surface of the substrate and having a first conductor at the first surface and a second conductor at a second surface, an interconnect structure extending through the first element electrically connecting the first and second conductors; an adhesive layer bonding the first surfaces of the first element and the substrate, at least portions of the first conductor and the substrate conductor being disposed beyond an edge of the adhesive layer; and a continuous electroless plated metal region extending between the first conductor and the substrate conductor.

Abstract: In a semiconductor device including a semiconductor element that produces heat and a substrate on which the semiconductor element is mounted, functions of the substrate are divided between a heat dissipating substrate and a wiring substrate. The heat dissipating substrate has a relatively high thermal conductivity, and includes principal surfaces defined by electric insulators, one of which is provided with an outer conductor located thereon. The wiring substrate is mounted on the upper principal surface of the heat dissipating substrate, has a thermal conductivity lower than that of the heat dissipating substrate, and includes a wiring conductor made mainly of silver or copper and located inside the wiring substrate, the wiring conductor being electrically connected to the outer conductor. The semiconductor element is mounted on the upper principal surface of the heat dissipating substrate and disposed in a through hole of the wiring substrate.

Abstract: Packaging devices and packaging methods are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming a plurality of through-substrate vias (TSVs) in an interposer substrate. The interposer substrate is recessed or a thickness of the plurality of TSVs is increased to expose portions of the plurality of TSVs. A conductive ball is coupled to the exposed portion of each of the plurality of TSVs.

Abstract: This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased.

Abstract: An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

Abstract: Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need.

Abstract: A BGA semiconductor package includes a semiconductor device adhered by adhesive to a substrate, and a conductive micro ball fitted into a through-hole provided in the substrate. A bonding wire electrically connects the semiconductor device and the micro ball to each other. An encapsulation member made of resin encapsulates the semiconductor device, the adhesive, part of the micro ball, and the bonding wire, only on a surface side of the substrate on which the semiconductor device is mounted. At least a part of a bottom surface of the micro ball has an exposed portion as an external connection terminal, which is exposed through the through-hole provided in the substrate as a bottom surface of the encapsulation member.

Abstract: A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip.

Abstract: The present invention relates to a solder ball for semiconductor packaging and an electronic member having such solder ball. Specifically there are provided: a solder ball capable of ensuring a sufficient thermal fatigue property even when a diameter thereof is not larger than 250 ?m as observed in recent years; and an electronic member having such solder ball. More specifically, there are provided: a solder ball for semiconductor packaging that is made of a solder alloy containing Sn as a main element, 0.1-2.5% Ag by mass, 0.1-1.5% Cu by mass and at least one of Mg, Al and Zn in a total amount of 0.0001-0.005% by mass, such solder ball having a surface including a noncrystalline phase that has a thickness of 1-50 nm and contains at least one of Mg, Al and Zn, O and Sn, and an electronic member having such solder ball.

Abstract: Disclosed are flip-chip package structures and methods for an integrated switching power supply. In one embodiment, a flip-chip package structure can include: (i) a die with an integrated switching power supply, where a first surface of the die includes first bumps with different polarities; (ii) a redistribution layer including redistribution layer units, each having a first surface to connect bumps with a same polarity from the first bumps, the redistribution layer having a second surface including second bumps to redistribute polarities; (iii) a lead frame having pins, where a first surface of the lead frame can connect bumps with a same polarity from the second bumps; and (iv) a flip-chip package configured to package the die, the redistribution layer, the first and second bumps, and the lead frame, where a second surface of the lead frame provides electrical connectivity between the integrated switching power supply and a PCB.