Abstract: A semiconductor device including a substrate having a dielectric layer over the substrate and a first conductive feature disposed within the dielectric layer. A metal nitride material is disposed directly on a top surface of the first conductive feature. A metal oxynitride material is disposed directly on a top surface of the dielectric layer, wherein the metal nitride and the metal oxynitride are coplanar. A second conductive feature is disposed over and interfacing the metal nitride material.

Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.

Abstract: A semiconductor device including a substrate having a dielectric layer over the substrate and a first conductive feature disposed within the dielectric layer. A metal nitride material is disposed directly on a top surface of the first conductive feature. A metal oxynitride material is disposed directly on a top surface of the dielectric layer, wherein the metal nitride and the metal oxynitride are coplanar. A second conductive feature is disposed over and interfacing the metal nitride material.

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, first and second lower vias in the insulating layer, first and second lower metal lines provided on the insulating layer and respectively connected to the first and second lower vias, and first and second upper metal lines provided on and respectively connected to the first and second lower metal lines. When viewed in a plan view, the first lower via is overlapped with the second upper metal line, and the second lower via is overlapped with the first upper metal line.

Abstract: A connector structure for electrically contacting with a conductive layer disposed on a substrate is provided. The connector structure comprises a conductive connecting element disposed on the substrate. The conductive connecting element comprises a connecting part and an extending part. The connecting part has a bottom portion electrically contacting with the conductive layer. The extending part laterally extends outwards from a top portion of the connecting part, and the extending part and the connecting part are respectively formed of different materials.

Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads.

Abstract: A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.

Abstract: A method for manufacturing a semiconductor structure includes preparing a semiconductor substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the semiconductor substrate in the memory cell region; forming a bit line structure over the semiconductor substrate in the memory cell region; forming a dielectric layer in the peripheral circuit region and the memory cell region; forming a first opening in the dielectric layer in the memory cell region; filling a silicon filler in the first opening; forming a second opening in the dielectric layer in the peripheral circuit region; forming a sidewall spacer over a sidewall of the second opening; recessing the silicon filler to form a silicon plug, wherein the silicon plug fills a lower portion of the first opening; and forming a first metal silicide over a top surface of the silicon plug, and concurrently forming a second metal silicide in a lower portion of the second opening.

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level.

Abstract: A multi-layer phase change material, including: a multi-layer film structure. The multi-layer film structure includes a plurality of periodic units. The periodic units each includes a first single-layer film phase change material and a second single-layer film phase change material. The first single-layer film phase change material and the second single-layer film phase change material are alternately stacked.

Abstract: An integrated circuit includes first and second metallization levels. The first metallization level includes a first metal routing path. The second metallization level includes a dielectric layer having a via opening formed therein extending vertically through the dielectric layer to reach a top surface of the first metal routing path. A metal plug is deposited at a bottom of the via opening in direct contact with the first metal routing path. A remaining open area of the via opening is filled with a metal material to define a second metal routing path. The metal plug is formed of cobalt or an alloy including cobalt, and has an aspect ratio of greater than 0.3.

Abstract: A semiconductor module includes a first semiconductor chip including a first signal line and a first ground, a mounting board or a second semiconductor chip including a second signal line and a second ground, a signal line coupling bump that couples the first signal line and the second signal line with each other, a first ground coupling bump that couples the first ground and the second ground with each other, a signal line side insulating film including a capacitance that causes a series resonance with an inductance by the signal line coupling bump at a target frequency and a ground side insulating film including a capacitance that causes a series resonance with an inductance by the first ground coupling bump at a target frequency.

Abstract: In order to prevent a crack from developing in an interlayer insulating film formed under a bonding pad due to impact forces, the bonding pad is formed so that small diameter metal plugs and large diameter metal plugs are arranged between a first metal film and a second metal film as an uppermost layer. Holes are formed in the centers of the larger diameter metal plugs and recessed portions are formed in surface areas of the second metal film above the large diameter metal plugs.

Abstract: Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode. The method includes removing the dummy gate electrode to form a trench bounded by the first and second sidewall spacers. The method removes an upper portion of the first sidewall spacer and deposits a layer of metal in the trench and over a remaining portion of the first sidewall spacer to form a gate electrode and an interconnect.

Abstract: An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included.

Abstract: An embodiment of a semiconductor device includes a gallium nitride (GaN) substrate having a first surface and a second surface. The second surface is substantially opposite the first surface, at least one device layer is coupled to the first surface, and a backside metal is coupled to the second surface. A top metal stack is coupled to the at least one device layer. The top metal stack includes a contact metal coupled to a surface of the at least one device layer, a protection layer coupled to the contact metal, a diffusion barrier coupled to the protection layer, and a pad metal coupled to the diffusion barrier. The semiconductor device is configured to conduct electricity between the top metal stack and the backside metal.

Abstract: A system may include a package defining a cavity and an integrated circuit (IC) disposed within the cavity. The package may include a first electrically conductive package contact and a second electrically conductive package contact. The IC may include a first electrically conductive IC contact and a second electrically conductive IC contact. The system also may include a wire bond extending between and electrically connecting the first electrically conductive package contact and the first electrically conductive IC contact. The system further may include an electrically conductive adhesive extending between and electrically connecting the second electrically conductive package contact and the second electrically conductive IC contact. Use of wire bonds and electrically conductive adhesive may increase an interconnect density between the IC and the package, while not requiring an increase in size of the IC or a decrease in pitch between wire bonds.

Abstract: A semiconductor device includes: a lead frame; a semiconductor element held by the lead frame; a frame body which is formed on the lead frame to surround the semiconductor element, cover a side surface of the lead frame, and expose a bottom surface of the lead frame; and a protective resin filling a region surrounded by the frame body. The lead frame includes an uneven part formed in a section which is part of an upper surface of the lead frame, and is covered with the frame body.

Abstract: A semiconductor device includes a semiconductor chip, a contact pad of the semiconductor chip and a first layer arranged over the contact pad. The first layer includes niobium, tantalum or an alloy including niobium and tantalum.

Abstract: A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer.

Abstract: The present invention relates to a terminal structure and an electronic device having the terminal structure. The terminal structure includes: a terminal having: a conductor layer containing at least one metal selected from gold, silver, and copper; a first layer containing nickel and phosphorus, laid on the conductor layer; a second layer having a smaller atomic ratio of nickel to phosphorus than the first layer and containing Ni3P, laid on the first layer; and a third layer containing a first intermetallic compound of an Ni—Cu—Sn type, laid on the second layer; and a solder layer on the third layer of the terminal. A second intermetallic compound of an Ni—P—Sn type partly covers a surface of the second layer on the third layer side and a maximum thickness of the second intermetallic compound in a lamination direction is from 0.05 to 0.7 ?m.

Abstract: A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled.

Abstract: The present invention relates to a terminal structure. The terminal structure includes: a terminal having: a conductor layer containing at least one metal selected from gold, silver, and copper; a first layer containing nickel and phosphorus, laid on the conductor layer; a second layer having a smaller atomic ratio of nickel to phosphorus than the first layer and containing Ni3P, laid on the first layer; a third layer containing a first intermetallic compound of an Ni—P—Sn type, laid on the second layer; and a fourth layer containing a second intermetallic compound of an Ni—Cu—Sn type, laid on the third layer; and a solder layer on the fourth layer of the terminal. Ra2 is larger than Ra1, where Ra1 is a surface roughness of the third layer on the second layer side and Ra2 is a surface roughness of the third layer on the fourth layer side.

Abstract: A chip structure comprising a substrate, a plurality of wire bonding pads and a plurality of solder pads is provided. Gold bumps or gold pads can be formed on the wire bonding pads while solder bumps can be formed on the solder pads concurrently. Alternatively, both wire bonding pads and solder pads can be formed of the same metal stack.

Abstract: A manufacturing method of a semiconductor device including an electrode having low contact resistivity to a nitride semiconductor is provided. The manufacturing method includes a carbon containing layer forming step of forming a carbon containing layer containing carbon on a nitride semiconductor layer, and a titanium containing layer forming step of forming a titanium containing layer containing titanium on the carbon containing layer. A complete solid solution Ti (C, N) layer of TiN and TiC is formed between the titanium containing layer and the nitride semiconductor layer. As a result, the titanium containing layer comes to be in ohmic contact with the nitride semiconductor layer throughout the border therebetween.

Abstract: A flip chip interconnection system includes: providing a conductive lead coated with a protective coating; forming a groove through the protective coating to the conductive lead for controlling solder position on a portion of the conductive lead; and attaching a flip chip having a solderable conductive interconnect to the portion of the conductive lead.

Abstract: A semiconductor device comprises a GaAs substrate having a first major surface and a second major surface opposite to each other; a first metal layer composed of at least one of Pd, Ta, and Mo on the first major surface of the GaAs substrate; and a second metal layer composed of a Ni alloy or Ni on the first metal layer.

Abstract: A conductive bump formed on an electrode surface of an electronic component. This conductive bump is composed of a plurality of photosensitive resin layers having different conductive filler contents. Consequently, this conductive bump is able to realize conflicting functions, namely, improvement in adhesion strength with the electrode and reduction of contact resistance.

Abstract: Embodiments of a low resistivity contact to a semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a semiconductor layer, a semiconductor contact layer having a low bandgap on a surface of the semiconductor layer, and an electrode on a surface of the semiconductor contact layer opposite the semiconductor layer. The bandgap of the semiconductor contact layer is in a range of and including 0 to 0.2 electron-volts (eV), more preferably in a range of and including 0 to 0.1 eV, even more preferably in a range of and including 0 to 0.05 eV. Preferably, the semiconductor layer is p-type. In one particular embodiment, the semiconductor contact layer and the electrode form an ohmic contact to the p-type semiconductor layer and, as a result of the low bandgap of the semiconductor contact layer, the ohmic contact has a resistivity that is less than 1×10?6 ohms·cm2.

Abstract: Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Abstract: An assembly and method of making same are provided. The assembly can include a first component including a dielectric region having an exposed surface, a conductive pad at the surface defined by a conductive element having at least a portion extending in an oscillating or spiral path along the surface, and a an electrically conductive bonding material joined to the conductive pad and bridging an exposed portion of the dielectric surface between adjacent segments. The conductive pad can permit electrical interconnection of the first component with a second component having a terminal joined to the pad through the electrically conductive bonding material. The path of the conductive element may or may not overlap or cross itself.

Abstract: Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may be a multi junction solar cell. The optoelectronic device may have a bi-layer electrical interconnect that is physically and electrically connected to sidewalls of the array of nanostructures. The optoelectronic device may be operated as a multi junction solar cell, wherein each junction is associated with one portion of the device. The bi-layer electrical interconnect allows current to pass from one portion to the next. Thus, the bi-layer electrical interconnect may serve as a replacement for a tunnel junction, which is used in some conventional multi junction solar cells.

Abstract: A semiconductor chip structure includes a semiconductor substrate, an circuit structure, a passivation layer, a first adhesion/barrier layer, a metal cap and a metal layer. The semiconductor substrate has multiple electric devices located on a surface layer of a surface of the substrate. The circuit structure had multiple circuit layers electrically connecting with each other and electrically connecting with the electric devices. One of the circuit layers has multiple pads. The passivation layer is located on the circuit structure and has multiple openings penetrating through the passivation layer. The openings expose the pads. The first adhesion/barrier layer is over the pads and the passivation layer. The metal cap is located on the first adhesion/barrier layer and the passivation layer. The metal layer is on the metal layer.

Abstract: A joint structure joins an electronic element 12 included in an electronic component to an electrode 14 included in that electronic component. The joint structure includes a solder layer, which contains 0.2 to 6% by weight of copper, 0.02 to 0.2% by weight of germanium and 93.8 to 99.78% by weight of bismuth, a nickel layer provided between the solder layer and the electrode, and a barrier layer provided between the nickel layer and the solder layer. Here, the barrier layer is formed so as to have an average thickness of from 0.5 to 4.5 ?m after the electronic element and the electrode are joined by the solder layer.

Abstract: A fine pitch solder bump structure with a built-in stress buffer that is utilized in electronic packages, and a method of producing the fine pitch solder bump structure with built-in stress buffer. Employed is a very thick final passivation layer that is constituted of a polyimide as a so-called “cushion” for a minimal thickness of UBM (BLM) pad and solder material, while concurrently completely separating the resultingly produced polyimide islands, so that the polyimide material provides most of the physical height for the “standoff” of a modified C4 (controlled collapse chip connection) structure.

Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.

Abstract: A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.

Abstract: A semiconductor device includes: a semiconductor structure unit; an interconnect layer provided on the major surface side of the semiconductor structure unit; an electrode pad provided on a surface of the interconnect layer on a side opposite to a surface on which the semiconductor structure unit is provided, and the electrode pad electrically connected to the interconnect layer; a plurality of metal pillars joined to the electrode pad separately from each other; and an external terminal provided commonly at tips of the plurality of metal pillars, the metal pillars having an area in a plan view smaller than an area in a plan view of the external terminal.

Abstract: An electronic component includes a metal substrate, a semiconductor chip configured to be attached to the metal substrate, and a buffer layer positioned between the metal substrate and the semiconductor chip configured to mechanically decouple the semiconductor chip and the metal substrate. The buffer layer extends across less than an entire bottom surface of the semiconductor chip.

Abstract: A pad in a semiconductor device and fabricating method thereof are disclosed. The pad includes an uppermost metal layer first to Nth intermediate metal layers, wherein capacitors configured or formed by the uppermost metal layer and the first to Nth intermediate metal layers are serially connected. Accordingly, the pad reduces total parasitic capacitance components by connecting MIM type capacitors in series, and not necessarily overlapping with each other, thereby minimizing design errors attributed to the pad by reducing parasitic factors generated from the integrated circuit design. The pad may also minimize capacitance attributed to resonance at a specific frequency. Moreover, the pad avoids affecting an adjacent pad or circuit without additional processing, despite maintaining the above-mentioned effects, thereby reducing cost.

Abstract: A semiconductor chip, having IC pads, the semiconductor chip having a device, electrically connected to at least one electrical contact through the IC pad, the electrical contact having a height and a cross sectional profile, through the height, configured to facilitate penetration of at least a portion of the electrical contact into a malleable contact on a second semiconductor chip.

Abstract: A first semiconductor chip and a second semiconductor chip which form a stack are mounted on a module substrate by deflecting a center position of the semiconductor chips from the module substrate. In the side where the distance from the edge of the deflected semiconductor chip to the edge of a module substrate is shorter, the electrode pad on the first semiconductor chip and the electrode pad on the second semiconductor chip are directly connected with a wire. In the side where the distance from the edge of the deflected semiconductor chip to the edge of a module substrate is longer, the electrode pad on the first semiconductor chip and the electrode pad on the second semiconductor chip are combined with the corresponding bonding lead on the module substrate with a wire.

Abstract: Device comprising an ohmic via contact, and method of fabricating thereof. A preferred embodiment comprises forming a metal layer over a substrate, forming a conductive barrier layer over the metal layer, depositing an insulating layer over the conductive barrier layer, creating an opening in the insulating layer to expose the conductive barrier layer, and forming a via contact in the opening. The conductive barrier layer protects the metal layer by preventing the formation of an oxide layer, which could reduce conductivity.

Abstract: Embodiments of the present invention include a conductive particle that includes a conductive nickel/gold (Ni/Au) complex metal layer having a phosphorous content of less than about 1.5 weight percent formed on the surface of a polymer resin particle. Methods of forming the same are also included. A conductive particle with a Ni/Au complex metal layer having less than about 1.5 weight percent of phosphorous may have relatively high conductivity while providing relatively good adhesion of the Ni/Au metal layer to the polymer resin particle. Further embodiments of the present invention provide an anisotropic adhesive composition comprising a conductive particle according to an embodiment of the invention.

Abstract: The module is of the type comprising an electronic component provided with a conductive face that is electrically connected to a connection member of the component by means of a conductor that is corrugated at least in part so as to define an alternating sequence of oppositely-directed arcs, a first series of arcs being connected to the conductive face of the electronic component. The conductor also includes a second series of arcs opposite to the arcs of the first series and interposed between the arcs of the first series, the second series of arcs being connected to the conductive face of the connection member.

Abstract: A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that includes a plurality of address pads and respective supply pins. The method includes: realizing at least one configuration terminal having a first and a second portion structurally independent and connected to at least one contact terminal; providing the contact of such first and second portions with respective terminals; and configuring the device by a short-circuiting of the contact terminal with at least one of said terminals.

Abstract: An electronic assembly comprising a first substrate, a number of bonds on the first substrate, a second substrate spaced apart from the first substrate, a number of bumps on the second substrate, each of the bumps including an insulating body and a conductive portion, the conductive portion extending from a top surface of the insulating body via at least one sidewall of the insulating body toward the second substrate, and an adhesive between the first substrate and the second substrate, the adhesive including an insulating layer and a conductive layer, the insulating layer and the conductive layer being laminated with respect to each other, wherein the insulating layer is positioned closer to the first substrate than the conductive layer.

Abstract: An alternating current (AC) light emitting device is revealed. The AC light emitting device includes a substrate and a plurality of light emitting units arranged on the substrate. The light emitting unit consists of a first semiconductor layer, a light emitting layer, a second semiconductor layer, at least one electrode and at least one second electrode respectively arranged on the first semiconductor layer and the second semiconductor layer from bottom to top. The plurality of light emitting units is coupled to at least one adjacent light emitting unit by a plurality of conductors. By the plurality of conductors that connect light emitting units with at least one adjacent light emitting unit, an open circuit will not occur in the AC light emitting device once one of the conductors is broken.

Abstract: A resin coated copper foil is used to fabricate a multilayer Chip Scale Package (CSP). A CSP package base has a first electrical routing layer. A resin coated copper foil is hot pressed onto the CSP package base and then patterned to form a second electrical routing layer. Conductive vias are then formed between the electrical routing layers. An Organic Solder Preservative (OSP) is used a surface finish for solder balls of the CSP.

Abstract: A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across the pad area. The alloy layer contains copper/tin alloys, which include Cu6Sn5 intermetallic compound, and nickel/copper/tin alloys, which include (Ni,Cu)6Sn5 intermetallic compound. A solder element (308) including tin is metallurgically attached to the alloy layer across the pad area. No fraction of the original thin nickel layer is left after the reflow process. Copper/tin alloys help to improve the drop test performance, nickel/copper/tin alloys help to improve the life test performance.