With Thermal Expansion Matching Of Contact Or Lead Material To Semiconductor Active Device Patents (Class 257/747)
-
Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
Patent number: 11251154Abstract: A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die.Type: GrantFiled: May 19, 2020Date of Patent: February 15, 2022Assignee: STATS ChipPAC Pte. Ltd.Inventor: Rajendra D. Pendse -
Patent number: 11031255Abstract: A method for forming a conductive structure is disclosed, the method comprising the steps of: forming a metallic frame having a plurality of metal parts separated from each other; forming an insulating layer on the top surface of the plurality of metal parts; and forming a conductive pattern layer on the insulating layer for making electrical connections with at least one portion of the plurality of metal parts.Type: GrantFiled: February 4, 2020Date of Patent: June 8, 2021Assignee: CYNTEC CO., LTD.Inventors: Bau-Ru Lu, Da-Jung Chen, Yi-Cheng Lin
-
Patent number: 10991649Abstract: A semiconductor device includes a first substrate, a pad array, a conductive bump, a first via and a dielectric. The pad array, formed on a surface of the first substrate, includes a first type pad and a second type pad at a same level. The conductive bump connects one of the first type pad of the second type pad to a second substrate. The first via, connected to a conductive feature at a different level to the first type pad, is located within a projection area of the first type pad and directly contacts the first type pad. The second type pad is laterally connected with a conductive trace on the same level. The conductive trace is connected to a second via at a same level with the first via. The dielectric in the first substrate contacts the second type pad. The second type pad is floated on the dielectric.Type: GrantFiled: December 17, 2019Date of Patent: April 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tsung-Yuan Yu, Hao-Yi Tsai, Chao-Wen Shih, Hung-Yi Kuo, Pi-Lan Chang
-
Patent number: 10593631Abstract: Techniques for reducing stress in an integrated circuit wafer are disclosed. A silicon substrate may include multiple integrated circuit chips and multiple scribe regions situated between the one of the multiple integrated circuit chips. A particular scribe region includes a plurality of layers and a stress reduction structure that includes, at a particular layer of the plurality of layers, a material whose coefficient of thermal expansion of materials is greater than a coefficient of thermal expansion of the silicon wafer.Type: GrantFiled: April 4, 2018Date of Patent: March 17, 2020Assignee: Oracle International CorporationInventor: Jeewika Ranaweera
-
Patent number: 10510652Abstract: A method of manufacturing a semiconductor device includes: receiving a first substrate with a surface; receiving a second substrate; determining a pad array on the surface of the first substrate, wherein the pad array includes a first type pad and a second type pad; forming a via pattern underlying the pad array in the first substrate according to the location of each via, wherein the first type pad in the pad array is directly contacting a via of the via pattern and the second type pad in the pad array is clear of any via of the via pattern; laterally connecting the second type pad with a conductive trace, wherein the conductive trace connects to another via that is same level with the via contacting the first type pad; and disposing a first conductive bump and a second conductive bump between the first substrate and the second substrate.Type: GrantFiled: August 15, 2016Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tsung-Yuan Yu, Hao-Yi Tsai, Chao-Wen Shih, Hung-Yi Kuo, Pi-Lan Chang
-
Patent number: 10090261Abstract: A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment, the debug access ports may be formed within an encapsulation material proximate the microelectronic package side. In another embodiment, the debug access ports may be formed in a microelectronic interposer of the microelectronic package proximate the microelectronic package side. In a further embodiment, the debug access ports may be formed at the microelectronic package bottom and may include a solder contact.Type: GrantFiled: March 28, 2017Date of Patent: October 2, 2018Assignee: Intel CorporationInventors: Florence R. Pon, Bilal Khalaf, Saeed S. Shojaie
-
Patent number: 10091874Abstract: The invention relates to a circuit board (1a, 1b, 1c), particularly for a power-electronic module (2), comprising an electrically-conductive substrate (3) which consists, at least partially and preferably entirely, of aluminum and/or an aluminum alloy. On at least one surface (3a, 3b) of the electrically-conductive substrate (3), at least one conductor surface (4a, 4b) is arranged in the form of an electrically-conductive layer applied preferably using a printing method and more preferably using a screen-printing method, said conductor surface (4a, 4b) being in direct electrical contact with the electrically-conductive substrate (3).Type: GrantFiled: January 26, 2017Date of Patent: October 2, 2018Assignee: AB Mikroelektronik Gesellschaft mit beschraenkter HaftungInventors: Robert Christopher Burns, Wolfgang Tusler, Bernd Haegele
-
Patent number: 9922917Abstract: The present disclosure relates to a semiconductor package. In an embodiment, the semiconductor package includes a substrate having a lateral surface and an upper surface, a semiconductor device mounted to the substrate, and a molding compound covering the lateral surface and the upper surface of the substrate and at least a portion of the semiconductor device. A surface of the semiconductor device is substantially coplanar with a surface of the molding compound.Type: GrantFiled: August 29, 2016Date of Patent: March 20, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Hsien Yu, Wen Tsung Hsu, Chun Yuan Tsai
-
Patent number: 9922875Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.Type: GrantFiled: July 18, 2017Date of Patent: March 20, 2018Assignee: Micron Technology, Inc.Inventors: Hongqi Li, Anurag Jindal, Jin Lu, Shyam Ramalingam
-
Patent number: 9887149Abstract: A cavity package is provided. The package can include a metal leadframe and a substrate attached to an interposer formed as part of the leadframe. The substrate typically has a coefficient of thermal expansion matched to the coefficient of thermal expansion of a semiconductor device to be affixed to the substrate. The semiconductor device is typically attached to an exposed top surface of the substrate. The cavity package also includes a plastic portion molded to the leadframe forming a substrate cavity. The substrate cavity allows access to the exposed top surface of the substrate for affixing the semiconductor device. The cavity package also include a connective element for grounding a lid through an electrical path from the lid to the interposer.Type: GrantFiled: January 31, 2017Date of Patent: February 6, 2018Assignee: Ubotic Company LimitedInventor: Chun Ho Fan
-
Patent number: 9837342Abstract: A multilayer wiring board includes a main wiring board which mounts a semiconductor component on a surface of the main wiring board, and a wiring structure body which is mounted to the main wiring board and is formed to be electrically connected to the semiconductor component. The wiring structure body includes conductive pads formed on a first side of the wiring structure body, a heat radiation component formed on a second side of the wiring structure body on the opposite side with respect to the first side, an insulation layer positioned between the conductive pads and the heat radiation component, and via conductors formed in the insulation layer such that each of the via conductors has a diameter which increases from the first side toward the second side of the wiring structure body.Type: GrantFiled: July 27, 2015Date of Patent: December 5, 2017Assignee: IBIDEN CO., LTD.Inventor: Hajime Sakamoto
-
Patent number: 9800015Abstract: This disclosure relates generally to an electronic package that can include a die and a dielectric layer at least partially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the dielectric layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic package different from the first major surface.Type: GrantFiled: February 29, 2016Date of Patent: October 24, 2017Assignee: Intel CorporationInventors: Feras Eid, Johanna Swan, Weng Hong Teh
-
Patent number: 9790369Abstract: Provided is a complex material that includes a first metal deposition layer, a first thermosetting resin layer positioned on one side of the first metal deposition layer, and a second thermosetting resin layer positioned on the other side of the first metal deposition layer.Type: GrantFiled: May 2, 2013Date of Patent: October 17, 2017Assignee: Lotte Advanced Materials Co., Ltd.Inventors: Young-Sin Kim, Kang-Yeol Park, Young-Chul Kwon, Seon-Ae Lee, Min-Young Lim
-
Patent number: 9648736Abstract: The invention relates to a circuit board, particularly for a power-electronic module, comprising an electrically-conductive substrate which consists, at least partially and preferably entirely, of aluminium and/or an aluminium alloy. On at least one surface of the electrically-conductive substrate, at least one conductor surface is arranged in the form of an electrically-conductive layer applied preferably using a printing method and more preferably using a screen-printing method, said conductor surface being in direct electrical contact with the electrically-conductive substrate.Type: GrantFiled: October 30, 2014Date of Patent: May 9, 2017Assignee: A.B. MIKROELEKTRONIK GESELLSCHAFT MIT BESCHRAENKTER HAFTUNGInventors: Robert Christopher Burns, Wolfgang Tusler, Bernd Haegele
-
Patent number: 9553058Abstract: A method of forming a network of RDL lines on the backside of a thinned TSV die to control warpage and the resulting device are provided. Embodiments include providing a thinned TSV die of a 3D IC stack, the thinned TSV die having a front side and a back side; forming a plurality of RDL lines across the backside of the die; and forming a plurality of UBM structures across the backside of the die.Type: GrantFiled: September 15, 2015Date of Patent: January 24, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Luke England, Rahul Agarwal
-
Patent number: 9460993Abstract: An interposer comprising an array of top contacts on the top surface configured to interface with an integrated circuit package, a corresponding array of bottom contacts on the bottom surface configured to interface with a component beneath the interposer, through connections between corresponding top and bottom contacts and a plurality of signal probe points on the edge surface. The interposer may include an electrical pathway connecting a first through connection to a first signal probe point. The electrical pathway may contact the first through connection at a first intersection. A resistor may be disposed along the electrical pathway, between the first intersection and the first signal probe point. The electrical pathway from the first intersection to the resistor may be an unconditioned signal pathway. The electrical pathway from the resistor to the first signal contact may be a conditioned signal pathway. The unconditioned signal pathway may have a length of not greater than 0.20 inch.Type: GrantFiled: February 22, 2016Date of Patent: October 4, 2016Inventors: Robert C. Shelsky, Kenneth W. Graham, Dennis D. Everson
-
Patent number: 9356008Abstract: A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.Type: GrantFiled: February 6, 2015Date of Patent: May 31, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Cheng-Chia Chiang, Hsin-Ta Lin, Fu-Tang Huang, Yu-Po Wang, Lung-Yuan Wang, Chu-Chi Hsu, Chia-Kai Shih
-
Patent number: 9223363Abstract: Provided herein are electronic devices assembled with a heat absorbing and/or thermally insulating composition.Type: GrantFiled: March 16, 2013Date of Patent: December 29, 2015Assignee: Henkel IP & Holding GmbHInventors: My N. Nguyen, Jason Brandi, Emilie Barriau
-
Patent number: 9099442Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.Type: GrantFiled: August 5, 2013Date of Patent: August 4, 2015Assignee: Micron Technology, Inc.Inventors: Hongqi Li, Anurag Jindal, Jin Lu, Shyam Ramalingam
-
Patent number: 8952530Abstract: A device includes a metal pad, a passivation layer overlapping edge portions of the metal pad, and a first polymer layer over the passivation layer. A Post-Passivation-Interconnect (PPI) has a level portion overlying the first polymer layer, and a plug portion that has a top connected to the level portion. The plug portion extends into the first polymer layer. A bottom surface of the plug portion is in contact with a dielectric material. A second polymer layer is overlying the first polymer layer.Type: GrantFiled: September 14, 2012Date of Patent: February 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Ying-Ju Chen
-
Publication number: 20150035150Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.Type: ApplicationFiled: August 5, 2013Publication date: February 5, 2015Applicant: MICRON TECHNOLOGY, INC.Inventors: Hongqi Li, Anurag Jindal, Jin Lu, Shyam Ramalingam
-
Patent number: 8946871Abstract: An integrated circuit package comprising an active semiconductor device layer and at least one heat-transfer semiconductor layer on the active semiconductor device layer. The heat-transfer semiconductor layer has a coefficient of thermal expansion that substantially matches a coefficient of thermal expansion of the active semiconductor device layer.Type: GrantFiled: November 7, 2012Date of Patent: February 3, 2015Assignee: LSI CorporationInventors: Zeki Z. Celik, Allen S. Lim, Atila Mertol
-
Patent number: 8946894Abstract: Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed.Type: GrantFiled: February 18, 2013Date of Patent: February 3, 2015Assignee: TriQuint Semiconductor, Inc.Inventors: Tarak A. Railkar, Deep C. Dumka
-
Patent number: 8896106Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads.Type: GrantFiled: July 9, 2012Date of Patent: November 25, 2014Assignee: Infineon Technologies AGInventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Klaus Schiess
-
Patent number: 8890304Abstract: A microelectronic package includes a microelectronic unit and a substrate. The microelectronic unit includes a microelectronic element having contacts on a front face. A dielectric material has a first surface substantially flush with the front face of the microelectronic element. Conductive traces have at least portions extending along the front face away from the contacts, at least some of which also extend along the first surface of the dielectric material. Contacts are connected with the traces, at least some of which are disposed at the first surface of the dielectric material. The substrate has first and second opposed surfaces and an edge extending therebetween, the first surface facing the front face of the microelectronic unit, and the second surface having a plurality of terminals thereon configured for electrical connection with at least one external component. Masses of conductive matrix material join the terminals with the redistribution contacts.Type: GrantFiled: June 8, 2011Date of Patent: November 18, 2014Assignee: Tessera, Inc.Inventors: Hiroaki Sato, Kiyoaki Hashimoto, Yoshikuni Nakadaira, Norihito Masuda, Belgacem Haba, Ilyas Mohammed, Philip Damberg
-
Patent number: 8796866Abstract: Thermally-induced stress on a silicon micro-electromechanical pressure transducer (MEMS sensor) is reduced by attaching the MEMS sensor to a plastic filled with low CTE fillers that lowers the plastic's coefficient of thermal expansion (CTE) to be closer to that of silicon. The MEMS sensor is attached to the housing using an epoxy adhesive/silica filler mixture, which when cured has a CTE between about ten PPM/° C. and about thirty PPM/° C. in order to match the housing CTE. The adhesive also has a glass transition temperature (Tg) above the operating temperature range. This design provides good sealing of the sensor and stable sensor outputs.Type: GrantFiled: October 16, 2012Date of Patent: August 5, 2014Assignee: Continential Automotive Systems, Inc.Inventor: Joe Pin Wang
-
Patent number: 8704347Abstract: A chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a packaging layer formed over the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer and a ball grid array formed over a surface of the packaging layer and being electrically connected to the device.Type: GrantFiled: August 16, 2010Date of Patent: April 22, 2014Assignee: Tessera, Inc.Inventors: Andrey Grinman, David Ovrutsky, Charles Rosenstein, Belgacem Haba, Vage Oganesian
-
Patent number: 8492203Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.Type: GrantFiled: June 20, 2011Date of Patent: July 23, 2013Assignee: STATS ChipPAC, Ltd.Inventors: Yaojian Lin, Kang Chen, Yu Gu, Wei Meng, Chee Siang Ong
-
Patent number: 8373275Abstract: A fine pitch solder bump structure with a built-in stress buffer that is utilized in electronic packages, and a method of producing the fine pitch solder bump structure with built-in stress buffer. Employed is a very thick final passivation layer that is constituted of a polyimide as a so-called “cushion” for a minimal thickness of UBM (BLM) pad and solder material, while concurrently completely separating the resultingly produced polyimide islands, so that the polyimide material provides most of the physical height for the “standoff” of a modified C4 (controlled collapse chip connection) structure.Type: GrantFiled: January 29, 2008Date of Patent: February 12, 2013Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
-
Patent number: 8283756Abstract: An electronic component includes a metal substrate, a semiconductor chip configured to be attached to the metal substrate, and a buffer layer positioned between the metal substrate and the semiconductor chip configured to mechanically decouple the semiconductor chip and the metal substrate. The buffer layer extends across less than an entire bottom surface of the semiconductor chip.Type: GrantFiled: August 20, 2007Date of Patent: October 9, 2012Assignee: Infineon Technologies AGInventors: Ivan Galesic, Joachim Mahler, Alexander Heinrich, Khalil Hosseini
-
Patent number: 8222737Abstract: A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.Type: GrantFiled: July 29, 2010Date of Patent: July 17, 2012Assignee: Elpida Memory, Inc.Inventors: Yuji Watanabe, Hisashi Tanie, Koji Hosokawa, Mitsuaki Katagiri, Ichiro Anjo
-
Patent number: 8183681Abstract: A semiconductor device which includes a semiconductor chip; an electrically conductive base electrode bonded to the lower surface of the chip by a first bonding member; an electrically conductive lead electrode bonded to the upper surface of the chip by a second bonding member; and a first stress relief member for reducing stress developed in the first bonding member due to the difference in thermal expansion between the chip and the base electrode. Both the base electrode and the first stress relief member are in direct contact with the lower surface of the first bonding member. A protrusion is formed upstanding from the base electrode in direct contact with the first bonding member, and the first stress relief member surrounds a circumferential portion of the protrusion.Type: GrantFiled: June 29, 2009Date of Patent: May 22, 2012Assignee: Hitachi, Ltd.Inventors: Shinji Hiramitsu, Hiroyuki Ohta, Koji Sasaki, Masato Nakamura, Osamu Ikeda, Satoshi Matsuyoshi
-
Patent number: 8164186Abstract: A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.Type: GrantFiled: April 14, 2005Date of Patent: April 24, 2012Assignee: Elpida Memory, Inc.Inventors: Yuji Watanabe, Hisashi Tanie, Koji Hosokawa, Mitsuaki Katagiri, Ichiro Anjo
-
Patent number: 8154122Abstract: A semiconductor package and a method of manufacturing the semiconductor package are provided. A semiconductor package according to the present general inventive concept may include a base substrate having one surface on which a connection terminal is formed and a first package substrate having a molding layer covering the base substrate. The molding layer faces a circumference of the connection terminal and includes a side surface having first and second surfaces having a circumference of a different size, respectively.Type: GrantFiled: May 20, 2009Date of Patent: April 10, 2012Assignee: Samsung Electronics Co., LtdInventors: Chul-Yong Jang, Pyoung-Wan Kim, Teak-Hoon Lee
-
Patent number: 8089150Abstract: A structurally robust power switching assembly, comprising a first rigid structural unit that defines a first unit major surface that is patterned to define a plurality of mutually electrically isolated, electrically conductive paths. Also, a similar, second rigid structural unit is spaced apart from the first unit major surface. Finally, a transistor is interposed between and electrically connected to the first unit major surface and the second unit major surface.Type: GrantFiled: November 14, 2007Date of Patent: January 3, 2012Inventors: Lawrence E. Rinehart, Guillermo L. Romero
-
Patent number: 8072084Abstract: An integrated circuit, a circuit system and method of manufacturing such is disclosed. One embodiment provides a circuit chip including a first contact field on a chip surface; and an insulating layer on the chip surface. The insulating layer includes a flexible material. A contact pillar is coupled to the first contact field and extends from the chip surface through the insulating layer. The contact pillar includes a conductive material.Type: GrantFiled: September 14, 2007Date of Patent: December 6, 2011Assignee: Qimonda AGInventors: Roland Irsigler, Harry Hedler, Stephan Dobritz
-
Patent number: 8063393Abstract: An exemplary hollow stylus-shaped structure is disclosed, including a hollow column spacer formed over a base layer and a hollow cone spacer stacked over the hollow column spacer, wherein the hollow cone spacer, the hollow column spacer, and the base layer form a space, and sidewalls of the hollow cone spacer and the hollow column spacer are made of silicon-containing organic or inorganic materials.Type: GrantFiled: September 5, 2008Date of Patent: November 22, 2011Assignee: Industrial Technology Research InstituteInventor: Wei-Su Chen
-
Patent number: 8044504Abstract: A semiconductor device, includes: an organic multilayer wiring substrate having an inner conductive layer; a semiconductor element mounted and connected on one surface of the wiring substrate; and a plurality of solder balls disposed on the other surface in a grid array. A defect portion is formed at an area corresponding to a corner solder ball disposed at an outer peripheral corner, or at an area corresponding to the corner solder ball and peripheral solder balls at the inner conductive layer. Temperature rises of the solder balls disposed in a vicinity of the corner are suppressed, and therefore, the semiconductor device of which fatigue life is prolonged and superior in reliability can be obtained.Type: GrantFiled: September 3, 2009Date of Patent: October 25, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Tooru Suda
-
Patent number: 8035202Abstract: A semiconductor chip of the present invention has a wiring substrate and a chip part. The wiring substrate has an insulating resin layer having a first major surface and a second major surface, and a first wiring layer disposed on the insulating resin layer on the second major surface side. The chip part has a projection electrode on the bottom surface. The insulating resin layer holds the chip part such that the bottom and side surfaces of the chip part are in contact with the insulating resin layer, and the top surface of the chip part is exposed on the insulating layer on the first major surface side. The projection electrode of the chip part is connected with the first wiring layer.Type: GrantFiled: July 6, 2009Date of Patent: October 11, 2011Assignee: NEC CorporationInventors: Shinji Watanabe, Yukio Yamaguchi
-
Patent number: 8035127Abstract: A packaging substrate structure with a semiconductor chip embedded therein is disclosed, including a carrier board having a first and an opposed second surfaces and disposed with at least a through cavity; a semiconductor chip received in the through cavity, the chip having an active surface and an inactive surface opposite to one another, wherein the active surface has a plurality of electrode pads, a passivation layer is disposed on the active surface with the electrode pads exposed from the passivation layer, and metal pads are disposed on surfaces of the electrode pads; a buffer layer disposed on the first surface of the carrier board and on surfaces of the passivation layer and the metal pads; a first dielectric layer disposed on the buffer layer; and a first circuit layer disposed on the first dielectric layer and electrically connected with the metal pads of the chip via first conductive structures disposed in the buffer layer and the first dielectric layer, wherein the CTE (Coefficient of Thermal ExpaType: GrantFiled: March 26, 2008Date of Patent: October 11, 2011Assignee: Unimicron Technology Corp.Inventors: Kan-Jung Chia, Shang-Wei Chen
-
Patent number: 8004001Abstract: A semiconductor device for light emission having a plurality of epitaxial layers with an n-type layer for light emission and a p-type layer for light reflection. The p-type layer has at least one seed layer for an outer layer of a conductive metal. The at least at least one seed layer is a material for providing a buffer for differential thermal expansion of the outer layer and the light reflecting layer.Type: GrantFiled: September 1, 2006Date of Patent: August 23, 2011Assignee: Tinggi Technologies Private LimitedInventors: Shu Yuan, Xuejun Kang, Daike Wu
-
Patent number: 7986214Abstract: An electrical assembly includes at least two PTC-resistor elements, each of which has a base body having a flat shape. Each base body has main surfaces that contain electrodes. A carrier plate has spacers for positioning base bodies of the at least two PTC resistor elements. A width each spacer is about equal, in at least one area, to a distance between facing electrodes of adjacent PTC-resistor elements.Type: GrantFiled: November 8, 2007Date of Patent: July 26, 2011Assignee: EPCOS AGInventor: Werner Kahr
-
Patent number: 7888800Abstract: A semiconductor structure including a first rigid dielectric layer and a second rigid dielectric layer. A first non-rigid low-k dielectric layer is formed between the first and second rigid dielectric layer. A plurality of dummy fill shapes is formed in the first non-rigid layer which replace portions of the first non-rigid low-k dielectric layer with lower coefficient of thermal expansion (CTE) metal such that an overall CTE of the first non-rigid low-k dielectric layer and the plurality of dummy fill shapes matches a CTE of the first and second rigid dielectric layers more closely than that of the first non-rigid low-k dielectric layer alone.Type: GrantFiled: October 22, 2008Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventor: Howard S. Landis
-
Patent number: 7791199Abstract: A chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a packaging layer formed over the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer and a ball grid array formed over a surface of the packaging layer and being electrically connected to the device.Type: GrantFiled: November 22, 2006Date of Patent: September 7, 2010Assignee: Tessera, Inc.Inventors: Andrey Grinman, David Ovrutsky, Charles Rosenstein, Belgacem Haba, Vage Oganesian
-
Patent number: 7696617Abstract: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.Type: GrantFiled: August 28, 2007Date of Patent: April 13, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kazuhiko Ooi, Tadashi Kodaira, Eisaku Watari, Jyunichi Nakamura, Shunichiro Matsumoto
-
Patent number: 7692299Abstract: A semiconductor apparatus having improved thermal fatigue life is provided by lowering maximum temperature on jointing members and reducing temperature change. A jointing member is placed between a semiconductor chip and a lead electrode, and a thermal stress relaxation body is arranged between the chip and a support electrode. Jointing members are placed between the thermal stress relaxation body and the chip and between the thermal stress relaxation body and the support electrode. A second thermal stress relaxation body made from a material having a thermal expansion coefficient between the coefficients of the chip and the lead electrode is located between the chip and the lead electrode. The first thermal stress relaxation body is made from a material which has a thermal expansion coefficient in between the coefficients of the chip and the support electrode, and has a thermal conductivity of 50 to 300 W/(m·° C.).Type: GrantFiled: August 7, 2007Date of Patent: April 6, 2010Assignees: Hitachi Haramachi Electronics Co., Ltd., Hitachi, Ltd.Inventors: Chikara Nakajima, Takeshi Kurosawa, Megumi Mizuno
-
Patent number: 7585693Abstract: Method of forming a microelectronic package using control of die and substrate differential expansions. The method includes: providing a die-substrate combination including a substrate, a die disposed on the substrate, and plurality of solder paste disposed between the die and the substrate; reflowing the solder paste by exposing the die-substrate combination to temperatures changes including heating the die-substrate combination to liquefy the solder paste, and cooling down the die-substrate combination until the solder paste has solidified to form solder joints to yield the package; and controlling an expansion of the die and the substrate at least during cooling down to mitigate a relative difference in volumetric strain between the die and the substrate. Controlling may comprise exposing the die-substrate combination to pressure changes at least during cooling down.Type: GrantFiled: March 31, 2006Date of Patent: September 8, 2009Assignee: Intel CorporationInventors: Kristopher J. Frutschy, Sudarshan V. Rangaraj, Kevin B. George
-
Publication number: 20090218690Abstract: A feature is inscribed in a major surface of a microelectronic workpiece having a material property expressed as a reference coefficient value. The feature includes a first material having a first coefficient value for the material property and a second material having a second coefficient value for the material property. The first coefficient value is different from the reference coefficient value different from the first coefficient value and the second coefficient value is different from the first coefficient value. The first and second materials behave as an aggregate having an aggregate coefficient value for the material property between the first coefficient value and the reference coefficient value.Type: ApplicationFiled: February 28, 2008Publication date: September 3, 2009Inventors: Harry Hedler, Roland Irsigler, Rolf Weis, Detlef Weber
-
Patent number: 7550845Abstract: In a ball grid array (BGA) package, a first stiffener is attached to a surface of a substrate. A second stiffener is attached to the surface of the substrate to be co-planar with the first stiffener. The second stiffener is separated from the first stiffener by a channel therebetween. An integrated circuit (IC) die is mounted to a surface of the second stiffener.Type: GrantFiled: October 31, 2002Date of Patent: June 23, 2009Assignee: Broadcom CorporationInventors: Sam Ziqun Zhao, Reza-ur Rahman Khan
-
Patent number: 7538432Abstract: A flip chip assembly having reduced stress and warpage comprises a flip chip package including an organic substrate and an integrated circuit chip, a temporary structure having a coefficient of thermal expansion that is substantially similar to a coefficient of thermal expansion of the integrated circuit chip, and a cap member coupled to a top side of the organic substrate. A bottom side of the integrated circuit chip is bonded to the top side of the organic substrate with controlled chip collapse columns. Additionally, a bottom side of the organic substrate is soldered to a top side of the temporary structure with solder interconnections that are applied to a plurality of solder pads on the top side of the temporary structure, the position of the solder pads on the temporary structure mirroring the position of a plurality of solder pads on the bottom side of the organic substrate.Type: GrantFiled: September 18, 2008Date of Patent: May 26, 2009Assignee: International Business Machines CorporationInventors: David Danovitch, Julien Sylvestre