Abstract: To enable freely choose a bus-line to be monitored without such a problem that the bus-line is made corroded. A liquid crystal display device comprising: a substrate (10) in which a display area (10d) is delimited; and two series of bus-lines (4, 5) supported by the substrate, one ends of the bus-lines being located in proximity to one side of the display area, another ends of the bus-lines being located in proximity to another side of the display area which is opposite to the one side of the display area, the two series of bus-lines (4, 5) being arranged to extend over the display area in such a manner that the one series of bus-lines (4) is orthogonal to the other series of bus-lines (5).

Abstract: An object of this invention is to provide an electrode for p-type SiC which can provide improved surface morphology and less thermal damage for a semiconductor crystal layer due to formation of an electrode. In this invention, a p-type electrode is manufactured to contain at least one selected from the group consisting of nickel (Ni), cobalt (Co), palladium (Pd) and platinum (Pt).

Abstract: Microelectronic packages include a first microelectronic substrate having a first face and a first AC-coupled interconnect element on the first face. A second microelectronic substrate includes a second face and a second AC-coupled interconnect element on the second face. A buried solder bump extends between the first and second faces, and is at least partially buried beneath the first and/or second faces, to maintain the first and second AC-coupled interconnect elements in closely spaced apart relation. The buried solder bump also may couple DC power between the first and second substrates. Other technologies also may be used to maintain the AC-coupled interconnect elements in closely spaced apart relation and to couple DC power between the substrates. The first and second AC-coupled interconnect elements may be first and second capacitor plates, first and second inductors and/or first and second combined inductive and capacitive elements.

Abstract: An electrode structure on a p-type III group nitride semiconductor layer includes first, second and third electrode layers successively stacked on the semiconductor layer. The first electrode layer includes at least one selected from a first metal group of Ti, Hf, Zr, V, Nb, Ta, Cr, W and Sc. The second electrode layer includes at least one selected from a second metal group of Ni, Pd and Co. The third electrode layer includes Au.

Abstract: To improve the radiation property without inhibiting miniaturization of the device, heat generated at a heat generating layer (5) is radiated to a substrate (1) via plugs (7, 17), wiring layers (8, 18), and plugs (9, 19). A cross sectional along the principal plane of the substrate (1) of the plugs (7, 9, 17, 19) is set to be a rectangle, and the long sides of the rectangle are parallel to the direction perpendicular to the direction connecting one end and the other end of the heat generating layer (5). Between the plugs (9, 19) and the semiconductor layer (2) is interposed n-type semiconductor layers (3, 13).

Abstract: The present invention relates to a high frequency module board device having a high frequency transmitting and receiving circuit for modulating and demodulating a high frequency signal. The high frequency module board device comprises a base board (2) whose main surface is formed as a build-up surface (2a) and a high frequency circuit part (3) formed on the build-up surface of the base board (2) and having passive elements formed. The base board (2) has an area (29) in which wiring is not formed in a lower layer from a fourth wiring layer (8b). The high frequency circuit part (3) has an upper electrode part (36) and a lower electrode part (35) in positions corresponding to the area (29) in which the wiring is not formed. Thus, since a capacitance (18) is provided just above the area (29) in which the wiring is not formed, a parasitic capacity that the capacitance (18) receives from ground patterns (14) is reduced. Accordingly, the characteristics of the capacitance (18) can be improved.

Abstract: The invention includes three-dimensional TFT based stacked CMOS inverters. Particular inverters can have a PFET device stacked over an NFET device. The PFET device can be a semiconductor-on-insulator thin film transistor construction, and can be formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The thin film of semiconductor material can comprise both silicon and germanium. Further, the thin film can contain two different layers. A first of the two layers can have silicon and germanium present in a relaxed crystalline lattice, and a second of the two layers can be a strained crystalline lattice of either silicon alone, or silicon in combination with germanium. The invention also includes computer systems utilizing such CMOS inverters.

Abstract: The impact strength resistance of a solder joint portion of a semiconductor device is improved. The semiconductor device has a joint structure wherein a jointing layer which does not contain sulfur substantially is arranged between an underlying conductive layer and a lead-free solder layer and further between the jointing layer and the lead-free solder layer is formed an alloy layer comprising elements of these layers.

Abstract: A semiconductor device includes an insulating film. On this insulating film, are formed an interconnection trench communicating with a semiconductor element and a pad trench communicating with the interconnection trench. In the pad trench, a protrusion is formed by leaving one part of the insulating film. A conductive film is formed over the insulating film including the interconnection and pad trenches. Thereafter, the conductive film is removed by a CMP process. At this time, the protrusion serves to prevent the conductive film in the pad trench from being over-polished.

Abstract: A dual-gate MOSFET with metal gates and a method for setting threshold voltage in such a MOSFET is provided. The method comprises: forming a gate oxide layer overlying first and second channel regions; forming a first metal layer having a first thickness overlying the gate oxide layer; forming a second metal layer having a second thickness overlying the first metal layer first thickness; selectively removing the second metal layer overlying the first channel region; forming a third metal layer; establishing a first MOSFET with a gate work function responsive to the thicknesses of the first and third metal layer overlying the first channel region; and, establishing a second MOSFET, complementary to the first MOSFET, with a gate work function responsive to the combination of the thicknesses of the first, second, and third metal layers overlying the second channel region.

Abstract: A method for manufacturing a semiconductor device is provided including: a step of forming a solid barrier metal layer on an interlayer insulating film; a removing step of removing at least a part of the solid barrier metal layer located at a place at which a pad opening portion is to be formed; a step of forming a solid second Al alloy film on the interlayer insulating film exposed in the removing step described above and the solid barrier metal layer; a step of patterning the solid second Al alloy film and the solid barrier metal layer so as to form a bonding pad portion on the interlayer insulating film; a step of forming a passivation film on the bonding pad portion and the interlayer insulating film; and a step of forming the pad opening portion in the passivation film at a position located on the bonding pad portion.

Abstract: A semiconductor device includes a first wiring line having a first through hole, and a first connection member which extends through the first through hole at an interval from the first wiring line.

Abstract: A chip-type semiconductor light-emitting device includes a semiconductor light-emitting chip connected to a pair of electrodes formed on a substrate. The semiconductor light-emitting chip is molded, together with respective parts of the electrodes, by resin. The electrode has a layered structure having a Cu layer, an Ni layer and an Au layer in that order from the lowermost layer, to have a step formed inside the mold by changing the wall thickness of the Cu layer.

Abstract: A placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slice 100 having a plurality of basic cells 110 formed in a matrix, in which first and second power source wirings 170 and 171 that traverse the plurality of basic cells 110 are connected to a plurality of signal wirings that are formed along a vertical direction to provide connections within each of the plurality of basic cells 110 and/or between the plurality of basic cells 110. The method includes: a first step of registering in the automatic pacing and routing apparatus definitions of effective pin positions A1-A14, B2-B13 and C1-C14; a second step of registering a net list in the automatic placing and routing apparatus; and a third step of determining the placement of pin positions and wiring routes, based on data for the definitions of the effective pin positions and the net list.

Abstract: A semiconductor device 1000 may include a protective insulation layer 50, a pad opening section 60 provided in the protective insulation layer 50, and a wiring layer which the pad opening section reaches. First and second wiring layers 30 and 32 are provided at levels below the wiring layer 40 which the pad opening section reaches. The first and second wiring layers 30 and 32 provided at levels below the wiring layer 40 which the pad opening section reaches are formed outside a region of the pad opening section 60 as viewed in a plan view.

Abstract: In a semiconductor heterojunction corresponding to the n-channel and p-channel, the present invention is to enable the selective carrier injection into each channel by employing a height difference of a Schottky barrier, &phgr; B, which is provided between a source/drain consisting of metal or semiconductor-intermetallic compound and a semiconductor film used for each channel of the semiconductor.

Abstract: The present invention provides a high-frequency module configuring a micro communication functional module, which includes a base substrate (2) which has multiple pattern wiring layers (6a) (6b) (9a) (9b) and dielectric insulating layers (5) (8) (11) formed therein, and has a buildup surface for smoothing the upper layer thereof, and a high-frequency element layer (4) formed on the buildup surface, which has an inductor (20) formed therein via an insulating layer (19) formed on the buildup surface. The base substrate (2) is provided with a region (30) where the pattern wiring layers (6a) (6b) (9a) (9b) are not formed from the upper layer to at least the mid portion thereof along the thickness direction, and the inductor (20) of the high-frequency element layer (4) is formed directly above the region (30).

Abstract: In a method of manufacturing a semiconductor device, semiconductor circuit elements or wiring patterns are formed on a semiconductor substrate. Then, a porous semiconductor oxide film is formed as an interlayer insulating film on the semiconductor substrate including the semiconductor circuit elements or wiring patterns by oxidizing semiconductor substance in a gas mixture containing an oxygen gas in a chamber.

Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a diffusion barrier layer is formed between the metal layer and the metal bond pad. In this manner, additional metal can be formed on the pad site using only one additional mask step, and thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Abstract: A semiconductor device includes a lower wiring layer, a first insulating layer formed on the lower wiring layer and having a via hole with a width, a via mask layer formed on the first insulating layer and having an opening with a width larger than the width of the via hole, a second insulating layer formed on the via mask layer and having an upper wiring, groove whose width coincides with the width of the via hole, a via contact structure buried in the via hole, and an upper wiring layer buried in the upper wiring groove.

Abstract: Isolated metal structures (110), (140) are formed adjacent to terminated metal lines (100), (130) that are connect by a via (120). The isolated structures (110), (140) act to suppress the stress created in the terminated metal lines (100), (130) during thermal cycling.

Abstract: A wiring structure of a semiconductor device and a method for manufacturing the same are provided. The wiring structure according to the present invention includes a body formed of a first conductive material in a first insulating film on a semiconductor substrate and a protrusion formed of a second conductive material in a second insulating film formed on the first insulating film, connected to the upper surface of the body, formed to have a width less than that of the body, and having a planarized upper surface.

Abstract: An integrated circuit (100) includes a semiconductor die (102, 103) and a semiconductor package (101) that has a leadframe (20, 40, 60, 80) for mounting the semiconductor die. The leadframe includes a first laminate (20) whose bottom surface (7) is patterned with leads (106, 107, 131, 132) of the integrated circuit. A second laminate (40) has a bottom surface (3) attached to a top surface (5) of the first laminate to electrically coupling the leads to the semiconductor die.

Abstract: Control of the characteristic impedance of wirings is performed with high accuracy.

Abstract: A method of fabricating a film of active devices is provided. First damaged regions are formed, in a substrate, underneath first areas of the substrate where active devices are to be formed. Active devices are formed onto the first areas. Second damaged regions are formed, in the substrate, between the first damaged regions. The film is caused to detach from a rest of the substrate at a location where the first and second damaged regions are formed.

Abstract: A connection device for a circuitry device connects a circuitry unit with a contact device to thermo-mechanically uncouple the circuitry unit and the contact device by forming the connection device as a metallic section and/or an alloy section having a buffer region, an intermediate region, and a connection region. The buffer region is of silver, the intermediate region (14) is of a silver-tin alloy region, and the connection region (16) is of an intermetallic substrate and, in particular, of an intermetallic tin-substrate.

Abstract: A semiconductor device has a bump electrode formed on a flat surface of a passivation film of the device. The bump electrode is connected to a top wiring layer through a plurality of openings in the passivation film underneath the bump electrode, which are filled with a conductive material. The bump electrode is formed away from via holes, which connects the top wiring layer for the bump electrode and a lower wiring layer connected to source and drain layers of the device.

Abstract: Disclosed is to provide an array substrate for display, a method of manufacturing the array substrate for display and a display device using the array substrate for display. The present invention is an array substrate for display, which includes: a thin film transistor array formed on an insulating substrate 1; a plurality of wirings 23 and 24 arranged on the insulating substrate 1; connection pads 25 and 27 arranged on unilateral ends of the wirings 23 and 24 and respectively connected therewith; and pixel electrodes 22, wherein dummy conductive patterns 29 are arranged between the ends of the connection pads 25 and 27 and ends of the pixel electrodes 22.

Abstract: A monolithic semiconducting ceramic electronic component includes barium titanate-based semiconducting ceramic layers and internal electrode layers alternately deposited, and external electrodes electrically connected to the internal electrode layers. The semiconducting ceramic layers contain ceramic particles having an average particle size of about 1 &mgr;m or less and the average number of ceramic particles per layer in the direction perpendicular to the semiconductor layers is about 10 or more. The internal electrode layers are preferably composed of a nickel-based metal.

Abstract: A method of connecting a conductive trace and an insulative base to a semiconductor chip includes providing a semiconductor chip, a conductive trace and an insulative base, wherein the chip includes a conductive pad, the conductive trace includes a bumped terminal, the bumped terminal includes a cavity that extends through the insulative base, and the insulative base contacts the conductive trace on a side opposite the chip, then forming a through-hole that extends through the insulative base and exposes the conductive trace and the pad, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, an insulative adhesive that attaches the chip to the conductive trace or an encapsulant that encapsulates the chip fills the cavity and provides compressible mechanical support for the bumped terminal.

Abstract: The present invention provides a system for self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simultaneously doping the silicon substrate and forming a low-resistance ohmic contact to it. The silver is coated with a layer of dopant. Once applied, the silver, substrate and dopant are heated to a temperature above the Ag—Si eutectic temperature (but below the melting point of silicon). The silver liquefies more than a eutectic proportion of the silicon substrate. This alloy of silver and silicon is the final contact material, and is composed of eutectic proportions of silicon and silver. Under eutectic proportions there is significantly more silver than silicon in the final contact material, thereby insuring good electrical conductivity of the final contact material.

Abstract: The structure around a high-resistance element is formed in mirror symmetry to a plane perpendicular to a semiconductor substrate and the surface of the sheet. Specifically, high-resistance element, contact plugs and extending portion of interconnection layers are symmetric, each of the interconnection layers covering high-resistance element by the same amount. Thus, a semiconductor device of which degree of freedom on designing layout of interconnections which is to be connected to interconnection layers electrically connected to the high-resistance element via contact plugs can be attained.

Abstract: A semiconductor chip having a semiconductor substrate; a surface protective film covering the semiconductor substrate; and an interconnection having a portion exposed on the surface protective film, at least the exposed portion of the interconnection being composed of an oxidation-resistant metal material. The interconnection includes, for example, an internal interconnection at least partly exposed from the surface protective film, and a metal coating film of the oxidation-resistant metal material covering a surface portion of the internal interconnection exposed from the surface protective film. The interconnection may be a surface interconnection of the oxidation-resistant metal material provided on the surface protective film.

Abstract: A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions.

Abstract: An electrode for a semiconductor device superior in die-bonding and wire-bonding characteristics with a submount and its manufacturing method are provided. The electrode is formed by ohmic-contacting the surface of a semiconductor, which comprises a substrate electrode E1 having a layer structure formed on the surface of the semiconductor and a surface electrode E2 formed by covering the surface and/or side face of the substrate electrode E1. The surface electrode is manufactured by a vacuum evaporation system or sputtering system provided with a holder which is tilted with respect to a material of the surface electrode and able to rotate on its axis and orbit the material.

Abstract: A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In an application requiring very fine pitch between bond pads, the probe regions (14) and active regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.

Abstract: For producing a semiconductor module, an electrically insulating layer and an electrically conductive layer are formed on a Nickel-base metal film over a metallic surface, the electrically conductive layer is connected electrically to an electric element through an electrically conductive joint arranged between the electric element and the electrically conductive layer, at least a part of the electric element and at least a part of the electrically conductive joint are covered with a molding resin, and subsequently, the Nickel-base metal film is removed from the metallic surface so that a combination of the Nickel-base metal film, the electrically insulating layer, the electrically conductive layer, the electrically conductive joint and the molding resin is separated from the metallic surface.

Abstract: A multi-layer device with a lid, a core, and a base. The lid has a first terminal and a second terminal, and an inner surface with a first insulator. The core has a first surface bonded to the first insulator and a second surface bonded to a second insulator, and includes a pillar electrically connected to the second terminal. The base has an inner surface bonded to the second insulator and a portion being electrically connected to the pillar. The first terminal of the lid and the base are adapted for electrically connecting to an interior electrical unit positioned within the core so that there are conductive paths from the electrical unit to the first and second terminals. The lid can include a third terminal in electrical contact with a portion of the core, and the portion of the core can be adapted for electrically connecting to the electrical unit.

Abstract: An ignition apparatus is provided for internal combustion engines to obtain higher reliability for the solder bonding parts. The ignition apparatus includes a molded case having an input-output terminal formed on the molded case, a semiconductor switching device, a control circuit board, and a heat sink. As such, the molded case provides a single body for containing the input-output terminal, the semiconductor switching device, the control circuit board and the heat sink. On the heat sink, one or more laminated structures are used, including the semiconductor switching devices with beryllia as an electric insulation plate.

Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiment relate to a manufacturing methods and semiconductor devices, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps.

Abstract: A phase-change memory may be formed with at least two phase-change material layers separated by a barrier layer. The use of more than one phase-change layer enables a reduction in the programming volume while still providing adequate thermal insulation.

Abstract: A semiconductor device includes a lower copper line formed on a substrate, an interlayer insulating layer formed on the lower copper line, and an upper copper line formed on the interlayer insulating layer. A copper via contact extends through the interlayer insulating layer for electrically connecting the lower copper line and the upper copper line. A concave recess is formed within the lower copper line and is vertically aligned and arranged below the copper via contact. A patterned barrier layer is formed at a bottom portion of the concave recess, such that the lower copper line and the copper via contact are directly electrically connected at an interface along sides of the concave recess, without an intervening barrier layer.

Abstract: Methods of forming a graded layer is disclosed. The graded layer transitions from one material to another material. The properties of these materials are chosen to optimize the interfaces on each side of the graded layer. Specifically, an improved transistor gate stack barrier layer may be formed by disposing an appropriate graded layer between a gate layer and an interconnect layer. In fact, the graded layer may obviate the use of the interconnect layer, as the top of the graded layer may include a highly conductive material. An improved integrated circuit interconnect structure may also be formed by grading the material composition of an interconnect layer.

Abstract: There is provided a semiconductor device comprising an insulating layer which is partly formed of porous material, and a method for fabricating the device. A stray capacitance of adjacent wiring lines is significantly reduced by reducing the amount of material, i.e., by using porous material in the insulating layer of a metallization layer. In one embodiment, the porous layer may be fabricated separately on a further substrate and is subsequently transferred to the product wafer while the further substrate and the product wafer are appropriately aligned to each other. In this way, fabrication of complete metallization layers having a reduced dielectric constant in advance or concurrently with the product wafer carrying the MOS structure is possible. Due to the reduced capacitance of the wiring lines of the metallization layer, signal performance and/or power consumption of an integrated circuit is improved.

Abstract: A semiconductor device includes a conductive layer formed on a silicon semiconductor substrate, cobalt silicide films formed in a surface layer of the conductive layer, an interlayer insulating film which covers the silicon semiconductor substrate thereabove, and a barrier metal film and a tungsten film which fill in a contact hole formed in the interlayer insulating film and is electrically connected to the cobalt silicide film. The positions of lower surfaces of the cobalt silicide films at the bottom of the contact hole are set lower than the position of a lower surface of the cobalt silicide film provided outside the contact hole. A cobalt silicide film having a necessary thickness can be ensured at the bottom of the contact hole. Further, a contact resistance can be reduced and a junction leak can be suppressed.

Abstract: A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g., ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g, ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.

Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle &agr; in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.

Abstract: A grid array package and a method for fabricating the same. The contact pads of the grid array package form three distinct groups: an outer array, a intermediate group, and a center array. The center array is positioned in the center of the package, the intermediate group forms a ring around the center array, and the outer array forms a ring around both the intermediate group and the inner array. The contact pads of the center array connect to ground. Most of the contact pads of the intermediate group connect to power, but selected contact pads of the intermediate group connect to ground. Within the outer array, most of the contact pads connect the integrated circuit to outside circuitry, but selected contact pads of the outer array connect to ground.

Abstract: The present invention provides a bonding structure between a bonding pad and a bonding portion of a bonding wire made of an Au-base material, wherein said bonding pad further comprises: a base layer; at least a barrier layer overlying said base layer; and a bonding layer overlying said at least barrier layer, said bonding layer including an Al-base material, and wherein said bonding portion of said bonding wire is buried in said bonding layer, and an Au—Al alloy layer extends on an interface between said bonding portion and said bonding layer, and a bottom of said Au—Al alloy layer is in contact with or adjacent to an upper surface of said barrier layer.

Abstract: A bond pad structure that is supported by a multiplicity of vias arranged in at least two regions each having a different via density than the other and a method for forming the structure are described. The structure includes a layer of an insulating material such as a low-k dielectric, a first multiplicity of vias formed in a center region of the low-k dielectric material that has a first density, a second multiplicity of vias formed in a peripheral region of the low-k dielectric material surrounding the center region that has a second density, wherein the second density is higher than the first density. A conductive metal pad of generally rectangular shape is then formed on top of and electrically connected to the first and second multiplicity of vias.