At Least Portion Of Which Is Transparent To Ultraviolet, Visible Or Infrared Light Patents (Class 257/749)
  • Patent number: 6759686
    Abstract: A light emitting diode (LED), and a method for producing the same. The LED includes a substrate that may be made of silicon, a first conductive layer on one side, and a porous insulating layer on the opposite side. The insulating layer defines microcavities therein, the microcavities having sharp tips on their inner surfaces. The microcavities have gas inside. A second conductive layer is disposed over the insulating layer. When an electrical potential is applied between the conductive layers, the gas-filled microcavities act as plasma discharge lamps, emitting light. The light may be in the ultraviolet portion of the spectrum. The method includes etching a substrate to produce a porous insulating layer on one side, depositing a first conductive layer on the opposite side, and depositing a second conductive layer over the insulating layer. The microcavities in the insulating layer are then filled with gas.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: July 6, 2004
    Inventors: Kok Wai Cheah, Wai Kwok Wong, Hoi Lam Tam
  • Patent number: 6740973
    Abstract: An image sensor, which is electrically connected to a printed circuit board. The image sensor includes a transparent glass layer on which signal input terminals and signal output terminals are formed, a photosensitive chip on which bonding pads are formed, a substrate, and an integrated circuit. Each bonding pad is formed with a projection, and the photosensitive chip is electrically connected to the signal input terminals through the projections. The substrate has a first surface, a second surface, and a first through hole penetrating through the substrate from the first surface to the second surface. The signal output terminals are electrically connected to the first surface of the substrate with the photosensitive chip positioned within the first through hole. The second surface is electrically connected to the printed circuit board. The integrated circuit is electrically connected to the second surface of the substrate.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: May 25, 2004
    Assignee: Kingpak Technology Inc.
    Inventor: Chung Hsien Hsin
  • Patent number: 6737679
    Abstract: An optoelectronic unit and a transparent conductive substrate of the same are disclosed. The transparent conductive substrate comprises a transparent plate, a transparent electrode film, an insulation part, and a bounding pad, wherein the transparent electrode film and the insulation part are formed on the transparent plate, the insulation part divides the transparent electrode film into a first transparent electrode film area and a second transparent electrode film area that non-conduct each other, and the bounding pad is formed on the second transparent electrode film area. The optoelectronic unit comprises the aforementioned transparent conductive substrate, an optoelectronic element, and a conductive wire, wherein one electrode of the optoelectronic element is electrically connected to the aforementioned first transparent electrode film area, and the other electrode of the optoelectronic element is electrically connected to the aforementioned bounding pad by the conductive wire.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: May 18, 2004
    Assignee: Highlink Technology Corporation
    Inventors: Ming-Der Lin, Kwang-Ru Wang
  • Patent number: 6734515
    Abstract: A semiconductor light receiving element having a light receiving layer (1) formed from a GaN group semiconductor, and an electrode (2) formed on one surface of the light receiving layer as a light receiving surface (1a) in such a way that the light (L) can enter the light receiving layer is provided. When the light receiving element is of a Schottky barrier type, the aforementioned electrode (2) contains at least a Schottky electrode, which is formed in such a way that, on the light receiving surface (1a), the total length of the boundary lines between areas covered with the Schottky electrode and exposed areas is longer than the length of the outer periphery of the light receiving surface (1a).
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: May 11, 2004
    Assignees: Mitsubishi Cable Industries, Ltd., Nikon Corporation
    Inventors: Kazuyuki Tadatomo, Hiroaki Okagawa, Youichiro Ohuchi, Masahiro Koto, Kazumasa Hiramatsu, Yutaka Hamamura, Sumito Shimizu
  • Publication number: 20040070076
    Abstract: An semiconductor chip package for image sensor includes an semiconductor chip for image sensor, a base member with a groove to that the semiconductor chip is mounted therein, a lead formed through the base member and spaced apart from the semiconductor chip, a conductive connecting member for electric connection between the lead and the semiconductor chip, and a transparent seal material formed in the groove for sealing the semiconductor chip for image sensor and the conductive connecting member, wherein an upper surface of the seal material is parallel with an upper surface of the semiconductor chip.
    Type: Application
    Filed: November 19, 2002
    Publication date: April 15, 2004
    Inventors: Yoshiaki Hayashimoto, Young-Joo Seo
  • Patent number: 6707148
    Abstract: An optical integrated circuit application where the integrated circuit is packaged in a clear molding material and is attached to a printed circuit board having an aperture is described. The integrated circuit senses and/or emits light through the clear molding material and through the aperture in the printed circuit board.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: March 16, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Shahram Mostafazedeh, Joseph O. Smith
  • Patent number: 6680488
    Abstract: This invention provides a liquid crystal display device having high display quality by preventing rays of light diffracted at an end part of a light shielding layer because such rays are irradiated to a semiconductor layer and invite fluctuation of TFT characteristics. To completely cut off the rays of light 117 diffracted at an end part of a third light shielding layer 108, a gate electrode 104 and a second light shielding portion 106 cover a semiconductor layer 103. In consequence, the irradiation of the rays of diffracted light can be prevented, fluctuation of TFT characteristics can be avoided and satisfactory display images can be acquired.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: January 20, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroshi Shibata
  • Patent number: 6650018
    Abstract: A high power, high luminous flux light emitting diode (LED) comprises a substrate, a light-emitting structure, a first electrode and a second electrode. The LED has a top surface layout design in which the first electrode has a number of legs extending in one direction, and the second electrode has a number of legs extending in the opposite direction. At least portions of the legs of the first electrode are interspersed with and spaced apart from portions of the legs of the second electrode. This provides a configuration that enhances current spreading along the length of the legs of both electrodes.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: November 18, 2003
    Assignee: AXT, Inc.
    Inventors: Yongsheng Zhao, William W. So, Kevin Y. Ma, Chyi S. Chern, Heng Liu, Eugene J. Ruddy
  • Patent number: 6610995
    Abstract: A gallium nitride-based III-V Group compound semi-conductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: August 26, 2003
    Assignee: Nichia Corporation
    Inventors: Shuji Nakamura, Takao Yamada, Masayuki Senoh, Motokazu Yamada, Kanji Bando
  • Patent number: 6583443
    Abstract: A light emitting epi-layer structure which contains a temporality light absorption substrate on one side, the other side thereof can be adhered to a light absorption free transparent substrate in terms of a transparent adhesive layer which is light absorption free too. After that, the light absorption substrate portion is removed by means of an etching process. The resulted light emitting diode has significant improvement in light emitting efficiency. Moreover, the transparent conductive layer is a low resistance and high transparency layer. The current flow can thus be distributed evenly than conventional one.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: June 24, 2003
    Assignee: United Epitaxy Co., Ltd.
    Inventors: Chih-Sung Chang, Kuang-Neng Yang, Tzer-Perng Chen
  • Publication number: 20030052327
    Abstract: An organic light emitting device display may be formed that is suitably passivated while still permitting electrical access to cathodes and anodes via electrical contacts. In one embodiment, a barrier layer may be formed over the light emitting material to prevent moisture or other ambient attack. The barrier layer may be covered with other layers to form an outer and inner via down to the cathode or anode to be contacted. A contact metal may be provided to the anode or cathode. The layers over the barrier layer permit patterning and contact formation while the barrier layer adequately protects the light emitting material during those steps and thereafter.
    Type: Application
    Filed: September 18, 2001
    Publication date: March 20, 2003
    Inventors: Robert F. Kwasnick, Mary E. Swallow
  • Patent number: 6522000
    Abstract: A method for making a semiconductor device is described. That method comprises forming a copper containing layer on a substrate, then forming a tantalum containing layer on the copper containing layer. After the tantalum containing layer is oxidized, an etch stop layer may be formed on the oxidized tantalum layer.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: February 18, 2003
    Assignee: Intel Corporation
    Inventor: Ajay Jain
  • Patent number: 6515310
    Abstract: A light shield film is provided adjacent to an anode of an EL element that consists of the anode, an EL layer, and a cathode. The anode and the cathode are transparent or semitransparent to visible light and hence transmit EL light. With this structure, ambient light is absorbed by the light shield film and does not reach an observer. This prevents an external view from appearing on the observation surface.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: February 4, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 6507041
    Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: January 14, 2003
    Assignee: Nichia Chemical Industries, Ltd.
    Inventors: Shuji Nakamura, Takao Yamada, Masayuki Senoh, Motokazu Yamada, Kanji Bando
  • Patent number: 6507045
    Abstract: A liquid crystal display having an increased pixel aperture ratio is disclosed along with a method of making same. An array of a-Si TFTs is deposited on a transparent substrate. Subsequently, an organic insulating layer (e.g. Benzocyclobutene) and a corresponding array of pixel electrodes are deposited over the TFT array so that the pixel electrodes overlap the display address lines thereby increasing the display's pixel aperture ratio. The low dielectric constant &egr; (e.g. about 2.7) and relatively high thickness (e.g. greater than about 1.5 &mgr;m) of the insulating layer reduce the pixel electrode-address line parasitic capacitance CPL in the overlap areas thereby reducing cross-talk (or capacitive coupling) in the display. In sum, an increased pixel aperture ratio is achieved without sacrificing display performance.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: January 14, 2003
    Assignee: LG Philips LCD Co., Ltd.
    Inventors: Tieer Gu, Willem den Boer
  • Patent number: 6504178
    Abstract: A semiconductor imaging device is disclosed. The device includes a substrate having at least first and second surfaces opposing each other, and a circuit layer. The substrate is doped to exhibit a first conductivity type. The substrate includes a conducting layer, a region, and a plurality of doped regions. The conducting layer includes a first type dopants incorporated near the first surface. The region includes a heavily doped area within the substrate near the second surface. The plurality of doped regions includes a second type dopants formed on the second surface. The circuit layer is formed over the second surface to provide gate contacts to and readout circuits for the plurality of doped regions. The readout circuit provides readout of optical signals from pixels.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: January 7, 2003
    Assignee: Digirad Corporation
    Inventors: Lars S. Carlson, Shulai Zhao, Richard Wilson
  • Patent number: 6489675
    Abstract: The optical semiconductor component has a semiconductor body having a first surface with an active region and a second surface with a passive region. An optically transparent layer adjoins at least the optically active region. Conduction paths extend from the active region through the semiconductor body to contact-making points in the region of the second surface.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: December 3, 2002
    Assignee: Infineon Technologies AG
    Inventors: Martin Gruber, Gernot Althammer
  • Publication number: 20020163012
    Abstract: A semiconductor triode comprises a gate electrode provided on a channel layer, wherein there is interposed an insulating metal oxide layer between a top surface of the channel layer and the gate electrode.
    Type: Application
    Filed: December 26, 2000
    Publication date: November 7, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Mizuhisa Nihei, Yuu Watanabe
  • Publication number: 20020105080
    Abstract: A method of forming an electronic device using the technique of drop on demand printing to deposit droplets of deposition material, said method comprising depositing a plurality of droplets on a surface to form a patterned electronic device comprising multiple discrete portions.
    Type: Application
    Filed: February 6, 2002
    Publication date: August 8, 2002
    Inventor: Stuart Speakman
  • Patent number: 6417525
    Abstract: A semiconductor light emitter characterized by including a semiconductor layer for providing an electric current block region and an electric current injection region on a surface thereof, an electric current block layer formed on the semiconductor layer for defining the electric current block region, a pad electrode formed on the electric current block layer, and a light-transmissive electrode formed on the semiconductor layer for defining the electric current injection region, wherein the pad electrode has an electrode connection portion for connection with the light-transmissive electrode. Such a semiconductor light emitter can prevent failure in electric current introduction into the light emitter owing to disconnection of the light-transmissive electrode and increase of the resistance of the light-transmissive electrode. It is possible to produce light emitters with good behavior in a good yield.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: July 9, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshio Hata
  • Patent number: 6399958
    Abstract: Aspects for electrical trace inspection during device analysis for devices with solder ball attachments are described. In a method aspect, the method includes forming a desired integrated circuit device including bond wire attachments. The bond wire attachments are then utilized with electrical traces in a transparent tape layer, with visual inspection of the electrical traces performed through the transparent polyimide tape. In an apparatus aspect, the apparatus includes an integrated circuit die, the integrated circuit die including bond pads. The apparatus further includes bond wires coupled to the bond pads of the integrated circuit die, and a transparent tape layer, including a plurality of traces for electrically connecting to the bond wires, wherein visual inspection of the plurality of traces occurs through the transparent tape layer.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: June 4, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mohammad Massoodi
  • Patent number: 6372560
    Abstract: A simplified process for forming a thin film transistor matrix for a liquid crystal display is disclosed. By forming and patterning a conductive layer overlying a TFT unit, a data line, a first connection line between the TFT unit and the data line, and a second connection line between the TFT unit and a pixel electrode can be simultaneously formed in the forming and patterning step. Furthermore, after a passivation layer is applied to protect the TFT matrix, an isolation window area, a contact hole and a TAB window can be created in a single patterning step. Therefore, masking steps can be reduced so as to simplify the process. On the other hand, owing to the first connection line for connecting the TFT unit and the scan line is of the same material as the scan line, the resistivity of the connection line is inherently low. Therefore, a TFTLCD of a large area can be made according to this process.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: April 16, 2002
    Assignee: Hannstar Display Corp.
    Inventors: Tean-Sen Jen, Jia-Shyong Cheng
  • Patent number: 6316832
    Abstract: A moldless semiconductor device comprising a semiconductor chip held between outer-connecting terminals and connected electrically to the terminals is provided. At least one of the two terminals has, at its region contiguous to the semiconductor chip or at its region contiguous to the semiconductor chip and a region vicinal thereto, a hardness different from all other regions of the one terminal. This moldless semiconductor device can withstand significant external force and exhibits high reliability when used in photovoltaic device modules.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: November 13, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Koji Tsuzuki, Tsutomu Murakami, Satoru Yamada, Yoshifumi Takeyama, Koichi Shimizu
  • Patent number: 6246071
    Abstract: This invention pertains to a device of a substrate and a ZrO2-based semiconductor disposed thereon and a method for depositing the semiconductor on the substrate. The semiconductor is typically in the form of a film of 1-20 weight % ZrO2 and 99-80 weight % In2O3 or SnO2 . The semiconductor is tunable in terms of optical transmission and electrical conductivity. Its transmission is in excess of about 80% over the wavelength range of 400-900 nm and its resistivity is from about 1.3×10−3 &OHgr;-cm to about 6.5×10−2 &OHgr;-cm. The deposition method is characterized by depositing in a chamber the semiconductor on a substrate by means of a physical vapor deposition whole maintaining a small oxygen pressure in the chamber.
    Type: Grant
    Filed: September 23, 1999
    Date of Patent: June 12, 2001
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Syed B. Qadri, Earl F. Skelton, Alberto Pique, James S. Horwitz, Douglas B. Chrisey, Heungsoo Kim
  • Patent number: 6204512
    Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.
    Type: Grant
    Filed: November 24, 1999
    Date of Patent: March 20, 2001
    Assignee: Nichia Chemical Industries, Ltd.
    Inventors: Shuji Nakamura, Takao Yamada, Masayuki Senoh, Motokazu Yamada, Kanji Bando
  • Patent number: 6191436
    Abstract: A LED has a thin highly resistive or insulative layer formed below an electrode pad in order to divert current flow from the region below an electrode pad, which region does not contribute to light emission, to another region which does. Consequently, better current efficiency is obtained. Further, diverting current flow from the region below the electrode pad where mechanical damages are expected deters deterioration of the region. Consequently, the LED lasts longer and is a better quality product.
    Type: Grant
    Filed: March 12, 1996
    Date of Patent: February 20, 2001
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Makoto Asai
  • Patent number: 6107680
    Abstract: A structure and method for protecting semiconductor integrated microcircuit dice during shipping. The structure secures the position of the die or dice atop an EMR-penetrable element using an adhesive layer, the stickiness, adhesiveness or coefficient of friction of which is alterable by exposure to EMR of a predetermined wavelength range, such as ultraviolet light. Once the structure reaches its destination, prior to removal of the dice, the adhesive layer is exposed to EMR, such as ultraviolet light, through the element. This exposure reduces the stickiness, adhesiveness, or coefficient of friction of the adhesive to facilitate die removal. The EMR-sensitive adhesive does not leave contaminating silicon residue on the removed die. The invention may be realized using currently commercially available UV tape and modified die-pac designs having UV light penetrable die transport portions, or tape-and-reel type die transport structures.
    Type: Grant
    Filed: September 8, 1998
    Date of Patent: August 22, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Joe W. Hodges
  • Patent number: 6093965
    Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: July 25, 2000
    Assignee: Nichia Chemical Industries Ltd.
    Inventors: Shuji Nakamura, Takao Yamada, Masayuki Senoh, Motokazu Yamada, Kanji Bando
  • Patent number: 6057587
    Abstract: A semiconductor devices includes an anti-reflective structure for use in patterning metal layers in semiconductor devices. The anti-reflective structure is made, at least in part, using indium tin oxide. The anti-reflective structure is especially useful for patterning the metal layers with light having a wavelength of 190-300 nm. The anti-reflective structure may be a single indium tin oxide layer or may include a titanium nitride layer formed over the metal layer and an indium tin oxide layer formed over the titanium nitride layer. For many applications, the anti-reflective structure, in the presence of a photoresist layer, has a reflectivity of about 3% or less for light having a wavelength of 190-300 nm.
    Type: Grant
    Filed: August 28, 1997
    Date of Patent: May 2, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Kouros Ghandehari, Samit Sengupta
  • Patent number: 5977566
    Abstract: A compound semiconductor light emitting element includes a light emitting region formed by a pn-junction between a first compound semiconductor layer of a first conductivity type and a second compound semiconductor layer of a second conductivity type. A first electrode is connected to the first compound semiconductor layer and is isolated from the second compund semiconductor layer. A current spreading layer is formed on the second compound semiconductor layer and a block is formed on the second compound semiconductor layer. A second electrode is formed on the block and is connected to the current spreading layer.
    Type: Grant
    Filed: June 5, 1997
    Date of Patent: November 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Haruhiko Okazaki, Yukio Watanabe
  • Patent number: 5945740
    Abstract: A semiconductor device comprising a lower level pattern formed on a semiconductor substrate, an interlayer insulator film covering the lower level pattern, and an upper level pattern formed on the interlayer insulator film, a step being formed on a surface of the interlayer insulator film because of the lower level pattern. The upper level pattern having a dummy pattern formed integrally therewith to extend near to the step in a plan view or to extend so as to partially overlap with the step in the plan view. Alternatively, the lower level pattern has a dummy pattern formed integrally therewith to extend near to an edge of the upper level pattern in a plan view, or to extend so as to overlap partially with the edge of the upper level pattern in the plan view.
    Type: Grant
    Filed: July 28, 1997
    Date of Patent: August 31, 1999
    Assignee: NEC Corporation
    Inventor: Takayuki Kawazoe
  • Patent number: 5877558
    Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: March 2, 1999
    Assignee: Nichia Chemical Industries, Ltd.
    Inventors: Shuji Nakamura, Takao Yamada, Masayuki Senoh, Motokazu Yamada, Kanji Bando
  • Patent number: 5864149
    Abstract: A multi-layer structure of source/drain electrodes and an amorphous silicon layer in a forward staggered thin film transistor. Source/drain electrodes are selectively provided on an insulator. Each of the source/drain electrodes comprises an undoped transparent conductive film on the insulator and an impurity doped transparent conductive film extending over the undoped transparent conductive film. An amorphous silicon active layer extends over the source/drain electrodes and a top surface of the insulator so that the amorphous silicon active layer over the source/drain electrodes has an impurity diffused interface in contact with the impurity doped transparent conductive film to form ohmic contacts between the impurity doped transparent conductive film and the amorphous silicon active layer. The amorphous silicon active layer in contact with the top surface of the insulator between the source/drain electrodes is free of impurities.
    Type: Grant
    Filed: April 17, 1997
    Date of Patent: January 26, 1999
    Assignee: NEC Corporation
    Inventor: Shuki Yamamori
  • Patent number: 5847410
    Abstract: A display device comprising a pixel portion having a thin film transistor using silicon as a semiconductor layer and a pixel electrode connected to the thin film transistor, wherein: said pixel electrode having a first transparent electrically conductive film electrically connected to said semiconductor layer and a second transparent electrically conductive film disposed on the first transparent electrically conductive film; said first transparent electrically conductive film comprises an oxide layer of a first metal having an oxidation potential lower than that of silicon; and said second transparent electrically conductive film comprises an oxide layer of a second metal having an oxidation potential higher than that of silicon. Also claimed is a process for fabricating the display device.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: December 8, 1998
    Assignee: Semiconductor Energy Laboratory Co.
    Inventor: Setsuo Nakajima
  • Patent number: 5840620
    Abstract: A method for counteracting increases in resistivity encountered when Indium Oxide resistive layers are subjected to high temperature annealing steps during semiconductor device fabrication. The method utilizes a recovery annealing step which returns the Indium Oxide layer to its original resistivity after a high temperature annealing step has caused the resistivity to increase. The recovery anneal comprises heating the resistive layer to a temperature between 100.degree. C. and 300.degree. C. for a period of time that depends on the annealing temperature. The recovery is observed even when the Indium Oxide layer is sealed under a dielectric layer.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: November 24, 1998
    Inventors: Carleton H. Seager, Joseph Tate Evans, Jr.
  • Patent number: 5798537
    Abstract: There is disclosed a blue light emitting device having a laminated structure, which comprises a buffer layer made of a first conductivity type GaN-based semiconductor, a first cladding layer made of the first conductivity type GaN-based semiconductor, an active layer made of a substantially intrinsic GaN-based semiconductor, and a second cladding layer made of a second conductivity type GaN-based semiconductor, on a conductive substrate such as a conductive sapphire substrate. The GaN-based semiconductors of the present invention are made of quaternary compound semiconductor layers, and preferably made of In.sub.x A.sub.y Ga.sub.1-x-y N whose mole fraction values x, y satisfy 0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1 and x+y.ltoreq.1. The mole fraction values x, y are selected to obtain desired luminous wavelength and intensity.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: August 25, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koichi Nitta
  • Patent number: 5777390
    Abstract: An improved metal-semiconductor-metal (MSM) photodiode, specifically a new high responsivity AND high bandwidth photodetector, resulting in a high gain-bandwidth product is disclosed. The disclosed device is an MSM photodiode in which the anode and cathode are made of different materials of differing opacity and possibly including different electrode dimensions as well. Using an opaque anode and a transparent cathode reduces surface reflections off the opaque electrodes allowing more light to be absorbed within the active semiconductor region. However, it concurrently keeps the transit distance for the slower moving holes to a minimum. Thus, the long tail in the impulse response due to hole collection is minimized, resulting in increased bandwidth.
    Type: Grant
    Filed: October 10, 1995
    Date of Patent: July 7, 1998
    Assignee: The University of Delaware
    Inventors: Paul R. Berger, Wei Gao
  • Patent number: 5767581
    Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.
    Type: Grant
    Filed: June 17, 1996
    Date of Patent: June 16, 1998
    Assignee: Nichia Chemical Industries, Ltd.
    Inventors: Shuji Nakamura, Takao Yamada, Masayuki Senoh, Motokazu Yamada, Kanji Bando
  • Patent number: 5757058
    Abstract: A pad for providing an electrical connection to a liquid crystal display (LCD) includes a first indium tin oxide (ITO) layer provided on a surface of an insulative substrate. At least one metal layer is provided on the first ITO layer and a second ITO layer, in turn, is disposed on the metal layer so that the metal layer is effectively embedded in ITO material. The metal layer is thus shielded from humidity effects and the resulting pad has improved conductivity and reduced signal propagation delay. A recessed portion may be provided in a top surface of the pad so that a spherical conductor spreading during a subsequent bonding process is prevented. The metal layer may be fabricated in the same step that the gate layer of a TFT is formed, and the second ITO layer may be formed concurrently with a pixel electrode of the LCD.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: May 26, 1998
    Assignee: LG Electronics Inc.
    Inventor: In Duk Song
  • Patent number: 5744864
    Abstract: A semiconductor device includes a transparent switching element (1) with two connection electrodes (2, 3) of a transparent material and an interposed transparent channel region (4) of a semiconductor material provided with a transparent gate electrode (5) of a conductive material, separated from the channel region (4) by a transparent insulating layer (6). The semiconductor material is a degenerate semiconductor material with a basic material having a bandgap (10) between conduction band (11) and valence band (12) of electrons greater than 2.5 eV and a mobility of charge carriers greater than 10 cm.sup.2 /Vs provided with dopant atoms which form a fixed impurity energy level (13) adjacent or in the valence band (12) or conduction band (11) of the basic material. The degenerate semiconductor material is transparent because the absorption of visible light is not possible owing to the great bandgap (10), while also no absorption of visible light takes place through the impurity energy levels (13).
    Type: Grant
    Filed: August 1, 1996
    Date of Patent: April 28, 1998
    Assignee: U.S. Philips Corporation
    Inventors: Johannes F. M. Cillessen, Paulus W. M. Blom, Ronald M. Wolf, Jacobus B. Giesbers
  • Patent number: 5728592
    Abstract: A thin film transistor matrix device is fabricated by forming a transparent conductor film and a metal film on an insulating substrate in this order. The metal film and the transparent conductor film are together patterned to form picture element electrodes, and drain bus lines or gate bus lines. Source electrodes and drain electrodes may also be formed from the transparent conductor film and metal film. A semiconductor layer, an insulating film and a conductor film may be formed on the entire surface in this order. In this case, the conductor film, the insulator film and the semiconductor layer are patterned to form an active layer from the semiconductor layer, gate insulating films from the insulating film, and gate electrodes and gate bus lines from the conductor film. By patterning the conductor film, the insulating film and the semiconductor layer, the metal film of the picture element electrodes and drain bus lines is exposed.
    Type: Grant
    Filed: July 6, 1995
    Date of Patent: March 17, 1998
    Assignee: Fujitsu Ltd.
    Inventors: Ken-ichi Oki, Ken-ichi Yanai, Tamotsu Wada, Koji Ohgata, Yutaka Takizawa, Masahiro Okabe, Tsutomu Tanaka
  • Patent number: 5600155
    Abstract: Array circuitry formed at the surface of a substrate includes M scan lines that cross N data lines. The array circuitry also includes cell circuitry connected to the mth scan line and the nth data line. The cell circuitry includes a component with a data lead for receiving signals from or providing signals to the nth data line. The cell circuitry also includes connecting circuitry with first and second semiconductor lines. The first semiconductor line has a channel between the nth data line and the data lead of the component. The second semiconductor line is connected to the mth scan line and crosses the first semiconductor line at the channel. Because the second semiconductor line is conductive, signals on the mth scan line control conductivity of the channel. The semiconductor lines can be polysilicon, and the scan lines can be aluminum. The component can include a capacitive element with one electrode under the (m+1)th scan line, part of which forms the other electrode of the capacitor.
    Type: Grant
    Filed: December 14, 1995
    Date of Patent: February 4, 1997
    Assignee: Xerox Corporation
    Inventor: I-Wei Wu
  • Patent number: 5589712
    Abstract: A semiconductor integrated circuit device includes a substrate formed with semiconductor elements and a metal wiring having a laminated structure and provided on the substrate. The metal wiring includes a first layer including aluminum as a main component, and a second layer formed on the first layer. The second layer includes titanium and nitrogen as main components. The second layer includes more titanium than nitrogen in number of atoms. A third layer may be formed between the first and second layers. The third layer includes a compound of aluminum and titanium as a main component. A fourth layer may further be formed between the second and third layers. The fourth layer includes titanium as a main component and is free of aluminum.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: December 31, 1996
    Assignee: Ricoh Company, Ltd.
    Inventors: Ikue Kawashima, Katsunari Hanaoka
  • Patent number: 5397920
    Abstract: A light transmissive, electrically conductive oxide comprising tin and a Group II element is doped with a Group III element and with one or more of hydrogen or fluorine. The oxide may be deposited by sputtering at a temperature in the range from 25.degree. to 350.degree. C., or by chemical vapor deposition at temperatures in the range from 80.degree. to 400.degree. C.
    Type: Grant
    Filed: March 24, 1994
    Date of Patent: March 14, 1995
    Assignee: Minnesota Mining and Manufacturing Company
    Inventor: Nang T. Tran
  • Patent number: 5396103
    Abstract: A II-VI laser diode including a substrate, a device layer of p-type II-VI semiconductor, an electrode and an ohmic contact layer between the electrode and device layer. The ohmic contact layer comprises a graded composition semiconductor compound including ZnTe. The relative amount of ZnTe in the semiconductor compound increases with increasing distance of the ohmic contact layer from the device layer. In a first embodiment the ohmic contact layer comprises a graded composition semiconductor alloy including the semiconductor compound of the device layer and ZnTe. The amount of ZnTe in the alloy increases with increasing distance of the ohmic contact layer from the device layer in the first embodiment. In a second embodiment the ohmic contact layer includes layers of ZnTe spaced between layers of the semiconductor compound of the device layer.
    Type: Grant
    Filed: February 12, 1993
    Date of Patent: March 7, 1995
    Assignee: Minnesota Mining and Manufacturing Company
    Inventors: Jun Oiu, James M. DePuydt, Hwa Cheng, Michael A. Haase
  • Patent number: 5369289
    Abstract: A light-emitting device comprises an n-type layer made of an n-type gallium nitride-based compound of the formula Al.sub.x Ga.sub.1-x N, wherein 0.ltoreq.X<1, and an i-type layer formed on the n-type layer and made of a semi-insulating i-type gallium nitride-based compound semiconductor and doped with a p-type impurity for junction with the n-type layer. A first electrode is formed on the surface of the i-type layer and made of a transparent conductive film and a second electrode is formed to connect to the n-type layer through the i-type layer. The device is so arranged that light is emitted from the side of the i-type layer to the outside. When an electric current is supplied to the first electrode from a wire contacted thereto, the first electrode is held entirely at a uniform potential. Light is emitted from the entire interface beneath the first electrode and can thus be picked up from the first electrode which is optically transparent.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: November 29, 1994
    Assignees: Toyoda Gosei Co. Ltd., Kabushiki Kaisha Toyota Chuo Kenkyusho
    Inventors: Makoto Tamaki, Takahiro Kozawa
  • Patent number: 5352300
    Abstract: A solar cell having a semiconductor layer has a structure in which a first electrode, a semiconductor layer, and a second electrode are stacked on a substrate, wherein a zinc oxide layer containing a transition metal is located between the semiconductor layer and at least one of the first and second electrodes and the density of the transition metal in the zinc oxide layer is continuously changed within a range of not less than 1 atm. ppm to not more than 5 atm %.
    Type: Grant
    Filed: September 24, 1992
    Date of Patent: October 4, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mitsuyuki Niwa
  • Patent number: 5340409
    Abstract: A photovoltaic element has a photoelectric conversion layer and a collecting electrode formed thereon by curing a paste having at least an electroconductive base substance and a curable resin formed on the photoelectric conversion layer. The number average molecular weight of the curable resin is 3000 or less.
    Type: Grant
    Filed: April 15, 1993
    Date of Patent: August 23, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventors: Koji Tsuzuki, Nobuyoshi Takehara
  • Patent number: 5324365
    Abstract: A solar cell has a semiconductor layer sandwiched between first and second electrodes, wherein a zinc oxide layer containing carbon atoms, nitrogen atoms, or carbon and nitrogen atoms is located between the semiconductor layer and at least one of the first and second electrodes. The density of carbon atoms, nitrogen atoms, or carbon and nitrogen atoms in the zinc oxide layer is constant or continuously changed within the range of 5 atm % or less.
    Type: Grant
    Filed: September 22, 1992
    Date of Patent: June 28, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mitsuyuki Niwa
  • Patent number: 5294833
    Abstract: An ohmic contact to a p-type zinc selenide (ZnSe) layer in a Group II-VI semiconductor device, includes a zinc telluride selenide (ZnTe.sub.x Se.sub.1-x) layer on the zinc selenide layer, a mercury selenide (HgSe) layer on the zinc telluride selenide layer and a conductor (such as metal) layer on the mercury selenide layer. The zinc telluride selenide and mercury selenide layers between the p-type zinc selenide and the conductor layer provide an ohmic contact by eliminating the band offset between the wide bandgap zinc selenide and the conductor. Step graded, linear graded, and parabolic graded layers of zinc telluride selenide may be provided. An integrated heterostructure is formed by epitaxially depositing the ohmic contact on the Group II-VI device. A removable overcoat layer may be formed on the Group II-VI device to allow room temperature atmospheric pressure transfer of the device from a zinc based deposition chamber to a mercury based deposition chamber, for deposition of the ohmic contact.
    Type: Grant
    Filed: August 21, 1992
    Date of Patent: March 15, 1994
    Assignee: North Carolina State University
    Inventor: Jan F. Schetzina