Recrystallized Semiconductor Material Patents (Class 257/75)
  • Patent number: 10128358
    Abstract: A transistor comprising a semiconductor substrate comprising a collector region extending from a main surface of the semiconductor substrate into a substrate material. The transistor comprising a base structure arranged at the collector region along a thickness direction parallel to a direction of a normal of the main surface of the semiconductor substrate, where an emitter structure arranged at the base structure is averted from the semiconductor substrate and along the thickness direction. The transistor comprising a doped electrode layer arranged at a lateral surface region of the base structure and along a lateral direction perpendicular to the thickness direction. The doped electrode layer and the base structure form a monocrystalline connection.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: November 13, 2018
    Assignee: Infineon Technologies Dresden GMBH
    Inventors: Claus Dahl, Dmitri Alex Tschumakow
  • Patent number: 9799696
    Abstract: An image sensor includes a semiconductor material with a photodiode disposed in the semiconductor material. The image sensor also includes a transfer gate electrically coupled to the photodiode to extract image charge from the photodiode in response to a transfer signal. A floating diffusion is electrically coupled to the transfer gate to receive the image charge from the photodiode. At least one isolation structure is disposed in the photodiode, and the at least one isolation structure extends from a surface of the semiconductor material into the photodiode.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: October 24, 2017
    Assignee: OmniVision Technologies, Inc.
    Inventors: Dyson H. Tai, Duli Mao, Cunyu Yang, Gang Chen
  • Patent number: 9487390
    Abstract: A semiconductor element of the electric circuit includes a semiconductor layer over a gate electrode. The semiconductor layer of the semiconductor element is formed of a layer including polycrystalline silicon which is obtained by crystallizing amorphous silicon by heat treatment or laser irradiation, over a substrate. The obtained layer including polycrystalline silicon is also used for a structure layer such as a movable electrode of a structure body. Therefore, the structure body and the electric circuit for controlling the structure body can be formed over one substrate. As a result, a micromachine can be miniaturized. Further, assembly and packaging are unnecessary, so that manufacturing cost can be reduced.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: November 8, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mayumi Yamaguchi, Konami Izumi
  • Patent number: 9324846
    Abstract: A method of forming a heterojunction bipolar transistor including a field plate. The method may include forming: a substrate having a selectively implanted collector (SIC) and a collector separated by a shallow trench isolation (STI), a field plate in the STI, the field plate extends below a top surface of the SIC, a base layer directly on the SIC, a heterojunction bipolar transistor (HBT) structure above the SIC, the HBT includes an emitter, the emitter is directly on the base layer, a fourth dielectric layer covering the HBT structure, the field plate and the collector, and an emitter contact, a field plate contact and a collector contact extending through the fourth dielectric layer, the emitter contact is in electrical connection with the emitter, the field plate contact is in electrical connection with the field plate and the collector contact is in electrical connection with the collector.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: April 26, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Renata A. Camillo-Castillo, Vibhor Jain, Marwan H. Khater, Santosh Sharma
  • Publication number: 20150137133
    Abstract: A method of forming a heavily-doped silicon layer on a more lightly-doped silicon substrate including the steps of depositing a heavily-doped amorphous silicon layer; depositing a silicon nitride layer; and heating the amorphous silicon layer to a temperature higher than or equal to the melting temperature of silicon.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 21, 2015
    Applicants: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Michel Marty, Francois Roy
  • Patent number: 9035429
    Abstract: There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing liquid at least once, and each step of polishing with the polishing liquid employs a basic polishing liquid or an acidic polishing liquid as the polishing liquid. The step of polishing with the basic or acidic polishing liquid allows removal of impurity such as abrasive grains remaining on the surface of the group III nitride crystal after it is polished with the slurry containing the abrasive grains.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: May 19, 2015
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takayuki Nishiura, Keiji Ishibashi
  • Patent number: 9035311
    Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Tae-Hoon Yang, Jin-Wook Seo, Soo-Beom Jo, Dong-Hyun Lee, Kil-Won Lee, Maxim Lisachenko, Yun-Mo Chung, Bo-Kyung Choi, Jong-Ryuk Park, Ki-Yong Lee
  • Publication number: 20150108490
    Abstract: A polycrystalline silicon wafer produced based on a melting method and having an outer diameter of 450 mm or more, wherein a depth of scratches on the polycrystalline silicon wafer is 10 ?m or less. A polycrystalline silicon wafer produced based on a melting method and having an outer diameter of 450 mm or more, wherein a maximum number of scratches having a width of 40 ?m or more and 100 ?m or less and a depth of more than 10 ?m and 40 ?m or less formed on the polycrystalline silicon wafer is one or less per section when the overall polycrystalline silicon wafer is divided into 100 mm-square sections, and a depth of remaining scratches is 10 ?m or less. Provided is a large polycrystalline silicon wafer, particularly a silicon wafer having a wafer size in which the outer diameter is 450 mm or more, in which a small number of scratches are generated on the wafer surface and which has mechanical properties similar to those of a monocrystalline silicon wafer.
    Type: Application
    Filed: February 20, 2013
    Publication date: April 23, 2015
    Inventors: Hiroshi Takamura, Ryo Suzuki
  • Publication number: 20150076504
    Abstract: The present disclosure relates to a new generation of laser-crystallization approaches that can crystallize Si films for large displays at drastically increased effective crystallization rates. The particular scheme presented in this aspect of the disclosure is referred to as the advanced excimer-laser annealing (AELA) method, and it can be readily configured for manufacturing large OLED TVs using various available and proven technical components. As in ELA, it is mostly a partial-/near-complete-melting-regime-based crystallization approach that can, however, eventually achieve greater than one order of magnitude increase in the effective rate of crystallization than that of the conventional ELA technique utilizing the same laser source.
    Type: Application
    Filed: March 14, 2013
    Publication date: March 19, 2015
    Inventor: James S. Im
  • Patent number: 8981379
    Abstract: It is an object to provide a method of manufacturing a crystalline silicon device and a semiconductor device in which formation of cracks in a substrate, a base protective film, and a crystalline silicon film can be suppressed. First, a layer including a semiconductor film is formed over a substrate, and is heated. A thermal expansion coefficient of the substrate is 6×10?7/° C. to 38×10?7/° C., preferably 6×10?7/° C. to 31.8×10?7/° C. Next, the layer including the semiconductor film is irradiated with a laser beam to crystallize the semiconductor film so as to form a crystalline semiconductor film. Total stress of the layer including the semiconductor film is ?500 N/m to +50 N/m, preferably ?150 N/m to 0 N/m after the heating step.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Hidekazu Miyairi, Fumito Isaka, Yasuhiro Jinbo, Junya Maruyama
  • Patent number: 8963124
    Abstract: At least first and second Si1-xGex (0?x?1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0?x?1) layers. A lattice constant of the first Si1-xGex (0?x?1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second Si1-xGex (0?x?1) layer is matched with a lattice constant of the second material layer.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Masanobu Miyao, Hiroshi Nakashima, Taizoh Sadoh, Ichiro Mizushima, Masaki Yoshimaru
  • Patent number: 8946062
    Abstract: A method of manufacturing a polycrystalline silicon film includes: depositing a catalyst layer including nickel and depositing nickel nanoparticles on a substrate; exposing the catalyst layer and the nanoparticles to at least silane gas; and heat treating the substrate coated with the catalyst layer and the nanoparticles during at least part of the exposing to silane gas in growing a silicon based film on the substrate.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Guardian Industries Corp.
    Inventors: Vijayen S. Veerasamy, Martin D. Bracamonte
  • Patent number: 8890297
    Abstract: A light emitting device package according to embodiments comprises: a package body; a lead frame on the package body; a light emitting device supported by the package body and electrically connected with the lead frame; a filling material surrounding the light emitting device; and a phosphor layer comprising phosphors on the filling material.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: November 18, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Yu Ho Won, Geun Ho Kim
  • Patent number: 8889569
    Abstract: The disclosed systems and method for non-periodic pulse sequential lateral solidification relate to processing a thin film. The method for processing a thin film, while advancing a thin film in a selected direction, includes irradiating a first region of the thin film with a first laser pulse and a second laser pulse and irradiating a second region of the thin film with a third laser pulse and a fourth laser pulse, wherein the time interval between the first laser pulse and the second laser pulse is less than half the time interval between the first laser pulse and the third laser pulse. In some embodiments, each pulse provides a shaped beam and has a fluence that is sufficient to melt the thin film throughout its thickness to form molten zones that laterally crystallize upon cooling. In some embodiments, the first and second regions are adjacent to each other. In some embodiments, the first and second regions are spaced a distance apart.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: November 18, 2014
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: James S. Im, Ui-Jin Chung, Alexander B. Limanov, Paul C. Van Der Wilt
  • Publication number: 20140332818
    Abstract: A low temperature polysilicon film and a manufacturing method thereof, a thin film transistor and a manufacturing method thereof and a display panel are provided. The manufacturing method of the low temperature polysilicon film includes crystallizing a nano-silicon thin film to form the low temperature polysilicon film.
    Type: Application
    Filed: June 7, 2013
    Publication date: November 13, 2014
    Inventor: Zhen Liu
  • Patent number: 8884304
    Abstract: A thin film transistor array substrate includes a substrate, a plurality of poly-silicon islands and a plurality of gates. The substrate has a display region, a gate driver region and a source driver region. Each poly-silicon island disposed on the substrate has a source region, a drain region and a channel region disposed therebetween. The poly-silicon islands include several first poly-silicon islands and several second poly-silicon islands. The first poly-silicon islands having main grain boundaries and sub grain boundaries are only disposed within the display region and the gate driver region. The main grain boundaries of the first poly-silicon islands are only disposed within the source regions and/or the drain regions. The second poly-silicon islands are disposed in the source driver region. Grain sizes of the first poly-silicon islands are substantially different from those of the second poly-silicon islands. Gates corresponding to the channel regions are disposed on the substrate.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: November 11, 2014
    Assignee: Au Optronics Corporation
    Inventors: Ming-Wei Sun, Chih-Wei Chao
  • Publication number: 20140319468
    Abstract: Systems including and methods for forming a backplane for an electronic display are presented. The backplane includes interlaced crystallized regions, and the interlaced crystallized regions include at least a left column of crystallized regions and a right column of crystallized regions. The left and right columns include rows of crystallized regions with gaps disposed between each of the rows. Furthermore, each crystallized region in the left column extends into a corresponding gap in the right column, and each crystallized region in the right column extends into a corresponding gap in the left column.
    Type: Application
    Filed: April 25, 2013
    Publication date: October 30, 2014
    Applicant: APPLE INC.
    Inventors: Yu Cheng Chen, Hiroshi Osawa, Shih Chang Chang
  • Patent number: 8860037
    Abstract: A thin-film transistor device includes a gate electrode formed above a substrate, a gate insulating film formed on the gate electrode, a crystalline silicon thin film that is formed above the gate insulating film and has a channel region, an amorphous silicon thin film formed on the crystalline silicon thin film, and a source electrode and a drain electrode that are formed above the channel region, and the crystalline silicon thin film has a half-width of a Raman band corresponding to a phonon mode specific to the crystalline silicon thin film of 5.0 or more and less than 6.0 cm?1, and an average crystal grain size of about 50 nm or more and 300 nm or less.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: October 14, 2014
    Assignee: Panasonic Corporation
    Inventors: Takahiro Kawashima, Tomohiko Oda, Hikaru Nishitani
  • Patent number: 8859346
    Abstract: A method for manufacturing array substrate with embedded photovoltaic cell includes: providing a substrate; forming a buffer layer on the substrate; forming an amorphous silicon layer on the buffer layer; converting the amorphous silicon layer into a polysilicon layer; forming a pattern on the polysilicon layer; forming a first photoresist pattern on the polysilicon layer and injecting N+ ions; forming a gate insulation layer on the polysilicon layer; forming a second photoresist pattern on the gate insulation layer and injecting N? ions; forming a third photoresist pattern on the gate insulation layer and injecting P+ ions; forming a metal layer on the gate insulation layer so as to form a gate terminal; forming a hydrogenated insulation layer on the metal layer; forming a first ditch in the first insulation layer; and forming a second metal layer on the first insulation layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: October 14, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Xindi Zhang
  • Publication number: 20140264345
    Abstract: The present disclosure relates a method to mitigate wafer warpage in advanced technology manufacturing processes due to crystallization of one or more amorphous layers with asymmetrical front-surface and back-surface layer thicknesses. After deposition of one or more layers of amorphous material on a front-surface and a back-surface of the wafer in a furnace tool, the front-surface layers are patterned which thins a front layer thickness. Downstream thermal processing performed at a temperature which exceeds a crystallization threshold of the amorphous material will result in asymmetric stress between the front and back surfaces due to the asymmetrical layer thicknesses. To mitigate this effect, the amount of warpage as a function of the difference in asymmetrical layer thickness may be determined such that a front-surface deposition tool may be utilized in conjunction with the furnace tool to reduce the difference in front-surface and back-surface layer thicknesses. Other methods are also disclosed.
    Type: Application
    Filed: July 8, 2013
    Publication date: September 18, 2014
    Inventors: Chun Hsiung Tsai, Shiang-Rung Tsai
  • Patent number: 8822991
    Abstract: It is an object to reduce characteristic variation among transistors and reduce contact resistance between an oxide semiconductor layer and a source electrode layer and a drain electrode layer, in a transistor where the oxide semiconductor layer is used as a channel layer. In a transistor where an oxide semiconductor is used as a channel layer, at least an amorphous structure is included in a region of an oxide semiconductor layer between a source electrode layer and a drain electrode layer, where a channel is to be formed, and a crystal structure is included in a region of the oxide semiconductor layer which is electrically connected to an external portion such as the source electrode layer and the drain electrode layer.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Junichiro Sakata
  • Patent number: 8816351
    Abstract: A laser annealing method includes forming a nitrogen-doped layer on a semiconductor layer, the nitrogen-doped layer having a nitrogen concentration of at least 3×1020 atoms/cc, irradiating a first area of the nitrogen-doped layer in a low oxygen environment with a laser beam and irradiating a second area of the nitrogen-doped layer in a low oxygen environment with a laser beam, a part of the second area overlapping with the first area.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: August 26, 2014
    Assignee: Japan Display Inc.
    Inventors: Kian Kiat Lim, Atsushi Nakamura, Kai Pheng Tan, Eng Soon Lim, Poh Ling Fu, Takaaki Kamimura
  • Patent number: 8809098
    Abstract: Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor also includes a radiation-detection device that is formed in the substrate. The radiation-detection device is operable to detect a radiation wave that enters the substrate through the back side. The image sensor further includes a recrystallized silicon layer. The recrystallized silicon layer is formed on the back side of the substrate. The recrystallized silicon layer has different photoluminescence intensity than the substrate.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Yeur-Luen Tu, Jen-Cheng Liu, Keng-Yu Chou, Chung Chien Wang
  • Patent number: 8802580
    Abstract: Crystallization of thin films using pulsed irradiation The method includes continuously irradiating a film having an x-axis and a y-axis, in a first scan in the x-direction of the film with a plurality of line beam laser pulses to form a first set of irradiated regions, translating the film a distance in the y-direction of the film, wherein the distance is less than the length of the line beam, and continuously irradiating the film in a second scan in the negative x-direction of the film with a sequence of line beam laser pulses to form a second set of irradiated regions, wherein each of the second set of irradiated regions overlaps with a portion of the first set of irradiated regions, and wherein each of the first and the second set of irradiated regions upon cooling forms one or more crystallized regions.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: August 12, 2014
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James S. Im
  • Patent number: 8796687
    Abstract: A method of treating a sheet of semiconducting material comprises forming a sinterable first layer over each major surface of a sheet of semiconducting material, forming a second layer over each of the first layers to form a particle-coated semiconductor sheet, placing the particle-coated sheet between end members, heating the particle-coated sheet to a temperature effective to at least partially sinter the first layer and at least partially melt the semiconducting material, and cooling the particle-coated sheet to solidify the semiconducting material and form a treated sheet of semiconducting material.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: August 5, 2014
    Assignee: Corning Incorporated
    Inventors: Glen Bennett Cook, Prantik Mazumder, Mallanagouda Dyamanagouda Patil, Lili Tian, Natesan Venkataraman
  • Publication number: 20140209156
    Abstract: The invention relates to a novel silicon-based, single-stage solar cell which, instead of converting light in a bulk semiconductor material, generates electrical energy within a very thin quantum structure that is deposited. The layer sequence itself consists of a three-fold hetero structure as an absorber, which is embedded into the space charge region of a pn-junction and is based on quantummechanical effects. Therein, the layer is preferably deposited by a CVD or the like method. High efficiencies of above 30% were initially measured on small samples on silicon.
    Type: Application
    Filed: December 23, 2011
    Publication date: July 31, 2014
    Inventor: Andreas Paul Schüppen
  • Patent number: 8785938
    Abstract: A method for forming a polycrystalline film, a polycrystalline film formed by the method and a thin film transistor fabricated from the polycrystalline film are provided. The method comprises the steps of: providing a substrate; forming a thermal conductor layer on the substrate; etching the thermal conductor layer until the substrate is exposed to form a thermal conductor pattern; forming a seed layer on the thermal conductor layer and the substrate; etching the seed layer to form seed crystals on both sidewalls of the thermal conductor; forming an amorphous layer on the substrate, the thermal conductor layer and the seed crystals; etching the amorphous layer; and recrystallizing the amorphous layer to form a polycrystalline layer.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: July 22, 2014
    Assignee: Tsinghua University
    Inventors: Lianfeng Zhao, Renrong Liang, Mei Zhao, Jing Wang, Jun Xu
  • Patent number: 8778753
    Abstract: A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinho Do, Hajin Lim, WeonHong Kim, Kyungil Hong, Moonkyun Song
  • Patent number: 8759205
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device, wherein an amorphous semiconductor film comprising a microcrystal is annealed using a microwave, to crystallize the amorphous semiconductor film comprising the microcrystal using the microcrystal as a nucleus.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonori Aoyama, Yusuke Oshiki, Kiyotaka Miyano
  • Patent number: 8754418
    Abstract: Disclosed is a semiconductor device 100A that has first lightly doped drain regions 31A1 and 32A1 between a source region 34A1 and a channel region 33A1 of a first conductive-type driver circuit TFT 10A1 and/or between a drain region 35A1 and the channel region 33A1 of the first conductive-type driver circuit TFT 10A1, and second lightly doped drain regions 31C and 32C between a source region 34C and a channel region 33C of a first conductive-type pixel TFT 10C and/or between a drain region 35C and the channel region 33C of the first conductive-type pixel TFT 10C, in which the first lightly doped drain regions 31A1 and 32A1 have first conductive-type impurities n1 at a first impurity concentration C1, and the second lightly doped drain regions 31C and 32C have first conductive-type impurities n1 at the first impurity concentration C1 and second conductive-type impurities p2 at a second impurity concentration C2.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: June 17, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazushige Hotta
  • Publication number: 20140159047
    Abstract: The present invention provides a manufacturing process of oxide insulating layer and flexible structure of LTPS-TFT display. The manufacturing process firstly provides a substrate, which is a soft material sheet; and then an a-Si layer is formed on the substrate, and oxygen ion implantation process of a certain depth is conducted onto the a-Si layer; finally, ELA process is conducted to transform a-Si layer into a Poly-Si layer and an oxide insulating layer; of which the oxide insulating layer is a silica insulating layer and located within the Poly-Si layer for subsequently producing LTPS-TFT; the structure comprises of a substrate, Poly-Si layer and oxide insulating layer within the Poly-Si layer.
    Type: Application
    Filed: December 7, 2012
    Publication date: June 12, 2014
    Inventors: Hao WANG, Wen-Shiang Liao, Yue-Gie Liaw
  • Publication number: 20140138696
    Abstract: A method of manufacturing a polycrystalline silicon film includes: depositing a catalyst layer including nickel and depositing nickel nanoparticles on a substrate; exposing the catalyst layer and the nanoparticles to at least silane gas; and heat treating the substrate coated with the catalyst layer and the nanoparticles during at least part of the exposing to silane gas in growing a silicon based film on the substrate.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: GUARDIAN INDUSTRIES CORP.
    Inventors: Vijayen S. VEERASAMY, Martin D. BRACAMONTE
  • Patent number: 8702865
    Abstract: Affords AlxGa1-xN crystal growth methods, as well as AlxGa1-xN crystal substrates, wherein bulk, low-dislocation-density crystals are obtained. The AlxGa1-xN crystal (0<x?1) growth method is a method of growing, by a vapor-phase technique, an AlxGa1-xN crystal (10), characterized by forming, in the growing of the crystal, at least one pit (10p) having a plurality of facets (12) on the major growth plane (11) of the AlxGa1-xN crystal (10), and growing the AlxGa1-xN crystal (10) with the at least one pit (10p) being present, to reduce dislocations in the AlxGa1-xN crystal (10).
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: April 22, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Michimasa Miyanaga, Naho Mizuhara, Hideaki Nakahata
  • Patent number: 8704239
    Abstract: Disclosed is a novel method for group III polarity growth on a sapphire substrate. Specifically disclosed is a method for producing a laminate wherein a group III nitride single crystal layer is laminated on a sapphire substrate by an MOCVD method.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: April 22, 2014
    Assignee: Tokuyama Corporation
    Inventors: Toru Kinoshita, Kazuya Takada
  • Patent number: 8686393
    Abstract: An integrated circuit device may include a semiconductor substrate including an active region and a transistor in the active region. The transistor may include first and second spaced apart source/drain regions in the active region of the semiconductor substrate, and a semiconductor channel region between the first and second source/drain regions. The semiconductor channel region may include a plurality of channel trenches therein between the first and second source/drain regions. A gate insulating layer may be provided on the channel region including sidewalls of the plurality of channel trenches, and a gate electrode may be provided on the gate insulating layer so that the gate insulating layer is between the gate electrode and the semiconductor channel region including the plurality of channel trenches. Related methods are also discussed.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jihyung Yu, Daewon Ha, Song yi Kim
  • Patent number: 8614495
    Abstract: Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor also includes a radiation-detection device that is formed in the substrate. The radiation-detection device is operable to detect a radiation wave that enters the substrate through the back side. The image sensor further includes a recrystallized silicon layer. The recrystalized silicon layer is formed on the back side of the substrate. The recrystalized silicon layer has different photoluminescence intensity than the substrate.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: December 24, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Yeur-Luen Tu, Jen-Cheng Liu, Keng-Yu Chou, Chung Chien Wang
  • Patent number: 8610255
    Abstract: A light emitting device package according to embodiments comprises: a package body; a lead frame on the package body; a light emitting device supported by the package body and electrically connected with the lead frame; a filling material surrounding the light emitting device; and a phosphor layer comprising phosphors on the filling material.
    Type: Grant
    Filed: July 4, 2008
    Date of Patent: December 17, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventors: Yu Ho Won, Geun Ho Kim
  • Patent number: 8598050
    Abstract: Disclosed are a laser annealing method and apparatus capable of forming a crystalline semiconductor thin film on the entire surface of a substrate without sacrificing the uniformity of crystallinity in a seam portion in a long-axis direction of laser light, the crystalline semiconductor thin film having good properties and high uniformity to an extent that the seam portion is not visually recognizable. During the irradiation of a linear beam, portions corresponding to the edges of the linear beam are shielded by a mask 10 which is disposed on the optical path of a laser light 2, and the mask 10 is operated so that the amount of shielding is periodically increased and decreased.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: December 3, 2013
    Assignee: IHI Corporation
    Inventors: Norihito Kawaguchi, Ryusuke Kawakami, Kenichiro Nishida, Miyuki Masaki, Masaru Morita
  • Publication number: 20130277677
    Abstract: A method for forming a polycrystalline film, a polycrystalline film formed by the method and a thin film transistor fabricated from the polycrystalline film are provided. The method comprises the steps of: providing a substrate; forming a thermal conductor layer on the substrate; etching the thermal conductor layer until the substrate is exposed to form a thermal conductor pattern; forming a seed layer on the thermal conductor layer and the substrate; etching the seed layer to form seed crystals on both sidewalls of the thermal conductor; forming an amorphous layer on the substrate, the thermal conductor layer and the seed crystals; etching the amorphous layer; and recrystallizing the amorphous layer to form a polycrystalline layer.
    Type: Application
    Filed: August 2, 2012
    Publication date: October 24, 2013
    Applicant: TSINGHUA UNIVERSITY
    Inventors: Lianfeng Zhao, Renrong Liang, Mei Zhao, Jing Wang, Jun Xu
  • Publication number: 20130264677
    Abstract: At least three electrically conducting blocks are disposed within an isolating region; and at least two of them are mutually separated and capacitively coupled by a part of the isolating region. At least two of them, being semiconductor, have opposite types of conductivity or identical types of conductivity, but with different concentrations of dopants, and these are in mutual contact by one of their sides. The mutual arrangement of these blocks within the isolating region, their type of conductivity and their concentration of dopants form at least one electronic module. Some of the blocks define input and output blocks.
    Type: Application
    Filed: April 9, 2013
    Publication date: October 10, 2013
    Applicant: STMICROELECTRONICS SA
    Inventors: Philippe GALY, Jean JIMENEZ
  • Publication number: 20130240892
    Abstract: The present invention relates to a process for conversion of semiconductor layers, especially for conversion of amorphous to crystalline silicon layers, in which the conversion is effected by treating the semiconductor layer with a plasma which is generated by a plasma source equipped with a plasma nozzle (1). The present invention further relates to semiconductor layers produced by the process, to electronic and optoelectronic products comprising such semiconductor layers, and to a plasma source for performance of the process according to the invention.
    Type: Application
    Filed: November 10, 2011
    Publication date: September 19, 2013
    Applicant: EVONIK DEGUSSA GmbH
    Inventors: Patrik Stenner, Matthias Patz, Michael Coelle, Stephan Wieber
  • Patent number: 8530901
    Abstract: A method for fabricating a thin film transistor and a thin film transistor includes a polycrystalline silicon layer formed by irradiating an amorphous silicon layer with a laser beam through an organic layer formed on the amorphous silicon layer and removing the organic layer.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: September 10, 2013
    Assignee: LG Display Co., Ltd.
    Inventor: Jae Bum Park
  • Patent number: 8530895
    Abstract: A semiconductor component includes a thinned semiconductor substrate having a back side and a circuit side containing integrated circuits and associated circuitry. The semiconductor component also includes at least one lasered feature on the back side configured to provide selected electrical or physical characteristics for the substrate. The lasered feature can cover the entire back side or only selected areas of the back side, and can be configured to change electrical properties, mechanical properties or gettering properties of the substrate.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: September 10, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim Corbett
  • Patent number: 8530290
    Abstract: A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: September 10, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Tae-hoon Yang, Jin-Wook Seo, Sei-Hwan Jung, Ki-Yong Lee
  • Publication number: 20130200386
    Abstract: In one aspect, crystallization of multiple layers of amorphous materials is disclosed. In one embodiment, multiple layers of amorphous materials such as amorphous silicon, silicon carbide, and/or germanium are deposited using deposition methods such as PECVD or sputtering. A layer of metal such as aluminum is deposited on the surface of the deposited amorphous materials using sputtering or evaporation, and the structure is annealed in a hydrogen environment. The structure is contained on a semiconductor substrate, glass, a flexible metal/organic film, or other type of substrate.
    Type: Application
    Filed: June 8, 2011
    Publication date: August 8, 2013
    Applicants: SILICON SOLAR SOLUTIONS, LLC, BOARD OF TRUSTEES OF THE UNIVERSITY OF ARKANSAS
    Inventors: Douglas Arthur Hutchings, Seth Daniel Shumate, Hameed Naseem, Khalil Hashim Sharif, Hafeezuddin Mohammed
  • Patent number: 8487316
    Abstract: An integrated semiconductor substrate structure is disclosed. In one aspect, the structure includes a substrate, a GaN-heterostructure and a semiconductor substrate layer. The GaN heterostructure is present in a first device area for definition of GaN-based devices, and is covered at least partially with a protection layer. The semiconductor substrate layer is present in a second device area for definition of CMOS devices. At least one of the GaN heterostructure and the semiconductor substrate layer is provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: July 16, 2013
    Assignee: IMEC
    Inventors: Kai Cheng, Stefan Degroote
  • Publication number: 20130146884
    Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include depositing a first amorphous film having a first impurity, depositing a third amorphous lower-layer film on the first amorphous film, forming microcrystals on the third amorphous lower-layer film, depositing a third amorphous upper-layer film on the third amorphous lower-layer film to cover the microcrystals, depositing a second amorphous film having a second impurity on the third amorphous upper-layer film, and radiating microwaves to crystallize the third amorphous lower-layer film and the third amorphous upper-layer film to form a third crystal layer, and crystallize the first amorphous film and the second amorphous film to form a first crystal layer and a second crystal layer.
    Type: Application
    Filed: February 12, 2013
    Publication date: June 13, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kabushiki Kaisha Toshiba
  • Patent number: 8461595
    Abstract: A semiconductor apparatus having a substrate and a laminate structure formed on the substrate, the laminate structure including an insulating film made of a metal oxide and a semiconductor thin film, both the insulating film and the semiconductor thin film being crystallized.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: June 11, 2013
    Assignee: Sony Corporation
    Inventors: Naoki Hayashi, Toshiaki Arai
  • Patent number: 8450724
    Abstract: A device is provided by use of a helical substituted polyacetylene. The device comprises a structure comprised of a helical substituted polyacetylene having a helical main chain, and a pair of electrodes for applying a voltage or electric current to the structure, wherein the molecule of the helical substituted polyacetylene has a length larger than the distance between the pair of the electrodes.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: May 28, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeyuki Sone, Akira Kuriyama, Koji Yano, Otto Albrecht, Masayoshi Tabata
  • Patent number: 8450743
    Abstract: Regions 106 which can be regarded as being monocrystalline are formed locally by irradiating with laser light, and at least the channel-forming region 112 is constructed using these regions. With thin-film transistors which have such a construction it is possible to obtain characteristics which are similar to those which employ monocrystals. Further, by connecting in parallel a plurality of such thin-film transistors it is possible to obtain characteristics which are effectively equivalent to those of a monocrystalline thin-film transistor in which the channel width has been increased.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: May 28, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto