Recrystallized Semiconductor Material Patents (Class 257/75)
  • Publication number: 20090283766
    Abstract: Embodiments in accordance with the present invention relate to the fabrication of thin (>1 ?m) polycrystalline, nanocrystalline, or amorphous silicon films on a substrate. Particular embodiments utilize liquid sources of silane, including but not limited to cyclohexasilane (CHS), cyclopentasilane (CPS) or related derivatives of these compounds. In one embodiment, the silane is applied in liquid form contained by the use of a series of raised walls. Subsequent polymerization results in the material being a solid form. In other embodiments, the silane is applied as a liquid which is then frozen, with subsequent localized melting allowing polymerization to convert the material into a stable solid form. Embodiments of the present invention are particularly suited for forming thick (>10 ?m) silicon films needed to achieve light absorption efficiencies deemed acceptable for thin film photovoltaic devices.
    Type: Application
    Filed: May 12, 2009
    Publication date: November 19, 2009
    Applicant: Silexos, Inc.
    Inventor: Eric Sirkin
  • Patent number: 7612379
    Abstract: An image display system has a multi-gate thin film transistor (TFT) disposed on a transparent substrate. The multi-gate TFT includes a silicon film layer, a first electrode and a reflecting layer. The silicon film layer is formed on the transparent substrate and has a first crystallization zone and a second crystallization zone, which are not adjacent to each other. A grain size of the first crystallization zone is smaller than a grain size of the second crystallization zone. The first electrode corresponding to the first crystallization zone is disposed on the silicon film layer. The reflecting layer corresponding to the second crystallization zone is disposed on the transparent substrate. The silicon film layer is disposed on the transparent substrate and the reflecting layer.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: November 3, 2009
    Assignee: TPO Displays Corp.
    Inventors: Yoshihiro Morimoto, Ryan Lee, Hanson Liu, Fengyi Chen
  • Publication number: 20090261344
    Abstract: A method for making a crystalline wafer, in which an interface layer is associated with a support substrate. A first layer is associated with the interface layer in a strained state. The interface layer is melted sufficiently to substantially uncouple the first layer from the support substrate to relax the first layer from the strained to state to a relaxed state. The interface material is solidified with the first layer in the relaxed state to obtain a first wafer.
    Type: Application
    Filed: June 23, 2009
    Publication date: October 22, 2009
    Inventor: George K. Celler
  • Publication number: 20090256146
    Abstract: Method of producing a semiconductor device, comprising: a) providing a semiconductor substrate, b) providing an insulating layer on a top surface of the semiconductor substrate, c) making an amorphous layer in a top layer of said semiconductor substrate by a suitable implant, d) implanting a dopant into said semiconductor substrate through said insulating layer to provide said amorphous layer with a predetermined doping profile, said implant being performed such that said doping profile has a peak value located within said insulating layer, e) applying a solid phase epitaxial regrowth action to regrow said amorphous layer and activate said dopant.
    Type: Application
    Filed: December 10, 2004
    Publication date: October 15, 2009
    Applicant: KONINKLIJKE PHILIPS ELECTRONIC, N.V.
    Inventor: Bartlomiej J. Pawlak
  • Publication number: 20090242896
    Abstract: A microstructure and a semiconductor element which are included in a micromachine have been generally formed in different steps. It is an object to provide a method for manufacturing a micromachine in which a microstructure and a semiconductor element are formed over one insulating substrate. A feature of the invention is a micromachine including a movable layer containing polycrystalline silicon which is thermally crystallized or crystallized by a laser using metal and a space below or above the layer. Such polycrystalline silicon has high strength and is formed on an insulating surface, so that it is used as a microstructure and used for forming a semiconductor element. Accordingly, a semiconductor device in which a microstructure and a semiconductor element are formed over one insulating substrate can be formed.
    Type: Application
    Filed: June 11, 2009
    Publication date: October 1, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Konami Izumi, Mayumi Yamaguchi
  • Publication number: 20090218577
    Abstract: Under one aspect, a method of processing a film includes defining a plurality of spaced-apart regions to be crystallized within a film, the film being disposed on a substrate and capable of laser-induced melting; generating a sequence of laser pulses having a fluence that is sufficient to melt the film throughout its thickness in an irradiated region, each pulse forming a line beam having a length and a width; continuously scanning the film in a first scan with a sequence of laser pulses at a velocity selected such that each pulse irradiates and melts a first portion of a corresponding spaced-apart region, wherein the first portion upon cooling forms one or more laterally grown crystals; and continuously scanning the film in a second time with a sequence of laser pulses at a velocity selected such that each pulse irradiates and melts a second portion of a corresponding spaced-apart region, wherein the first and second portions in each spaced-apart region partially overlap, and wherein the second portion upon
    Type: Application
    Filed: August 16, 2006
    Publication date: September 3, 2009
    Inventor: James S. Im
  • Patent number: 7576361
    Abstract: Imaging devices having reduced image artifacts are disclosed. The image artifacts in the imaging devices are reduced by redirecting, absorbing or scattering IR radiation that passes through the imaging device substrate away from dark pixels.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: August 18, 2009
    Assignee: Aptina Imaging Corporation
    Inventors: Gennadiy A. Agranov, Igor Karasev
  • Patent number: 7557375
    Abstract: The present invention provides methods of manufacturing of silicon in substantially crystalline form out of amorphous silicon.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: July 7, 2009
    Assignee: California Institute of Technology
    Inventors: Christine E. Richardson, Harry A. Atwater
  • Publication number: 20090166642
    Abstract: There are provided a higher-performance compound semiconductor epitaxial substrate having improved electron mobility characteristics and its production method. The compound semiconductor epitaxial substrate includes a channel layer in which electrons travel and an epitaxial layer on each of a front side and a back side of the channel layer, wherein a total p-type carrier concentration A (/cm2) per unit area in the epitaxial layer on the back side of the channel layer and a total p-type carrier concentration B (/cm2) per unit area in the epitaxial layer on the front side of the channel layer satisfy the following expression (1): 0<A/B?3.
    Type: Application
    Filed: May 28, 2007
    Publication date: July 2, 2009
    Applicant: SUMITOMO CHEMICAL COMPANY LIMITED
    Inventor: Tsuyoshi Nakano
  • Patent number: 7553778
    Abstract: A method for producing a semiconductor device includes irradiating an amorphous semiconductor film on an insulating material with a pulsed laser beam having a rectangular irradiation area, while scanning in a direction intersecting a longitudinal direction of the irradiation area, thereby forming a first polycrystalline semiconductor film, and irradiating a part of the amorphous semiconductor film with the laser beam, while scanning in a longitudinal direction intersecting the irradiation area, the part superposing the first polycrystalline semiconductor film and being adjacent to the first polycrystalline semiconductor film, thereby forming a second polycrystalline semiconductor film. The laser beam has a wavelength in a range from 390 nm to 640 nm, and the amorphous semiconductor film has a thickness in a range from 60 nm to 100 nm.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: June 30, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuyuki Sugahara, Naoki Nakagawa, Atsuhiro Sono, Shinsuke Yura, Kazushi Yamayoshi
  • Patent number: 7547914
    Abstract: The process relates to the production of a layer of a single-crystal first material on a second material. The second material has at least one aperture exposing a surface portion of a single-crystal third material. The process generally includes forming an at least partially crystalline first layer of said first material on said surface portion of the third material. Then, an amorphous or partially crystalline second layer of the first material is formed on the at least partially crystalline first layer of the first material and on one part of the second material that is around said aperture. Finally, the process includes recrystallization annealing of the first material. Thus, it is possible to produce, within one and the same wafer, either transistors on a germanium-on-insulator substrate with transistors on a silicon-on-insulator substrate, or transistors on a germanium-on-insulator substrate with transistors on a silicon substrate.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: June 16, 2009
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Olivier Kermarec, Yves Campidelli, Guillaume Pin
  • Publication number: 20090146146
    Abstract: A semiconductor device includes a substrate that includes a first layer and a recrystallized layer on the first layer. The first layer has a first intrinsic stress and the recrystallized layer has a second intrinsic stress. A transistor is formed in the recrystallized layer. The transistor includes a source region, a drain region, and a charge carrier channel between the source and drain regions. The second intrinsic stress is aligned substantially parallel to the charge carrier channel.
    Type: Application
    Filed: February 9, 2009
    Publication date: June 11, 2009
    Inventors: Roman Knoefler, Armin Tilke
  • Publication number: 20090127560
    Abstract: Example embodiments relate to a poly-crystalline silicon (Si) thin film, a thin film transistor (TFT) formed from a poly-crystalline silicon (Si) thin film and methods of manufacturing the same. The method of manufacturing the poly-crystalline Si thin film includes forming an active layer formed of amorphous Si on a substrate, coating a gold nanorod on the active layer, and irradiating infrared rays onto the gold nanorod to crystallize the active layer.
    Type: Application
    Filed: July 18, 2008
    Publication date: May 21, 2009
    Inventors: Kyung-bae Park, Seon-mi Yoon, Sang-yoon Lee, Jae-young Choi, Hyeon-jin Shin, Myung-kwan Ryu, Tae-sang Kim, Jang-yeon Kwon, Kyung-seok Son, Ji-sim Jung
  • Patent number: 7528056
    Abstract: A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the Si regions have been strained. The inventive method includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polaity (tensile or compressive) of the stress can be controlled by the type and thickness of the stress films.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: May 5, 2009
    Assignee: International Business Machines Corporation
    Inventors: Meikei Ieong, Douglas C. La Tulipe, Jr., Leathen Shi, Anna W. Topol, James Vichiconti, Albert M. Young
  • Patent number: 7528408
    Abstract: To improve the laser annealing process for polycrystallizing amorphous silicon to form silicon thin films having large crystal particle diameters at a high throughput, the present invention is directed to a process of crystallization by irradiation of a semiconductor thin film formed on a substrate with pulsed laser light. The process comprises having a means to shape laser light into a linear beam and a means to periodically and spatially modulate the intensity of pulsed laser in the direction of the long axis of the linear beam by passing through a phase-shifting stripy pattern perpendicular to the long axis, and collectively forming for each shot a polycrystalline film composed of crystals which have grown in a certain direction over the entire region irradiated with the linear beam.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: May 5, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Takeda, Jun Gotou, Masakazu Saito, Makoto Ohkura, Takeshi Satou, Hiroshi Fukuda, Takeo Shiba
  • Patent number: 7521712
    Abstract: A thin film semiconductor device is provided that includes a semiconductor thin film and a gate electrode. The semiconductor thin film has an active region turned into a polycrystalline region through irradiation with an energy beam. The gate electrode is provided to traverse the active region. In a channel part that is the active region overlapping with the gate electrode, a crystalline state is changed cyclically in a channel length direction, and areas each having a substantially same crystalline state traverse the channel part.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: April 21, 2009
    Assignee: Sony Corporation
    Inventors: Akio Machida, Toshio Fujino, Tadahiro Kono
  • Patent number: 7518252
    Abstract: A thin-film semiconductor substrate includes an insulative substrate, an amorphous semiconductor thin film that is formed on the insulative substrate, and a plurality of alignment marks that are located on the semiconductor thin film and are indicative of reference positions for crystallization.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: April 14, 2009
    Assignee: Advanced LCD Technologies Development Center Co., Ltd
    Inventors: Masato Hiramatsu, Yoshinobu Kimura, Hiroyuki Ogawa, Masayuki Jyumonji, Masakiyo Matsumura
  • Publication number: 20090085042
    Abstract: A display device having a thin film semiconductor device including a semiconductor thin film having first and second semiconductor regions formed each into a predetermined shape above an insulative substrate, a conductor fabricated into a predetermined shape to the semiconductor thin film and a dielectric film put between the semiconductor thin film and the conductor, in which the semiconductor thin film is a polycrystal thin film with the crystallization ratio thereof exceeding 90% and the difference of unevenness on the surface of the semiconductor thin film does not exceed 10 nm.
    Type: Application
    Filed: July 29, 2008
    Publication date: April 2, 2009
    Inventors: Toshiyuki Mine, Mitsuharu Tai, Akio Shima
  • Publication number: 20090026465
    Abstract: A method of forming a polysilicon film having smooth surface using a lateral growth and a step-and-repeat laser process. Amorphous silicon formed in a first irradiation region of a substrate is crystallized to form a first polysilicon region by a first laser shot. Then, the substrate is moved a predetermined distance, and irradiated by a second laser shot. The polysilicon region is then recrystallized and locally planarized by subsequent laser shots. After multiple repetitions of the irradiation procedure, the amorphous silicon film formed on a substrate is completely transformed into a polysilicon film. The polysilicon film includes lateral growth crystal grains and nano-trenches formed in parallel on the surface of the polysilicon film. A longitudinal direction of the nano-trenches is substantially perpendicular to a lateral growth direction of the crystal grains.
    Type: Application
    Filed: June 13, 2008
    Publication date: January 29, 2009
    Applicant: AU OPTRONICS CORP.
    Inventors: Chih-Wei Chao, Ming-Wei Sun
  • Patent number: 7482274
    Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ? in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: January 27, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Ono, Hideomi Suzawa
  • Publication number: 20090020763
    Abstract: A method of fabricating a poly silicon layer comprising the following steps is provided. First, a substrate is provided and an amorphous silicon layer is formed on the substrate. A patterned metal layer is formed on the amorphous silicon layer. Next, a pulsed rapid thermal annealing process is performed to form a metal silicide between the patterned metal layer and the amorphous silicon layer, wherein the patterned metal layer and the amorphous silicon layer are adopted for conducting thermal energy to the amorphous silicon layer such that the amorphous silicon layer is converted into a polysilicon layer. Finally, the patterned metal layer is removed. A polysilicon layer formed according to the above-mentioned fabrication method is also provided. The grains of the poly silicon layer are spherical in shape.
    Type: Application
    Filed: September 30, 2008
    Publication date: January 22, 2009
    Applicant: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Chiung-Wei Lin, Sheng-Chi Lee, Yi-Liang Chen, Rui-Cheng Huang, Te-Hua Teng
  • Patent number: 7476895
    Abstract: An n-type diamond epitaxial layer 20 is formed by processing a single-crystalline {100} diamond substrate 10 so as to form a {111} plane, and subsequently by causing diamond to epitaxially grow while n-doping the diamond {111} plane. Further, a combination of the n-type semiconductor diamond, p-type semiconductor diamond, and non-doped diamond, obtained in the above-described way, as well as the use of p-type single-crystalline {100} diamond substrate allow for a pn junction type, a pnp junction type, an npn junction type and a pin junction type semiconductor diamond to be obtained.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: January 13, 2009
    Assignee: Sumitomo Electric Industries., Ltd.
    Inventors: Akihiko Namba, Takahiro Imai, Yoshiki Nishibayashi
  • Patent number: 7453090
    Abstract: A method of manufacturing a semiconductor device includes forming isolation regions, a gate insulator film and gate electrodes, implanting in the silicon substrate with impurity ions, annealing to recover crystallinity of the implanted silicon substrate without diffusing the impurity ions, depositing an interlayer insulator film on the isolation regions, the silicon substrate, and the gate electrodes, and heating the silicon substrate by irradiating a light having a wavelength that the light is absorbed by the silicon substrate without being absorbed by the interlayer insulator film, activating the impurity ions so as to form source and drain regions.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: November 18, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takayuki Ito
  • Patent number: 7427775
    Abstract: The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain areas and crystalline films in source/drain regions. By using an etch which is selective to amorphous silicon, the amorphous material may be removed. This may avoid some problems associated with selective deposition of the doped silicon material.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: September 23, 2008
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Justin K. Brask, Andrew N. Westmeyer, Boyan Boyanov, Nick Lindert
  • Patent number: 7396712
    Abstract: A thin film processing method for processing the thin film by irradiating an optical beam to the thin film. A unit of the irradiation of the optical beam includes a first and a second optical pulse irradiation to the thin film, and the unit of the irradiation is carried out repeatedly to process the thin film. The first and the second optical pulse have pulse waveforms different from each other. Preferably, a unit of the irradiation of the optical beam includes the a first optical pulse irradiated to the thin film and a second optical pulse irradiated to the thin film starting substantially simultaneous with the first optical pulse irradiation. In this case, the relationship between the first and the second optical pulse satisfies (the pulse width of the first optical pulse)<(the optical pulse of the second optical pulse) and (the irradiation intensity of the first optical pulse)?(the irradiation intensity of the second optical pulse).
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: July 8, 2008
    Assignees: NEC Corporation, Sumitomo Heavy Industries, Ltd
    Inventors: Hiroshi Tanabe, Akihiko Taneda
  • Publication number: 20080135850
    Abstract: A process for manufacturing a semiconductor device, provides that a silicide layer is formed, an amorphous semiconductor layer is applied both to the silicide layer and to an open monocrystalline semiconductor region, adjacent to the silicide layer, and during a subsequent temperature treatment, the amorphous semiconductor layer is crystallized proceeding from the open, monocrystalline semiconductor region, acting as a crystallization nucleus, so that the silicide layer is covered at least partially by a crystallized, monocrystalline semiconductor layer.
    Type: Application
    Filed: January 28, 2008
    Publication date: June 12, 2008
    Inventor: Christoph Bromberger
  • Patent number: 7354477
    Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: April 8, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
  • Publication number: 20080061302
    Abstract: A light emitting diode comprises an N-type semiconductor layer comprising a horizontal lattice defect layer, an active layer on the N-type semiconductor layer, and a P-type semiconductor layer on the active layer.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 13, 2008
    Inventor: Dae Sung Kang
  • Patent number: 7335910
    Abstract: An object of the present invention is to provide a thin film transistor having a high mobility and having fewer fluctuations in the mobility or threshold voltage characteristics. A non-single-crystal semiconductor thin film having a thickness of less than 50 nm and disposed on an insulating substrate is irradiated with laser light having an inverse-peak-patterned light intensity distribution to grow crystals unidirectionally in a lateral direction. Thus, band-like crystal grains having a dimension in a crystal growth direction, which is longer than a width, are arranged adjacent to each other in a width direction to form a crystal grain array. A source region and a drain region of a TFT are formed so that a current flows in the crystal growth direction in an area including a plurality of crystal grains of this crystal grain array.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: February 26, 2008
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Tomoya Kato, Masakiyo Matsumura, Yoshiaki Nakazaki
  • Patent number: 7303630
    Abstract: Dotted seeds are implanted in a regular pattern upon an undersubstrate. A GaN crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations from neighboring regions, accumulate the dislocations into pit bottoms, and make closed defect accumulating regions (H) on the seeds. The polycrystalline or slanting orientation single crystal closed defect accumulating regions (H) induce microcracks due to thermal expansion anisotropy. The best one is orientation-inversion single crystal closed defect accumulating regions (H). At an early stage, orientation-inverse protrusions are induced on tall facets and unified with each other above the seeds. Orientation-inverse crystals growing on the unified protrusions become the orientation-inverse single crystal closed defect accumulating regions (H).
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: December 4, 2007
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Takuji Okahisa, Ryu Hirota, Seiji Nakahata, Koji Uematsu
  • Patent number: 7297983
    Abstract: Integrated circuit device comprising a conductive layer and a poly-crystalline silicon layer, wherein the integrated circuit device further comprises an intermediate counter-stress layer. This intermediate counter-stress layer is arranged between the poly-crystalline silicon layer and the conductive layer, and enables stress-reduced crystallization of the poly-crystalline silicon layer. Further, the intermediate counter-stress layer is amorphous at and below a poly-silicon crystallization temperature.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: November 20, 2007
    Assignee: Infineon Technologies AG
    Inventors: Thomas Hecht, Henry Bernhardt, Christian Kapteyn
  • Publication number: 20070264806
    Abstract: Embodiments of a mask for sequential lateral solidification are disclosed herein. In some embodiments, a mask of the present disclosure comprises a transmission region including a first slit column having a plurality of first slits separated from one another by a predetermined interval, and a second slit column having a plurality of second slits separated from one another by a predetermined interval and disposed adjacent to and offset from the first slit column. An irradiated laser beam is substantially completely transmitted through the transmission region. In some embodiments, the mask includes a semi-transmission region including a first opening pattern disposed at least partially between adjacent first slits and having a plurality of first openings formed into a desired shape, and a second opening pattern disposed at least partially between adjacent second slits and having a plurality of second opening formed into a desired shape.
    Type: Application
    Filed: October 5, 2006
    Publication date: November 15, 2007
    Inventor: Cheol Ho Park
  • Patent number: 7279404
    Abstract: A process for fabricating a strained layer of silicon or of a silicon/germanium alloy, includes: a) the formation of a layer (2) of silicon or of a silicon/germanium alloy on a layer (1) of a material having a modifiable lattice parameter; and b) the modification of the lattice parameter.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: October 9, 2007
    Assignee: STMicroelectronics S.A.
    Inventors: Aomar Halimaoui, Daniel Bensahel
  • Publication number: 20070210313
    Abstract: A method for fabricating a thin film transistor and a thin film transistor includes a polycrystalline silicon layer formed by irradiating an amorphous silicon layer with a laser beam through an organic layer formed on the amorphous silicon layer and removing the organic layer.
    Type: Application
    Filed: September 29, 2006
    Publication date: September 13, 2007
    Inventor: Jae Bum Park
  • Publication number: 20070210307
    Abstract: A method for making a structure which may have at least one layer on a supporting substrate. The method includes at least the steps for forming from the supporting substrate an intermediate structure which may have an amorphous layer, a first crystalline layer containing point defects and, a second crystalline layer located immediately underneath the amorphous layer and in the lower portion of the intermediate structure. The method may also include bonding a receiving substrate on the upper face of the intermediate structure and removing the layer of the intermediate structure in which point defects have formed so that amorphous layer forms the upper layer of the intermediate structure. A structure made by such a method may comprise at least one thin layer of an amorphous material on a supporting substrate. The structure may comprise a receiving substrate, a central crystalline layer and an amorphous layer, all of which may lack any EOR type point defect.
    Type: Application
    Filed: August 14, 2006
    Publication date: September 13, 2007
    Inventor: Xavier Hebras
  • Patent number: 7268026
    Abstract: A method of forming a crystal grain for use in a semiconductor manufacturing process, the method including the steps of forming an oxide silicon film on a glass substrate, etching at least one hole at a predetermined location in the oxide silicon film, forming an amorphous silicon film over the oxide silicon film, heating the amorphous silicon film such that a portion of the amorphous silicon film in the at least one hole is in a non-melting state and a substantial remainder of the amorphous silicon film is brought into a melting state, and allowing the amorphous silicon film to cool such that crystal growth is generated using the non-melting state portion as a crystal nucleus.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: September 11, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyuki Shimada
  • Patent number: 7268367
    Abstract: Methods of forming thin film devices with different electrical characteristics on a substrate comprising a driver circuit region and a pixel region. A first and a second polysilicon pattern layers are formed on the driving circuit region and the pixel region of the substrate, respectively. A first ion implantation is performed on the second polysilicon pattern layer using a masking layer covering the first polysilicon pattern layer as an implant mask, such that the first polysilicon pattern layer has an impurity concentration different from the second polysilicon pattern layer. After removal of the masking layer, a gate dielectric layer and a gate are successively formed on each of the first and second polysilicon pattern layers and a source/drain region is subsequently formed in each of the first and second polysilicon pattern layers to define a channel region therein.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: September 11, 2007
    Assignee: AU Optronicscorp.
    Inventors: Wei-Pang Huang, Chun-Huai Li, Yun-Sheng Chen
  • Patent number: 7256109
    Abstract: A high-quality isotropic polycrystalline silicon (poly-Si) and a method for fabricating high quality isotropic poly-Si film are provided. The method includes forming a film of amorphous silicon (a-Si) and using a MISPC process to form poly-Si film in a first area of the a-Si film. The method then anneals a second area, included in the first area, using a Laser-Induced Lateral Growth (LILaC) process. In some aspects, a 2N-shot laser irradiation process is used as the LILaC process. In some aspects, a directional solidification process is used as the LILaC process. In response to using the MISPC film as a precursor film, the method forms low angle grain boundaries in poly-Si in the second area.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: August 14, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Masao Moriguchi, Apostolos T. Voutsas, Mark A. Crowder
  • Patent number: 7247882
    Abstract: There is provided a semiconductor device having TFTs whose thresholds can be controlled. There is provided a semiconductor device including a plurality of TFTs having a back gate electrode, a first gate insulation film, a semiconductor active layer a second gate insulation film and a gate electrode, which are formed on a substrate, wherein an arbitrary voltage is applied to the back gate electrode.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: July 24, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Setsuo Nakajima, Naoya Sakamoto
  • Patent number: 7223665
    Abstract: A method for manufacturing a dielectric thin film capacitor of the present invention includes the steps of coating a liquid raw material on a substrate and performing a first heat treatment to form an adhesive layer, forming a lower electrode on the adhesive layer, coating a liquid raw material on the lower electrode and performing a second heat treatment to form a dielectric thin film by crystallization, forming an upper electrode on the dielectric thin film, and performing a third heat treatment at a temperature higher than those of the first and second heat treatments. The adhesive layer and the dielectric thin film are formed by using materials having the same composition system or using the same material.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: May 29, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yutaka Takeshima, Koki Shibuya
  • Patent number: 7202499
    Abstract: An object of the present invention is to provide a TFT of new structure in which the gate electrode overlaps with the LDD region and a TFT of such structure in which the gate electrode does not overlap with the LDD region. The TFT is made from crystalline semiconductor film and is highly reliable. The TFT of crystalline semiconductor film has the gate electrode formed from a first gate electrode 113 and a second gate electrode in close contact with said first gate electrode and gate insulating film. The LDD is formed by ion doping using said first gate electrode as a mask, and the source-drain region is formed using said second gate electrode as a mask. After that the second gate electrode in the desired region is selectively removed. In this way it is possible to form LDD region which overlaps with the second gate electrode.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: April 10, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Setsuo Nakajima
  • Patent number: 7193240
    Abstract: A mask and its application in sequential lateral solidification (SLS) crystallization of amorphous silicon are provided. The mask includes a light absorptive portion for blocking a laser beam and a plurality of stripe-shaped light transmitting portions for passing the laser beam. Each stripe-shaped light transmitting portion is rectangular-shaped, and each light-transmitting portion includes triangular-shaped or semicircular-shaped edges on both sides. The distance between the adjacent light transmitting portions is less than the width of the light transmitting portion. The width of the light transmitting portions is less than or equal to twice the maximum length of lateral grain growth that is to be grown by sequential lateral solidification (SLS).
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: March 20, 2007
    Assignee: L.G.Philips LCD Co., Ltd.
    Inventor: Yun-Ho Jung
  • Patent number: 7183571
    Abstract: A polycrystalline silicon thin film to be used in display devices, the thin film having adjacent primary grain boundaries that are not parallel to each other, wherein an area surrounded by the primary grain boundaries is larger than 1 ?m2, a fabrication method of the polycrystalline silicon thin film, and a thin film transistor fabricated using the method.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: February 27, 2007
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Ji Yong Park, Hye Hyang Park
  • Patent number: 7176479
    Abstract: A nitride compound semiconductor element having improved characteristics, productivity and yield. A nitride compound semiconductor element includes: a sapphire substrate; a first single crystalline layer of AlN formed on said sapphire substrate; a second single crystalline layer formed on said first single crystalline layer, said second single crystalline layer being made of AlxGa1-xN (0.8?x?0.97) and having a thickness of equal to or more than 0.3 ?m and equal to or less than 6 ?m; and a device structure section of a nitride semiconductor formed on said second single crystalline layer.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: February 13, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuo Ohba
  • Patent number: 7157737
    Abstract: Single-crystal devices and a method for forming semiconductor film single-crystal domains are provided. The method comprises: forming a substrate, such as glass or Si; forming an insulator film overlying the substrate; forming a single-crystal seed overlying the substrate and insulator; forming an amorphous film overlying the seed; annealing the amorphous film; and, forming a single-crystal domain in the film responsive to the single-crystal seed. The annealing technique can be (conventional) laser annealing, a laser induced lateral growth (LiLAC) process, or conventional furnace annealing. In some aspects, forming a single-crystal seed includes forming a nanowire or a self assembled monolayer (SAM). For example, a Si nanowire can be formed having a crystallographic orientation of <110> or <100>. When, the seed has a <100> crystallographic orientation, then an n-type TFT can be formed.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: January 2, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Apostolos T. Voutsas, John W. Hartzell
  • Patent number: 7148507
    Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: December 12, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Shunpei Yamazaki, Koji Dairiki, Hiroshi Shibata, Chiho Kokubo, Tatsuya Arao, Masahiko Hayakawa, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Mai Akiba
  • Patent number: 7148510
    Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: December 12, 2006
    Assignee: Semiconductor Energy Laboratory Co. Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Masahiko Hayakawa, Kiyoshi Kato, Mitsuaki Osame, Takashi Hirosue, Saishi Fujikawa
  • Patent number: 7115905
    Abstract: A semiconductor device has a SALICIDE structure with low leakage currents, while maintaining shallow source and drain regions. A method of manufacturing the semiconductor device includes forming source and drain regions in a first semiconductor layer, the source region and the drain region being separated from each other, forming a gate insulating film between the source region and the drain region on the first semiconductor layer, and forming a gate electrode on the gate insulating film. The method also includes forming a metal silicide layer showing a first compound phase on the source region, the drain region and the gate electrode, and forming a second semiconductor layer on the metal silicide layer showing the first compound phase where the second semiconductor layer is adapted to react with the metal silicide layer.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: October 3, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masakatsu Tsuchiaki
  • Patent number: 7115903
    Abstract: An insulating film having depressions and projections are formed on a substrate. A semiconductor film is formed on the insulating film. Thus, for crystallization by using laser light, a part where stress concentrates is selectively formed in the semiconductor film. More specifically, stripe or rectangular depressions and projections are provided in the semiconductor film. Then, continuous-wave laser light is irradiated along the stripe depressions and projections formed in the semiconductor film or in a direction of a major axis or minor axis of the rectangle.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: October 3, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Koji Dairiki, Hiroshi Shibata, Chiho Kokubo, Tatsuya Arao, Masahiko Hayakawa, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Shunpei Yamazaki, Mai Akiba
  • Patent number: 7112826
    Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. A GaN crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: September 26, 2006
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Takuji Okahisa, Seiji Nakahata, Ryu Hirota, Koji Uematsu