Separating Insulating Layer Is Laminate Or Composite Of Plural Insulating Materials (e.g., Silicon Oxide On Silicon Nitride, Silicon Oxynitride) Patents (Class 257/760)
  • Patent number: 10354918
    Abstract: A contact element structure of a semiconductor device includes an opening positioned in an insulating material layer, the insulating material layer being positioned above a semiconductor substrate, and the opening having an upper sidewall portion, a lower sidewall portion, and a bottom surface portion. An insulating liner portion is positioned within the opening, the insulating liner portion covering the insulating material layer at the upper sidewall portion but not covering the insulating material layer at the lower sidewall portion. A contact liner is positioned within the opening and covers the insulating liner portion, the insulating material layer at the lower sidewall portion, and the insulating material layer at the bottom surface portion, and a conductive material is positioned in the opening and covers the contact liner.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Jim Shih-Chun Liang
  • Patent number: 10340355
    Abstract: A method of forming source/drain contact structures that exhibit low contact resistance and improved electromigration properties is provided. After forming a first contact conductor portion composed of a metal having a high resistance to electromigration, such as, for example, tungsten, at a bottom portion of source/drain contact trench to form direct contact with a source/drain region of a field effect transistor, a second contact conductor portion composed of a highly conductive metal, such as, for example, copper or a copper alloy, is formed over the first contact conductor portion.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Koichi Motoyama, Oscar Van Der Straten
  • Patent number: 10211166
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor circuit layer including a first conductive layer, a second semiconductor circuit layer including a second conductive layer, and a third semiconductor circuit layer between the first semiconductor circuit layer and the second semiconductor circuit layer, the third semiconductor circuit layer including a third conductive layer in contact with the first conductive layer, a fourth conductive layer in contact with the second conductive layer, and a fifth conductive layer in contact with the third conductive layer and electrically connected to the fourth conductive layer. The fifth conductive layer has a width that is narrower than a width of the third conductive layer.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: February 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Kouji Matsuo
  • Patent number: 10157836
    Abstract: A fabrication process including the following steps for making a metal via structure is disclosed. A substrate with at least a metal pad configured thereon is prepared. A first dielectric layer configured on a top surface of the substrate has a first opening exposing a top surface of the metal pad. A patterned first photoresist having a second opening aligned with the first opening is applied on a top surface of the first dielectric layer. A first metal evaporation is performed to form a first adhesive layer conformably distributed on a wall surface of the first opening and on a top surface of the exposed area of the metal pad. A second metal evaporation is performed to form a first metal block. The first photoresist is stripped. The first metal block is flattened to have a top surface coplanar with a top surface of the first dielectric layer.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: December 18, 2018
    Inventor: Dyi-Chung Hu
  • Patent number: 10032712
    Abstract: One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. A first metal region is formed within a first dielectric region. A cap region is formed on the first metal region. A second dielectric region is formed above the cap region and the first dielectric region. A trench opening is formed within the second dielectric region. A via opening is formed through the second dielectric region, the cap region, and within some of the first metal region by over etching. A barrier region is formed within the trench opening and the via opening. A via plug is formed within the via opening and a second metal region is formed within the trench opening. The via plug electrically connects the first metal region to the second metal region and has a tapered profile.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: July 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 9935160
    Abstract: The present invention provides an OLED display device, which includes: a substrate (1), a plurality of pixel zones arranged in an array on the substrate (1), each of the pixel zones comprising a pixel electrode (2), an organic light-emitting layer (3), and a common electrode (4) that are sequentially stacked on the substrate (1), and a pixel separation layer (5) including a plurality of openings, the openings being each delimited and circumferentially surrounded by a pixel separation layer sidewall (51), each of the openings corresponding to one of the pixel zones. The pixel separation layer (5) is formed of an inorganic material.
    Type: Grant
    Filed: May 25, 2015
    Date of Patent: April 3, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaowen Lv, Hejing Zhang
  • Patent number: 9865798
    Abstract: A semiconductor device includes an interconnect layer and a bottom electrode of a resistive memory device. The bottom electrode is coupled to the interconnect layer, and the bottom electrode is comprised of cobalt tungsten phosphorus (CoWP).
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: January 9, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Yu Lu, Junjing Bao, Xia Li, Seung Hyuk Kang
  • Patent number: 9847249
    Abstract: A stack of layers is formed that includes first, second, and third dielectric layers. Contact plugs are then formed extending through the stack. Then a fourth dielectric layer is formed over the stack and contact plugs and trenches are formed through the fourth and third dielectric layers, extending to the second dielectric layer and exposing contact plugs.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: December 19, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yuji Takahashi, Takuya Futase, Noritaka Fukuo, Katsuo Yamada, Tomoyasu Kakegawa
  • Patent number: 9831209
    Abstract: Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: November 28, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takafumi Betsui, Motoo Suwa
  • Patent number: 9793163
    Abstract: Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Florian Gstrein, Richard E. Schenker, Paul A. Nyhus, Charles H. Wallace, Hui Jae Yoo
  • Patent number: 9666433
    Abstract: Carbon-containing patterns are formed on an etch target layer, side surfaces of the carbon-containing patterns are treated by a hydrophilic process, poly-crystalline silicon spacers are formed on the side surfaces of the carbon-containing patterns after the hydrophilic process has been performed, and the etch target layer is patterned using the poly-crystalline silicon spacers as an etch mask.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: May 30, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Badro Im, Yoonchul Cho, Sangyeol Kang, Daehyun Kim, Dongkak Lee, Jun-Noh Lee, Bonghyun Kim, Kongsoo Lee
  • Patent number: 9659872
    Abstract: A step of forming a connecting member configured to electrically connect a first conductive line and a second conductive line includes a phase of perforating a laminate from a first semiconductor wafer to form a plurality of connection holes that reach the second conductive line and a phase of filling the plurality of penetrating connection holes with a conductive material to form conductive sections in contact with the second conductive line.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 23, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hideomi Kumano
  • Patent number: 9589836
    Abstract: One illustrative method disclosed herein includes, among other things, forming a first conductive structure and a second conductive structure that is conductively coupled to the first conductive structure. In this example, forming the second conductive structure includes forming a ruthenium cap layer on and in contact with an upper surface of the first conductive structure, with the ruthenium cap layer in position, forming a liner layer comprising manganese on and in contact with at least the surfaces of the second layer of insulating material, wherein an upper surface of the ruthenium cap layer is substantially free of the liner layer, and forming a bulk ruthenium material on and in contact with the liner layer, wherein a bottom surface of the bulk ruthenium material contacts the upper surface of the ruthenium cap layer.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 7, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Hoon Kim
  • Patent number: 9362207
    Abstract: A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: June 7, 2016
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Kwan-soo Kim, Tae-jong Lee, Kang-sup Shin, Si-bum Kim, Yang-beom Kang, Jong-yeul Jeong
  • Patent number: 9293413
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an insulating material layer over a workpiece, patterning an upper portion of the insulating material layer with a conductive line pattern, and forming a stop layer comprising a metal oxide or a metal nitride over the patterned insulating material layer. A masking material is formed over the stop layer, and the masking material is patterned with a via pattern. The via pattern of the masking material is transferred to a lower portion of the insulating material layer.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Patent number: 9242900
    Abstract: Preparing porous materials includes forming a mixture including a geopolymer resin and a liquid between which a nanoscale (1-1000 nm), microscale (1-1000 m), and/or milliscale (1-10 mm) phase separation occurs. The mixture is solidified (e.g., at an ambient temperature or a relatively low temperature), and a portion (e.g., a majority or a significant majority) of the liquid is removed from the solidified mixture. The liquid can include organic liquids from agricultural, geological, industrial, or household sources. The porous materials have accessible pores with a range of pore sizes including nanoscale pore sizes, microscale pore sizes, milliscale pore sizes, or a combination thereof. The porous material may be treated further to form another material, such as a composite.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: January 26, 2016
    Assignee: ARIZONA BOARD OF REGENTS, A BODY CORPORATE OF THE STATE OF ARIZONA ACTING FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Dong-Kyun Seo, Dinesh Medpelli, Jungmin Seo
  • Patent number: 9209130
    Abstract: Semiconductor devices having a ground shield structure and methods for their formation are provided herein. An exemplary semiconductor device can include a substrate, a ground ring, a ground shield, an electronic device, and/or an insulation layer. The ground ring can be disposed over the substrate. The ground shield can be disposed over the substrate and surrounded by the ground ring. The ground shield can include a plurality of coaxial conductive wirings and a metal wire passing through the plurality of coaxial conductive wirings along a radial direction. The metal wire can be connected to the ground ring. The electronic device can be disposed over the ground shield. The insulation layer can be disposed between the ground shield and the electronic device.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: December 8, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Jenhao Cheng, Xining Wang, Ling Liu
  • Patent number: 9136163
    Abstract: A step of forming a connecting member configured to electrically connect a first conductive line and a second conductive line includes a phase of perforating a laminate from a first semiconductor wafer to form a plurality of connection holes that reach the second conductive line and a phase of filling the plurality of penetrating connection holes with a conductive material to form conductive sections in contact with the second conductive line.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: September 15, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideomi Kumano
  • Patent number: 9076804
    Abstract: A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The first layer includes a via opening and a tapered portion proximate to the via opening. The metal layer is formed over the via opening and the tapered portion of the first layer. The metal layer is substantially free from gaps and voids.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: July 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Patent number: 9054109
    Abstract: A method of producing reduced corrosion interconnect structures and structures thereby formed. A method of producing microelectronic interconnects having reduced corrosion begins with a damascene structure having a first dielectric and a first interconnect. A metal oxide layer is deposited selectively to metal or nonselective over the damascene structure and then thermally treated. The treatment converts the metal oxide over the first dielectric to a metal silicate while the metal oxide over the first interconnect remains as a self-aligned protective layer. When a subsequent dielectric stack is formed and patterned, the protective layer acts as an etch stop, oxidation barrier and ion bombardment protector. The protective layer is then removed from the patterned opening and a second interconnect formed. In a preferred embodiment the metal oxide is a manganese oxide and the metal silicate is a MnSiCOH, the interconnects are substantially copper and the dielectric contains ultra low-k.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Son Nguyen, Vamsi Paruchuri, Tuan A. Vo
  • Patent number: 9041147
    Abstract: According to a semiconductor substrate (40), a space (A) between a plurality of Si thin film (16), which are provide apart from one another on the insulating substrate (30), is (I) larger than a difference between elongation of part of the insulating substrate which part corresponds to the space (A) and elongation of each of Si wafers (10) when a change is made from room temperature to 600° C. and (II) smaller than 5 mm. This causes an increase in a region of each of a plurality of semiconductor thin films which region has a uniform thickness, and therefore prevents transferred semiconductor layers and the insulating substrate from being fractured or chipped.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: May 26, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Mitani
  • Publication number: 20150130065
    Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and H2SO4 can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicants: Intermolecular Inc.
    Inventors: Anh Duong, Errol Todd Ryan
  • Patent number: 9030019
    Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Ludwig Heitzer
  • Patent number: 9029228
    Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: May 12, 2015
    Assignees: SunEdision Semiconductor Limited (UEN201334164H), Kansas State University Research Foundation
    Inventors: Michael R. Seacrist, Vikas Berry, Phong Tuan Nguyen
  • Patent number: 8987909
    Abstract: According to one embodiment, a lower wiring layer is formed by using a sidewall transfer process for forming a sidewall film having a closed loop along a sidewall of a sacrificed or dummy pattern and, after removing the sacrificed pattern to leave the sidewall film, selectively removing the base material with the sidewall film as a mask. One or more upper wiring layers are formed in an upper layer of the lower wiring layer via another layer using the sidewall transfer process. Etching for cutting each of the lower wiring layer and the upper wiring layers is collectively performed, whereby closed-loop cut is applied to the lower wiring layer and the upper wiring layers.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Nansei
  • Patent number: 8987907
    Abstract: A semiconductor device may include a semiconductor layer including at least one unit device, a first interconnection on the semiconductor layer and electrically connected to the at least one unit device, a diffusion barrier layer on the first interconnection, an intermetallic dielectric layer on the diffusion barrier layer, a plug in a first region of the intermetallic dielectric layer and passing through the diffusion barrier layer so that a bottom surface thereof contacts the first interconnection, and a first dummy plug in a second region of the intermetallic dielectric layer, passing through the diffusion barrier layer, and disposed apart from the first interconnection so that a bottom surface of the first dummy plug does not contact the first interconnection.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-sung Kang, Se-myeong Jang
  • Patent number: 8981466
    Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 8981496
    Abstract: An embodiment includes a substrate, wherein a portion of the substrate extends upwards, forming a fin, a gate dielectric over a top surface and sidewalls of the fin, a liner overlaying the gate dielectric, and an uninterrupted metallic feature over the liner a portion of the liner overlaying the gate dielectric, wherein the liner extends from a top surface of the uninterrupted metallic feature and covers sidewalls of the metallic feature, and wherein the gate dielectric, liner, and uninterrupted metallic feature collectively form a gate, a gate contact barrier, and a gate contact.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 8975749
    Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8970015
    Abstract: Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region and the drain region; a dielectric layer disposed over the substrate; and a gate contact, a source contact, and a drain contact. The dielectric layer is disposed over both etch stop layers. The gate contact extends through the dielectric layer and the first etch stop layer to the gate structure. The source contact and the drain contact extend through the dielectric layer and the second etch stop layer respectively to the source region and the drain region.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hong-Dyi Chang, Pei-Chao Su, Kong-Beng Thei, Hun-Jan Tao, Harry-Hak-Lay Chuang
  • Patent number: 8952258
    Abstract: A method, and structures for implementing enhanced interconnects for high conductivity applications. An interconnect structure includes an electrically conductive interconnect member having a predefined shape with spaced apart end portions extending between a first plane and a second plane. A winded graphene ribbon is carried around the electrically conductive interconnect member, providing increased electrical current carrying capability and increased thermal conductivity.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mark D. Plucinski, Arvind K. Sinha, Thomas S. Thompson
  • Patent number: 8952452
    Abstract: Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Seong Kang, Yoon-Hae Kim, Jong-Shik Yoon
  • Publication number: 20150035157
    Abstract: After formation of line openings in a hard mask layer, hard mask level spacers are formed on sidewalls of the hard mask layer. A photoresist is applied and patterned to form a via pattern including a via opening. The overlay tolerance for printing the via pattern is increased by the lateral thickness of the hard mask level spacers. A portion of a dielectric material layer is patterned to form a via cavity pattern by an etch that employs the hard mask layer and the hard mask level spacers as etch masks. The hard mask level spacers are subsequently removed , and the pattern of the line is subsequently transferred into an upper portion of the dielectric material layer, while the via cavity pattern is transferred to a lower portion of the dielectric material layer.
    Type: Application
    Filed: October 21, 2014
    Publication date: February 5, 2015
    Inventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8946898
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: February 3, 2015
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Patent number: 8946890
    Abstract: Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: February 3, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Chung Chyung Han, Weidan Li, Shuhua Yu, Chuan-Cheng Cheng, Albert Wu
  • Patent number: 8912657
    Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: December 16, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Yuichi Nakao, Satoshi Kageyama, Masaru Naitou
  • Patent number: 8906801
    Abstract: Processes for forming integrated circuits and integrated circuits formed thereby are provided in which a first dielectric layer including a first dielectric material is formed on an underlying substrate. A first etch mask having at least two patterned recesses is patterned over the first dielectric layer. At least one first-level via is etched in the first dielectric layer through one patterned recess in the first etch mask with a first etchant, and the first-level via is filled with electrically-conductive material. A second dielectric layer including a second dielectric material is formed over the first dielectric layer. A second etch mask having patterned recesses corresponding to the patterned recesses of the first etch mask is patterned over the second dielectric layer. Second-level vias are etched in the second dielectric layer through the patterned recesses in the second etch mask with a second etchant and exposed to the first etchant.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: December 9, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Ralf Richter, Hans-Jürgen Thees
  • Patent number: 8884310
    Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: November 11, 2014
    Assignees: SunEdison Semiconductor Limited (UEN201334164H), KSU Research Foundation
    Inventors: Michael R. Seacrist, Vikas Berry
  • Patent number: 8884441
    Abstract: The present disclosure relates to an integrated chip (IC) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ILD) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the IC has an inter-level dielectric layer disposed above a semiconductor substrate. The ILD layer has a cavity with a sidewall having a plurality of sections, wherein respective sections have different slopes that cause the cavity to have a rounded shape. A metal layer is disposed within the cavity. The rounded shape of the cavity reduces stress between the ILD layer and the metal layer to prevent cracks from forming along an interface between the ILD layer and the metal layer.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hung Hsueh, Wei-Te Wang, Shao-Yu Chen, Chun-Liang Fan, Kuan-Chi Tsai
  • Patent number: 8884377
    Abstract: In one embodiment, first and second pattern structures respectively include first and second conductive line patterns and first and second hard masks sequentially stacked, and at least portions thereof extends in a first direction. The insulation layer patterns contact end portions of the first and second pattern structures. The first pattern structure and a first insulation layer pattern of the insulation layer patterns form a first closed curve shape in plan view, and the second pattern structure and a second insulation layer pattern of the insulation layer patterns form a second closed curve shape in plan view. The insulating interlayer covers upper portions of the first and second pattern structures and the insulation layer patterns, a first air gap between the first and second pattern structures, and a second air gap between the insulation layer patterns.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sok-Won Lee, Joon-Hee Lee, Jung-Dal Choi, Seong-Min Jo
  • Patent number: 8884433
    Abstract: A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: November 11, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Mou-Shiung Lin, Chien-Kang Chou, Ke-Hung Chen
  • Patent number: 8866144
    Abstract: An object of the present invention is to apply an insulating film of cure and high quality that is suitably applicable as gate insulating film and protective film to a technique that the insulating film is formed on the glass substrate under a temperature of strain point or lower, and to a semiconductor device realizing high efficiency and high reliability by using it. In a semiconductor device of the present invention, a gate insulating film of a field effect type transistor with channel length of from 0.35 to 2.5 ?m in which a silicon nitride film is formed over a crystalline semiconductor film through a silicon oxide film, wherein the silicon nitride film contains hydrogen with the concentration of 1×1021/cm3 or less and has characteristic of an etching rate of 10 nm/min or less with respect to mixed solution containing an ammonium hydrogen fluoride (NH4HF2) of 7.13% and an ammonium fluoride (NH4F) of 15.4%.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Shunpei Yamazaki, Kengo Akimoto
  • Patent number: 8866202
    Abstract: A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: October 21, 2014
    Assignee: Lam Research Corporation
    Inventors: S. M. Reza Sadjadi, Zhi-Song Huang
  • Patent number: 8859415
    Abstract: A method of forming wiring of a semiconductor device includes: forming an insulating resin on a main surface of a substrate such that an opening portion defining a wiring pattern is provided in the insulating resin; forming a first wiring layer made of a first metal on a bottom surface and side surfaces of the opening portion surrounding and a surface of the insulating resin opposite to the main surface of the substrate, the first wiring layer having a bottom portion formed on the bottom surface of the opening portion and side portions formed on the side surfaces, the bottom portion having a thickness greater than a thickness of at least one of the side portions; and cutting the insulating resin and the first wiring layer such that the insulating resin and the first wiring layer are exposed.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Tajima, Akira Tojo
  • Patent number: 8860223
    Abstract: A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: October 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Cristina Casellato, Carmela Cupeta, Michele Magistretti, Fabio Pellizzer, Roberto Somaschini
  • Patent number: 8836129
    Abstract: A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 16, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao
  • Patent number: 8835305
    Abstract: The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Shyng-Tsong Chen, Samuel S. Choi, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Wai-Kin Li, Christopher J. Penny, Shom Ponoth, Yunpeng Yin
  • Patent number: 8829679
    Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: September 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
  • Patent number: 8810032
    Abstract: A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: August 19, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomomi Imamura, Tetsuo Matsuda, Yoshinosuke Nishijo
  • Patent number: 8810034
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: August 19, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi