Multiple Metal Levels On Semiconductor, Separated By Insulating Layer (e.g., Multiple Level Metallization For Integrated Circuit) Patents (Class 257/758)
  • Patent number: 11832442
    Abstract: The present disclosure provides a semiconductor memory device with improved element performance and reliability. The semiconductor memory device comprises a substrate, a gate electrode extending in a first direction in the substrate, a plurality of buried contacts on the substrate, and a fence in a trench between adjacent ones of the buried contacts. The fence is on the gate electrode. The fence includes a spacer film on side walls of the trench and extending in a second direction intersecting the first direction, and a filling film in the trench and on the spacer film. An upper surface of the spacer film is lower than an upper surface of the filling film with respect to the substrate.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: November 28, 2023
    Inventors: Hyeon Woo Jang, Soo Ho Shin, Dong Sik Park, Jong Min Lee, Ji Hoon Chang
  • Patent number: 11817494
    Abstract: A semiconductor device includes an active layer having an active region, a source electrode, a drain electrode, a gate electrode, a source metal layer, a drain metal layer, and a source pad. The source metal layer and the drain metal layer are electrically connected to the source electrode and the drain electrode, respectively. An orthogonal projection of the drain metal layer on the active layer each forms a drain metal layer region. The source pad is electrically connected to the source metal layer. An orthogonal projection of the source pad on the active layer forms a source pad region overlapping the drain metal layer. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: November 14, 2023
    Assignee: ANCORA SEMICONDUCTORS INC.
    Inventors: Li-Fan Lin, Chun-Chieh Yang, Ying-Chen Liu
  • Patent number: 11784460
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a vertical cavity surface emitting laser (VCSEL) device. The method includes forming a bond bump and a bond ring over a substrate. A semiconductor die is bonded to the bond ring. A molding layer is formed around the semiconductor die. The molding layer is laterally offset from a cavity between the semiconductor die and the substrate. A VCSEL structure is formed over the bond bump.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: October 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhih-Bin Chen, Ming Chyi Liu
  • Patent number: 11774392
    Abstract: A chip crack detection structure, including a substrate, a first chip crack detection ring, a second chip crack detection ring, and a seal ring, is provided. The first chip crack detection ring includes multiple first conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the first conductive layers is not in contact with any plug. The second chip crack detection ring surrounds the first chip crack detection ring. The second chip crack detection ring includes multiple second conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the second conductive layers is not in contact with any plug. The seal ring surrounds the second chip crack detection ring. The seal ring includes multiple third conductive layers stacked over the substrate and electrically connected to each other.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: October 3, 2023
    Assignee: United Microelectronics Corp.
    Inventors: Tsong-Lin Shen, Tsung-Yu Yang
  • Patent number: 11744059
    Abstract: Certain aspects are directed to a static random access memory (SRAM) including an SRAM cell with a pass-gate (PG) transistor having increased threshold voltage to improve the read margin of the SRAM cell. The SRAM generally includes a first SRAM cell having a pull-down (PD) transistor and a PG transistor coupled to the PD transistor. In certain aspects, the SRAM includes a second SRAM cell, the second SRAM cell being adjacent to the first SRAM cell and having a PD transistor and a PG transistor coupled to the PD transistor of the second SRAM cell. The SRAM may also include a gate contact region coupled to a gate region of the PG transistor of the first SRAM cell, wherein at least a portion of the gate contact region is offset from a midpoint between the first SRAM cell and the second SRAM cell.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: August 29, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Xia Li, Haining Yang, Bin Yang
  • Patent number: 11728441
    Abstract: A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer, and a structure provided between the first and second semiconductor layers. The semiconductor apparatus further includes a first electrode supported by a first insulating layer, a second electrode supported by a second insulating layer, a first wire bonded to the first electrode through a first opening provided in the first semiconductor layer, and a second wire bonded to the second electrode through a second opening provided in the first semiconductor layer, and an annular member made of a non-insulating material and provided between the first semiconductor layer and the first electrode. A distance from the second semiconductor layer to a first joint between the first electrode and the first wire is longer than a distance from the second semiconductor layer to a second joint between the second electrode and the second wire.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: August 15, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideki Hayashi, Junji Iwata, Keita Torii, Yusuke Todo
  • Patent number: 11721597
    Abstract: A semiconductor device and a method for detecting a defect in a semiconductor device are provided. The semiconductor device includes a packaging structure. The packaging structure includes a redistribution layer and a detecting component disposed in the redistribution layer. The semiconductor device further includes a cooling plate over the packaging structure and a fixing component penetrating through the packaging structure and the cooling plate. The packaging structure and the cooling plate are fixed by the fixing component. The detecting component is in a chain configuration having a ring shaped structure circling around the fixing component.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Huang-Wen Tseng, Chwen-Ming Liu
  • Patent number: 11721624
    Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: August 8, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yuan Ting, Chung-Wen Wu
  • Patent number: 11688632
    Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: June 27, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alex Joseph Varghese, Marc A. Bergendahl, Andrew M. Greene, Dallas Lea, Matthew T. Shoudy, Yann Mignot, Ekmini A. De Silva, Gangadhara Raja Muthinti
  • Patent number: 11682583
    Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang
  • Patent number: 11676958
    Abstract: A semiconductor device includes: first and second core regions; first and second input/output (I/O) regions coupled to each other and to the first and second core regions; the first and second I/O regions being between an expendable region and correspondingly the first and second core regions; a sealing ring surrounding the core regions and the I/O regions; metallization layers and interconnection layers; inter-communication (inter-com) segments extending between the I/O regions; first and second parapets which extend from the first to third sides of the sealing ring or from first to second locations on corresponding third and fourth parapets, the latter extending from the first to third sides of the sealing ring; the first parapet being between the first core region and the first I/O region; and the second parapet being between the second core region and the second I/O region.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Liang-Chen Lin
  • Patent number: 11659767
    Abstract: A thermoelectric element-containing package according to one aspect of the present disclosure includes a thermoelectric conversion module including: a first substrate having first and second main surfaces; a second substrate having third and fourth main surfaces; and a plurality of thermoelectric elements that are sandwiched between the first and second substrates and arranged along the second main surface and the third main surface. The thermoelectric element-containing package further includes: a frame joined to the first and second substrates so as to form a hermetically sealed space surrounding the plurality of thermoelectric elements and disposed between the first substrate and the second substrate; and a placement member that is disposed on the first main surface of the first substrate or the fourth main surface of the second substrate and to which an additional device is to be connected.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: May 23, 2023
    Assignees: NGK SPARK PLUG CO., LTD., FERROTEC MATERIAL TECHNOLOGIES CORPORATION
    Inventors: Masahiro Ogawa, Tetsuya Kato, Takayuki Hachida
  • Patent number: 11621317
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an isolation layer covering the magnetic element and a portion of the semiconductor substrate. The isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding edges of the magnetic element.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: April 4, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Cheng Chen, Wei-Li Huang, Chun-Yi Wu, Kuang-Yi Wu, Hon-Lin Huang, Chih-Hung Su, Chin-Yu Ku, Chen-Shien Chen
  • Patent number: 11610710
    Abstract: A module includes a circuit board and an inductor. The circuit board has a facing surface and a rear surface which are located at opposite sides to each other in an up-down direction. The inductor has a magnetic core and a coil. The magnetic core is made of a soft magnetic metal material. The magnetic core has a facing surface and a radiating surface which are located at opposite sides to each other in the up-down direction. The facing surface of the magnetic core is arranged to face the facing surface of the circuit board in the up-down direction. The radiating surface of the magnetic core is arranged to be radiatable heat outward. The coil has a coil portion and a connection end. The coil portion winds, at least in part, the magnetic core. The connection end is connected to the facing surface of the circuit board.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: March 21, 2023
    Assignee: TOKIN CORPORATION
    Inventors: Kenichi Chatani, Kenji Ikeda, Toshinori Tsuda
  • Patent number: 11605558
    Abstract: A method includes providing a substrate, a dielectric layer over the substrate, and metallic features over the dielectric layer; and forming an organic blocking layer (OBL) over the dielectric layer and between lower portions of the metallic features. The OBL covers sidewall surfaces of the lower portions, but not upper portions, of the metallic features. The method further includes depositing a dielectric barrier layer over top surfaces of the metallic features and over the sidewall surfaces of the upper portions of the metallic features, wherein at least a portion of a top surface of the OBL is not covered by the dielectric barrier layer; forming an inter-metal dielectric (IMD) layer between the metallic features and above the OBL; and removing the OBL, leaving an air gap above the dielectric layer, below the dielectric barrier layer and the IMD layer, and laterally between the lower portions of the metallic features.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Lung Chung, Shin-Yi Yang, Ming-Han Lee
  • Patent number: 11600563
    Abstract: Disclosed is an embedded multi-die interconnect bridge (EMIB) substrate. The EMIB substrate can comprise an organic substrate, a bridge embedded in the organic substrate and a plurality of routing layers. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. Each of the plurality of routing layers can have a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: March 7, 2023
    Assignee: Intel Corporation
    Inventors: Srinivas Venkata Ramanuja Pietambaram, Rahul N. Manepalli
  • Patent number: 11600568
    Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: March 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang, Meng-Xiang Lee, Hao-Tien Kan, Jhih-Hong Ye
  • Patent number: 11538826
    Abstract: A semiconductor device includes: an alternating stack of conductive layers and dielectric layers disposed over a substrate; a channel layer disposed in a through portion, penetrating through the alternating stack; a blocking layer disposed in the through portion, surrounding an outer wall of the channel layer; and a continuous etch stop layer disposed in the through portion, surrounding an outer wall of the blocking layer.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: December 27, 2022
    Assignee: SK hynix Inc.
    Inventor: Jinha Kim
  • Patent number: 11532779
    Abstract: A piezoelectric element includes a piezoelectric body layer, a first electrode, a second electrode, a third electrode, and a conductor. The piezoelectric body layer has rectangular first and second principal surfaces opposing each other, and includes a piezoelectric material. The first electrode is provided on the first principal surface. The second electrode is provided on the first principal surface in such a way that the second electrode is separated from the first electrode. The third electrode is provided on the second principal surface in such a way that the third electrode opposes the first electrode. The conductor is connected to the second electrode and the third electrode. The first electrode has a round corner being rounder than a corner part of the piezoelectric body layer when seen in an opposing direction of the first and second principal surfaces.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: December 20, 2022
    Assignee: TDK CORPORATION
    Inventors: Yoshiki Ohta, Hideya Sakamoto, Kazushi Tachimoto, Nobuo Furukawa, Akihiro Takeda
  • Patent number: 11522130
    Abstract: A routing structure is disclosed. A first wiring line coupled to a programming access device and a routing block driver and receiver enabling device and a second wiring line coupled to a programming access device and a routing block driver and receiver enabling device. An insulator-metal-transistor device that includes a top electrode, a middle electrode and a bottom electrode, coupled at the intersection of the first wiring line and the second wiring line.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 6, 2022
    Assignee: Intel Corporation
    Inventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
  • Patent number: 11508665
    Abstract: A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Yuan Teng, Kuo Lung Pan, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chen-Hua Yu
  • Patent number: 11502000
    Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Chou, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11488893
    Abstract: Provided is a semiconductor device having high planarity in an in-plane direction. This semiconductor device includes a semiconductor substrate, a first plating film pattern, a second plating film pattern, and an insulating layer. The semiconductor substrate has a first surface, and a second surface on a side opposite to the first surface. The first plating film pattern includes a first portion that covers a first regional portion of the first surface, and a second portion that is stacked to cover a portion of the first portion. The second plating film pattern includes a third portion that covers a second regional portion different from the first regional portion of the first surface, and also includes a fourth portion that is stacked to cover a portion of the third portion. A portion between the second portion and the fourth portion is filled with the insulating layer.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: November 1, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takahiro Kamei, Yoichi Ootsuka
  • Patent number: 11476213
    Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: October 18, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Belgacem Haba, Rajesh Katkar, Ilyas Mohammed, Javier A. DeLaCruz
  • Patent number: 11469202
    Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: October 11, 2022
    Inventors: Seong-Min Son, Jeong-Gi Jin, Jin-Ho An, Jin-Ho Chun, Kwang-Jin Moon, Ho-Jin Lee
  • Patent number: 11444118
    Abstract: A method of manufacturing an optoelectronic device, including: a) transferring, onto a connection surface of a control circuit, an active diode stack including at least first and second semiconductor layers of opposite conductivity types, so that the second semiconductor layer in the stack faces the connection surface of the control circuit and is separated from the connection surface of the control circuit by at least one insulating layer; b) forming in the active stack trenches delimiting a plurality of diodes, the trenches extending through the insulating layer and emerging onto the connection surface of the control circuit; and c) forming in the trenches metallizations connecting the second semiconductor layer to the connection surface of the control circuit.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 13, 2022
    Assignee: Commissariat √† l'√Čnergie Atomique et aux √Čnergies Alternatives
    Inventors: Hubert Bono, Julia Simon
  • Patent number: 11444071
    Abstract: An integrated circuit disclosed here includes several cell rows extending in a first direction and a multi-bit cell having several bit cells included in the cell rows. The bit cells include M bit cells, and an output signal of a N-th bit cell of the M bit cells is an input signal of a (N+1)-th bit cell of the M bit cells, N and M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell, and the N-th bit cell and the (N+1)-th bit cell are arranged diagonally in different cell rows in the multi-bit cell.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Lun Chien, Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 11430764
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a semiconductor article having a package substrate, a first semiconductor die coupled to the package substrate, a second semiconductor die coupled to the package substrate and adjacent the first semiconductor die, and a bridge component therebetween coupling the first semiconductor die to the second semiconductor die. The bridge component can include a bridge substrate, a conductive trace therein, and a passive component coupled to the conductive trace.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Seok Ling Lim, Jenny Shio Yin Ong, Jackson Chung Peng Kong, Kooi Chi Ooi
  • Patent number: 11423278
    Abstract: A Radio Frequency Identification (RFID) integrated circuit (IC) is at least partially covered by a repassivation layer that is, in turn, at least partially covered by a large, electrically conductive contact pad. The repassivation layer is disposed so as to leave uncovered at least one IC contact. The large contact pad is disposed so as to cover the IC IC contact. The large contact pad forms a first galvanic coupling to the IC contact and a second galvanic coupling to a tag antenna. The surface area of the first galvanic coupling is substantially smaller than the surface area of the second galvanic coupling.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: August 23, 2022
    Assignee: Impinj, Inc.
    Inventors: Ronald L. Koepp, Harley K. Heinrich, Christopher J. Diorio, Tan Mau Wu
  • Patent number: 11410944
    Abstract: A stacked structure includes a lower structure and an upper structure. The lower structure includes at least one lower dielectric layer and at least one lower metal layer in contact with the lower dielectric layer. The upper structure includes at least one upper dielectric layer and at least one upper metal layer in contact with the upper dielectric layer. The upper dielectric layer includes a first upper dielectric layer attached to the lower structure. The first upper dielectric layer includes a first portion and a second portion. A difference between a thickness of the first portion and a thickness of the second portion is greater than a gap between a highest point of a top surface of the first upper dielectric layer and lowest point of the top surface of the first upper dielectric layer.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 9, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11410848
    Abstract: A method of forming a pattern of an embodiment includes: forming an etch mask on a film to be processed by using a pattern-forming material containing an organic polymer; and patterning the etch mask. In the method of the embodiment, the organic polymer contains 70 atom % or more carbon atoms having an sp2 orbital and 5 atom % or more carbon atoms having an sp3 orbital among the carbon atoms constituting the organic polymer. The patterned etch mask is used for etching of the film to be processed with a gas containing a fluorine atom.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: August 9, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Koji Asakawa, Norikatsu Sasao, Shinobu Sugimura
  • Patent number: 11398539
    Abstract: Arrangements of the present disclosure relate to an array substrate, a display panel and a display device. The array substrate includes a circuit region and a boundary region. The circuit region includes a plurality of stacked conductive layers and an interlayer dielectric disposed between every two adjacent conductive layers. One or more first via holes are provided on the interlayer dielectric. The boundary region is disposed outside the circuit region. One or more second via holes for improving uniformity of the first via holes in the circuit region are disposed within a preset range of the boundary region close to one side of the circuit region. The second via holes and the first via holes are disposed on the same interlayer dielectric.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: July 26, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Pan Li, Yong Qiao, Xueguang Hao
  • Patent number: 11393864
    Abstract: An image sensor is provided. The image sensor includes a first substrate; a plurality of photoelectric conversion units positioned in the first substrate; a first connection layer disposed on the first substrate; a plurality of first pixel pads disposed on the first connection layer; a plurality of first peripheral pads disposed on the first substrate; a plurality of second pixel pads respectively positioned on the plurality of first pixel pads; a plurality of second peripheral pads respectively positioned on the plurality of first peripheral pads; a second connection layer disposed on the plurality of second pixel pads and the plurality of second peripheral pads; a device disposed on the second connection layer; and a second substrate disposed on the second connection layer and the device, wherein a pitch of the plurality of first pixel pads is substantially the same as a pitch of the plurality of pixel regions of the first substrate.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: July 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ingyu Baek, Doowon Kwon
  • Patent number: 11387191
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die; and a redistribution structure including: a plurality of dielectric layers over the encapsulant and the integrated circuit die; a plurality of metallization patterns in the dielectric layers, the metallization patterns being electrically coupled to the integrated circuit die; and a sealing ring in the dielectric layers, the sealing ring extending around the metallization patterns, the sealing ring being electrically isolated from the metallization patterns and the integrated circuit die, the sealing ring including a plurality of sealing ring layers, each of the sealing ring layers including a via portion extending through a respective one of the dielectric layers, the via portion of each of the sealing ring layers being aligned along a same common axis.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tzu Yun Huang, Ming-Che Ho, Hung-Jui Kuo
  • Patent number: 11387185
    Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: July 12, 2022
    Assignee: Sony Group Corporation
    Inventors: Naoki Saka, Daisaku Okamoto, Hideki Tanaka
  • Patent number: 11387204
    Abstract: A semiconductor structure including a semiconductor substrate, an interconnect structure disposed over the semiconductor substrate, and a bonding structure disposed over the interconnect structure is provided. The bonding structure includes a dielectric layer covering the interconnect structure, signal transmission features penetrating through the dielectric layer, and a thermal conductive feature penetrating through the dielectric layer. The thermal conductive feature includes a thermal routing and thermal pads, and the thermal pads are disposed on and share the thermal routing.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 11387210
    Abstract: A semiconductor module is provided, including: a semiconductor chip having an upper surface electrode and a lower surface electrode opposite to the upper surface electrode; a metal wiring plate electrically connected to the upper surface electrode of the semiconductor chip; and a sheet-like low elastic sheet provided on the metal wiring plate, the low elastic sheet having elastic modulus lower than that of the metal wiring plate. A manufacturing method for a semiconductor module is provided, including: providing a semiconductor chip; solder-bonding a metal wiring plate above said semiconductor chip; and applying a sheet-like low elastic sheet having the elastic modulus lower than that of said metal wiring plate to said metal wiring plate.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: July 12, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takafumi Yamada, Hiromichi Gohara
  • Patent number: 11380837
    Abstract: A piezoelectric device that includes a sintered body in which a first conductor portion and a second conductor portion are disposed on both principal surfaces of a piezoelectric ceramic base body. The first conductor portion includes conductive films having a predetermined pattern. An insulating film is formed on the principal surface of the piezoelectric ceramic base body on which the conductive films are disposed such that portions of the conductive films are exposed therethrough. The insulating film has a malleability equal to or greater than that of the conductive films.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 5, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shinsuke Tani
  • Patent number: 11362034
    Abstract: A semiconductor device that is miniaturized and highly integrated is provided. One embodiment of the present invention is a semiconductor device including a first insulator, a second insulator, a first conductor, a second conductor, and a semiconductor layer; the first insulator includes an opening exposing the semiconductor layer; the first conductor is provided in contact with the semiconductor layer at a bottom of the opening; the second insulator is provided in contact with a top surface of the first conductor and a side surface in the opening; the second conductor is provided in contact with the top surface of the first conductor and in the opening with the second insulator therebetween; and the second insulator has a barrier property against oxygen.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 14, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuya Kakehata, Yuta Endo
  • Patent number: 11362064
    Abstract: A package structure includes a first die, a second die, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die is electrically bonded to the first die. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The through via includes a first barrier layer and a conductive post on the first barrier layer. The dielectric layer is on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a second barrier layer and a conductive layer on the second barrier layer. The conductive layer of the redistribution layer is in contact with the conductive post of the through via.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Ming-Fa Chen, Sung-Feng Yeh, Ying-Ju Chen
  • Patent number: 11361987
    Abstract: A method for making a semiconductor apparatus includes forming a first bottom interconnect in a device area of a first dielectric layer; fabricating a device on top of the first bottom interconnect; capping the device with a first interlayer dielectric; exposing a logic area of the first dielectric layer that is adjacent to the device area by removing a portion of the first interlayer dielectric from the first dielectric layer while leaving another portion of the first interlayer dielectric that caps the device; and forming a second bottom interconnect in the logic area of the first dielectric layer. By forming the second bottom interconnect after the device fabrication and capping, damage to the device and to the second bottom interconnect is avoided.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: June 14, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, Saumya Sharma, Tianji Zhou, Chih-Chao Yang
  • Patent number: 11362035
    Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive structure is disposed within the first ILD layer. A capping layer continuously extends along a top surface of the lower conductive structure. An upper ILD structure overlies the lower conductive structure. A conductive body is disposed within the upper ILD structure. A bottom surface of the conductive body directly overlies the top surface of the lower conductive structure. A width of the bottom surface of the conductive body is less than a width of the top surface of the lower conductive structure. A diffusion barrier layer is disposed between the conductive body and the upper ILD structure. The diffusion barrier layer is laterally offset from a region disposed directly between the bottom surface of the conductive body and the top surface of the lower conductive structure by a non-zero distance.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Wen Hsueh, Chii-Ping Chen, Neng-Jye Yang, Ya-Lien Lee, An-Jiao Fu, Ya-Ching Tseng
  • Patent number: 11355177
    Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: June 7, 2022
    Assignee: SK hynix Inc.
    Inventors: Seung-Hwan Kim, Su-Ock Chung, Seon-Yong Cha
  • Patent number: 11348832
    Abstract: A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: May 31, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin C. Backes, Brian A. Cohen, Joyeeta Nag, Carl J. Radens
  • Patent number: 11342357
    Abstract: A semiconductor device structure and method of manufacturing a semiconductor device is provided. The method includes providing a first semiconductor substrate having a first major surface and an opposing second major surface, the first major surface having a first metal layer formed thereon; providing a second semiconductor substrate having a first major surface and an opposing second major surface, with the second semiconductor substrate including a plurality of active device regions formed therein and a second metal layer formed on the first major surface connecting each of the plurality of active device regions; bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate; and forming device contacts on the second major surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: May 24, 2022
    Assignee: Nexperia B.V.
    Inventors: Hans-Martin Ritter, Frank Burmeister
  • Patent number: 11342282
    Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: May 24, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Chiang Shih, Hung-Yi Lin, Meng-Wei Hsieh, Yu Sheng Chang, Hsiu-Chi Liu, Mark Gerber
  • Patent number: 11342292
    Abstract: A bonding pad structure and a method thereof includes: a base metal layer formed on a substrate; first conductive vias arranged in a peripheral region of the base metal layer; an intermediate buffer layer formed above the base metal layer, the intermediate buffer layer spaced from and aligned with the base metal layer, the first conductive vias vertically connecting the base metal layer and the intermediate buffer layer; second conductive vias arranged in a peripheral region of the intermediate buffer layer; a surface bonding layer formed above the intermediate buffer layer, the surface bonding layer spaced from and aligned with the intermediate buffer layer, the second conductive vias vertically connecting the intermediate buffer layer and the surface bonding layer, the intermediate buffer layer comprising a mesh structure, and the first conductive vias and the second conductive vias not vertically aligned with a central region of the intermediate buffer layer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 24, 2022
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Chih Cheng Liu
  • Patent number: 11335811
    Abstract: A semiconductor arrangement and methods of formation are provided. A semiconductor arrangement includes a semiconductor column on a buffer layer over a substrate. The buffer layer comprises a conductive material. Both a first end of the semiconductor column and a bottom contact are connected to a buffer layer such that the first end of the semiconductor column and the bottom contact are connected to one another through the buffer layer, which reduces a contact resistance between the semiconductor column and the bottom contact. A second end of the semiconductor column is connected to a top contact. In some embodiments, the first end of the semiconductor column corresponds to a source or drain of a transistor and the second end corresponds to the drain or source of the transistor.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Georgios Vellianitis
  • Patent number: 11335596
    Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hai-Ching Chen, Shau-Lin Shue
  • Patent number: 11329220
    Abstract: The present invention relates to a non-volatile memory device and a method of fabricating the same. The non-volatile memory device according to an embodiment of the present invention comprises a first electrode; a second electrode; a first oxide layer disposed between the first electrode and the second electrode, and having a reversible filament formed therein; and an oxygen reservoir layer disposed between the first oxide layer and the second electrode, and absorbing oxygens of the first oxide layer to form oxygen vacancy constituting the reversible filament in the first oxide layer. The concentration of the oxygen vacancy may increase from the first oxide layer toward the oxygen reservoir layer.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: May 10, 2022
    Assignees: SK hynix Inc., UIF (University Industry Foundation), Yonsei University
    Inventors: Woo Young Park, Hyunchul Sohn, Jinyeol Lee, Taeho Kim