Multiple Metal Levels On Semiconductor, Separated By Insulating Layer (e.g., Multiple Level Metallization For Integrated Circuit) Patents (Class 257/758)
  • Patent number: 11329220
    Abstract: The present invention relates to a non-volatile memory device and a method of fabricating the same. The non-volatile memory device according to an embodiment of the present invention comprises a first electrode; a second electrode; a first oxide layer disposed between the first electrode and the second electrode, and having a reversible filament formed therein; and an oxygen reservoir layer disposed between the first oxide layer and the second electrode, and absorbing oxygens of the first oxide layer to form oxygen vacancy constituting the reversible filament in the first oxide layer. The concentration of the oxygen vacancy may increase from the first oxide layer toward the oxygen reservoir layer.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: May 10, 2022
    Assignees: SK hynix Inc., UIF (University Industry Foundation), Yonsei University
    Inventors: Woo Young Park, Hyunchul Sohn, Jinyeol Lee, Taeho Kim
  • Patent number: 11329032
    Abstract: A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: May 10, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ae-Nee Jang, Inhyo Hwang
  • Patent number: 11322417
    Abstract: A wiring board of the present disclosure includes: a first insulating layer including a surface; a second insulating layer including un upper surface and a lower surface and locating above the surface of the first insulating layer; a wiring conductor layer formed on the surface of the first insulating layer, includes a via land; and a via hole conductor penetrating from the upper surface to the lower surface of the second insulating layer. The via hole conductor includes a via bottom being in contact with the via land. Crystal grains in the via bottom are smaller than crystal grains in the via land.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: May 3, 2022
    Assignee: KYOCERA CORPORATION
    Inventors: Tsuyoshi Sunada, Hidetoshi Yugawa
  • Patent number: 11304297
    Abstract: Encapsulated electronic modules having complex contact structures may be formed by encapsulating panels containing a substrate comprising pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within terminal holes and other holes drilled in the panel within the boundaries of the cut lines. Slots may be cut in the panel along the cut lines. The interior of the holes, as well as surfaces within the slots and on the surfaces of the panel may be metallized, e.g. by a series of processes including plating. Terminals may be inserted into the terminal holes and connected to conductive features or plating within the holes. A conductive element may be provided on the substrate to connect to a terminal. Alternatively solder may be dispensed into the holes for surface mounting.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: April 12, 2022
    Assignee: Vicor Corporation
    Inventors: Patrizio Vinciarelli, Michael B. LaFleur
  • Patent number: 11302683
    Abstract: A package structure and method of forming the same are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is laterally aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element insertion. The encapsulant laterally encapsulates the second die and the wall structure.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11296285
    Abstract: The present disclosure discloses a flexible substrate and a method for manufacturing the same, and a flexible display substrate and a method for manufacturing the same. The method for manufacturing the flexible substrate includes: sequentially forming a first flexible substrate layer and a first inorganic layer on a rigid base substrate; forming a second flexible substrate layer on a side of the first inorganic layer distal from the first flexible substrate layer, an orthographic projection of the second flexible substrate layer on the first flexible substrate layer being located within the first flexible substrate layer; and stripping off the rigid base substrate to obtain the flexible substrate. The method solves the problem of poor process of the flexible substrate.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: April 5, 2022
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Baoqiang Xu, Xiangnan Wang, Qiang Wen, Jianjun Tan, Haitao Yi
  • Patent number: 11289403
    Abstract: A multi-layer substrate includes: a first insulating layer; a conductor layer that is provided on an upper surface of the first insulating layer and that has a penetrating portion; a second insulating layer that covers the conductor layer and that is stacked on the upper surface of the first insulating layer; a via hole that penetrates the second insulating layer from an upper surface of the second insulating layer to reach an inside of the first insulating layer and that includes the penetrating portion; and an insulating member with which the via hole is filled. The conductor layer has a portion exposed in the via hole, and the insulating member covers an upper surface and a lower surface of the conductor layer exposed in the via hole through the penetrating portion of the conductor layer.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 29, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Misaki Komatsu, Katsuya Fukase
  • Patent number: 11288433
    Abstract: Various implementations described herein refer to a method for providing a cell layout with a power grid line, track lines and vias. The method may include determining a cell placement pitch from architecture rules related to the cell layout. The method may include converting spacing for the vias in terms of the cell placement pitch to identify free regions on the track lines for placement of the vias. The method may include determining boundaries for the free regions based on the spacing of the vias from the power grid line and the track lines.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: March 29, 2022
    Assignee: Arm Limited
    Inventor: Abhilash Velluridathil Thazhathidathil
  • Patent number: 11276652
    Abstract: A method for securing an integrated circuit upon making it includes the steps of delimiting said integrated circuit into a first so-called standard zone and into a second so-called security zone, and randomly misaligning in said security zone between a lower level of interconnection holes and an upper level of interconnection holes generating the formation of an interconnection structure having a random distribution of electrical contact and non-contact points. Also described is a secured integrated circuit obtainable using such a method.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: March 15, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Christelle Charpin-Nicolle, Sophie Bernasconi, Aomar Halimaoui, Florian Pebay-Peyroula
  • Patent number: 11275999
    Abstract: A neural network using a cross-point array is provided along with a pattern readout method thereof. Resistive memory devices are stacked vertically to form the neural network as synaptic devices. The connection strength of the signal passing between two neurons is controlled by the positive and negative conductance of the resistive memory devices and it is possible to recognize and readout patterns by learning in the cross-point array.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: March 15, 2022
    Assignee: Seoul National University R&DBFoundation
    Inventors: Byung-Gook Park, Min-Hwi Kim, Sungjun Kim
  • Patent number: 11276638
    Abstract: A semiconductor structure includes a first conductive line and a second conductive line in a first dielectric layer, and a third conductive line in a second dielectric layer overlying the first dielectric layer. The first conductive line and the second conductive line each extend along a first direction. The third conductive line extends along a second direction different from the first direction and above at least the second conductive line. The semiconductor structure further includes a via in the second dielectric layer and electrically connecting the second conductive line and the third conductive line. The via lands on a portion of the second conductive line. The semiconductor structure further includes a dielectric cap over the first conductive line. A bottom surface of the dielectric cap is below a top surface of the first dielectric layer.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: March 15, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Yi-Chun Huang, I-Chih Chen, Chun-Wei Kuo
  • Patent number: 11271154
    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a metal interconnection. The two magnetic tunnel junction elements are arranged side by side at a first direction. The metal interconnection is disposed between the magnetic tunnel junction elements, wherein the metal interconnection includes a contact plug part having a long shape at a top view, and the long shape has a length at a second direction larger than a width at the first direction, wherein the second direction is orthogonal to the first direction.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: March 8, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Ting-Hsiang Huang, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 11271027
    Abstract: To reduce the capacitance between wiring lines of a semiconductor device, while maintaining mechanical strength and reliability. A semiconductor device including: a multilayer wiring layer in which a plurality of interlayer films and a plurality of diffusion preventing films are alternately stacked, and a wiring line is formed in the interlayer films; a contact via that penetrates a via insulating layer formed on one surface of the multilayer wiring layer, and is electrically connected to the wiring line of the multilayer wiring layer; a through hole that penetrates at least one of the interlayer films and the diffusion preventing films from the other surface of the multilayer wiring layer on the opposite side from the one surface; and an air gap that is connected to the through hole, and is formed in at least one of the interlayer films, to expose the contact via.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 8, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hiroyuki Kawashima
  • Patent number: 11257802
    Abstract: A semiconductor device includes: a first semiconductor substrate and a logic circuit provided on the first semiconductor substrate; a memory cell provided above the logic circuit and a second semiconductor substrate provided above the memory cell; a bonding pad provided above the second semiconductor substrate and electrically connected to the logic circuit; and a wiring provided above the second semiconductor substrate. The wiring is electrically connected to the memory cell, and includes at least one of a data signal line, a control voltage line, and a power supply line.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: February 22, 2022
    Assignee: Toshiba Memory Corporation
    Inventor: Tomoya Sanuki
  • Patent number: 11257805
    Abstract: A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dun-Nian Yaung, Szu-Ying Chen
  • Patent number: 11251115
    Abstract: A redistribution structure including a first redistribution layer is provided. The first redistribution layer includes a dielectric layer; at least one conductive structure located in the dielectric layer, wherein the at least one conductive structure has a width L; and at least one dummy structure located adjacent to the at least one conductive structure and located in the dielectric layer, and the at least one dummy structure has a width D, wherein there is a gap width S between the at least one dummy structure and the at least one conductive structure, and a degree of planarization DOP of the first redistribution layer is greater than or equal to 95%, wherein DOP=[1?(h/T)]*100%, and h refers to a difference between a highest height and a lowest height of a top surface of the dielectric layer; and T refers to a thickness of the at least one conductive structure.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: February 15, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Shao-An Yan, Chieh-Wei Feng, Tzu-Yang Ting, Tzu-Hao Yu, Chien-Hsun Chu, Jui-Wen Yang, Hsin-Cheng Lai
  • Patent number: 11251100
    Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-An Kuo, Ching-Jung Yang, Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
  • Patent number: 11244916
    Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second conductive interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: February 8, 2022
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Jeremy Alfred Theil, Rajesh Katkar, Guilian Gao, Laura Wills Mirkarimi
  • Patent number: 11233008
    Abstract: A method of manufacturing an integrated circuit having buried power rails includes forming a first dielectric layer on an upper surface of a first semiconductor substrate, forming a series of power rail trenches in an upper surface of the first dielectric layer, forming the buried power rails in the series of power rail trenches, forming a second dielectric layer on the upper surface of the first dielectric layer and upper surfaces of the buried power rails, forming a third dielectric layer on a donor wafer, bonding the third dielectric layer to the second dielectric layer, and forming a series of semiconductor devices, vias, and metal interconnects on or in the donor wafer. The buried power rails are encapsulated by the first dielectric layer and the second dielectric layer, and the buried power rails are below the plurality of semiconductor devices.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: January 25, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon Goo Hong, Kang-ill Seo, Mark S. Rodder
  • Patent number: 11227794
    Abstract: A multi-layer interconnect structure with a self-aligning barrier structure and a method for fabricating the same is disclosed. For example, the method includes forming a via through an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and a contact structure, pre-cleaning the via with a metal halide, forming a barrier structure on the contact structure in-situ during the pre-cleaning of the via with the metal halide, and depositing a second metal in the via on top of the barrier structure.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Shuen-Shin Liang, Yu-Yun Peng, Fang-Wei Lee, Chia-Hung Chu, Mrunal Abhijith Khaderbad, Keng-Chu Lin
  • Patent number: 11222751
    Abstract: A multilayer ceramic electronic component includes a ceramic body including first and second surfaces opposing each other in a thickness direction, third and fourth surfaces opposing each other in a width direction, and fifth and sixth surfaces opposing each other in a longitudinal direction, and including a capacitance formation portion having a dielectric layer and first and second internal electrodes disposed to be stacked in the thickness direction with the dielectric layer interposed therebetween; first and second conductive layers disposed on the fifth and sixth surfaces of the ceramic body, respectively, and each including a first conductive metal; and first and second external electrodes each including a second conductive metal and covering the first and second conductive layers, respectively. The first and second conductive layers each have a network structure.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: January 11, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Ah Song, Bong Gyu Choi
  • Patent number: 11211342
    Abstract: A semiconductor device includes a semiconductor substrate, a conductive segment, a conductive layer, a first contact element and a second contact element. The semiconductor substrate includes an active region. The conductive segment is formed on the semiconductor substrate, and extends across the active region. The conductive layer is formed over the semiconductor substrate and the conductive segment. The first contact element, formed between the conductive segment and a first conductive portion of the conductive layer, is arranged to electrically connect the conductive segment to the first conductive portion. The second contact element is formed between the conductive segment and a second conductive portion of the conductive layer. The first contact element and the second contact element are formed on the conductive segment and spaced apart from each other. The second contact element is arranged to electrically isolate the conductive segment from the second conductive portion.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11211291
    Abstract: A semiconductor device includes a base structure including a first interlayer dielectric (ILD) layer and a contact including a conductive liner disposed along a conductive core, a conductive plug disposed on the conductive liner between the conductive core and the first ILD layer to a height of the base structure, and a metallization level including a conductive line and a self-aligned via underneath the conductive line disposed on the contact and the conductive plug. The conductive plug protects underlying material and increases connectivity between the self-aligned via and the contact that was reduced due to misalignment.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: December 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Christopher J. Waskiewicz, Kangguo Cheng, Chih-Chao Yang
  • Patent number: 11201182
    Abstract: An embedded image sensor package including a transparent cover having a first side and an opposing second side. A first layer couples over the second side of the transparent cover and has an opening. An electrically conductive layer couples in or over the first layer and electrically couples with one or more electrical contacts exposed on an outer surface of the package. An image sensor chip having a first side with an image sensor and an opposing second side electrically couples with the electrically conductive layer at the first side of the image sensor chip. The image sensor chip couples over the first layer so the first side of the image sensor chip faces the second side of the transparent cover through the opening. The image sensor chip, first layer, and transparent cover at least partially define a cavity hermetically sealed using an underfill material. The package includes no wirebonds.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: December 14, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Weng-Jin Wu
  • Patent number: 11195748
    Abstract: A method for forming an interconnect structure in an element is disclosed. The method can include patterning a cavity in a non-conductive material. The method can include exposing a surface of the cavity in the non-conductive material to a surface nitriding treatment. The method can include depositing a conductive material directly onto the treated surface after the exposing.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: December 7, 2021
    Assignee: INVENSAS CORPORATION
    Inventors: Cyprian Emeka Uzoh, Laura Wills Mirkarimi
  • Patent number: 11195798
    Abstract: Conducting alloys comprising cobalt, tungsten, and boron and conducting alloys comprising nickel, tungsten, and boron are described. These alloys can, for example, be used to form metal interconnects, can be used as liner layers for traditional copper or copper alloy interconnects, and can act as capping layers. The cobalt-tungsten and nickel-tungsten alloys can be deposited using electroless processes.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Yang Cao, Akm Shaestagir Chowdhury, Jeff Grunes
  • Patent number: 11177211
    Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yen Liu, Boo Yeh, Min-Chang Liang, Jui-Yao Lai, Sai-Hooi Yeong, Ying-Yan Chen, Yen-Ming Chen
  • Patent number: 11171040
    Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
  • Patent number: 11171156
    Abstract: According to an embodiment, a memory device includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting with the first direction, an insulating layer provided between the first conductive layer and the second conductive layer, and a dielectric layer provided between the first conductive layer and the third conductive layer, and between the insulating layer and the third conductive layer, the dielectric layer having a first thickness thinner than a second thickness, the first thickness being a thickness between the first conductive layer and the third conductive layer, the second thickness being a thickness between the insulating layer and the third conductive layer, and the dielectric layer including an oxide including at least one of hafnium oxide and zirconium oxide.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: November 9, 2021
    Assignee: Kioxia Corporation
    Inventors: Tsunehiro Ino, Kazuhiko Yamamoto
  • Patent number: 11171112
    Abstract: Cross talk among wirings formed in an interposer is reduced while increase in a parasitic capacitance among the wirings formed in the interposer is suppressed. A semiconductor device has an interposer including a first wiring layer, a second wiring layer formed above the first wiring layer, and a third wiring layer formed above the second wiring layer. In a plan view, a first signal wiring formed in the first wiring layer and a reference wiring formed in the second wiring layer are distant from each other. Similarly, in a plan view, the reference wiring formed in the second wiring layer and a third signal wiring formed in a third wiring layer are distant from each other.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: November 9, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Ryuichi Oikawa
  • Patent number: 11171089
    Abstract: A method of manufacturing a semiconductor device including the operations of defining a first metal pattern (MX-1) having a first metal pattern pitch (MX-1P); depositing an insulating layer over the first metal pattern; defining a core grid having a plurality of core locations having a coreX pitch (CoreXP) on the insulating layer; removing predetermined portions of the insulating layer to form a plurality of core openings through a predetermined set of the core locations; and elongating the core openings using a directional etch (DrE) to form expanded core openings that are used to form the next metal layer MX pattern.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Chih-Ming Lai, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Patent number: 11164778
    Abstract: A semiconductor device includes a first interconnect structure formed in an MX level of the semiconductor device, the MX level includes a third interlevel dielectric layer located above a second capping layer, a first trench within the third interlevel dielectric layer extending through the second capping layer to expose a top surface of a contact structure located below the second capping layer, the contact structure is located within a second interlevel dielectric layer, a second metal liner conformally deposited within the first trench, and a first seed layer conformally deposited above the second metal liner, the first seed layer includes a metal manganese film. A first thermal annealing process is conducted on the semiconductor device to form a first barrier liner underneath the second metal liner to prevent diffusion of conductive metals.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Junli Wang, Hsueh-Chung Chen, Su Chen Fan, Yann Mignot, Lawrence A. Clevenger
  • Patent number: 11164791
    Abstract: A method of forming a semiconductor structure includes forming a stacked vertical transport field-effect transistor (VTFET) structure including one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower VTFET, an isolation layer, and a second semiconductor layer providing a vertical transport channel for an upper VTFET. The method also includes forming at least one vertical via in the stacked VTFET structure spaced apart from the one or more vertical fins. The method further includes forming at least one horizontal via extending from the vertical via to at least one source/drain region of at least one of the upper and lower VTFETs. The method further includes forming a contact liner in the horizontal via, forming a barrier layer on sidewalls of the vertical via and the contact liner, and forming a contact material over the barrier layer in the vertical via.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Tenko Yamashita, Chen Zhang, Joshua M. Rubin
  • Patent number: 11164832
    Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Li-Hsien Huang
  • Patent number: 11158589
    Abstract: A semiconductor device has a semiconductor chip region which contains a semiconductor chip and a first portion of a passivation film covering the semiconductor chip and a scribe line region which contains a second portion of the passivation film connected to the first portion of the passivation film, a first insulating film protruding from a distal end of the second portion of the passivation film, and at least a part of a first wiring. A first portion of the first insulating film is disposed along the distal end of the second portion of the passivation film, a second portion of the first insulating film protrudes laterally beyond the first portion of the first insulating film, and the first wiring protrudes laterally beyond the second portion of the first insulating film.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: October 26, 2021
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Seung Hun Han, Yun Rae Cho, Nam Gyu Baek, Ae Nee Jang
  • Patent number: 11158546
    Abstract: A semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the guard region. The active region comprises an active device. The guard region of the semiconductor arrangement comprises residue from the active region. A method of forming a semiconductor arrangement is also provided.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Chin-Yi Huang, Shih-Chang Liu
  • Patent number: 11158585
    Abstract: An integrated circuit package shield comprising a frame comprising two or more segments, the segments to interlock with one another along a substrate and the segments comprising electrically conductive material to electrically couple to the substrate; and a lid to cover the frame, the lid comprising a conductive material to electrically couple to the substrate.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: October 26, 2021
    Assignee: Intel IP Corporation
    Inventor: Rizwan Fazil
  • Patent number: 11152215
    Abstract: Described herein is a technique capable of selectively growing a film with a high selectivity on a substrate with surface portions of different materials. According to one aspect of the technique of the present disclosure, there is provided a method of manufacturing a semiconductor device including: (a) forming a second metal film on a substrate with a first metal film and an insulating film formed thereon by alternately supplying a metal-containing gas and a reactive gas onto the substrate, wherein an incubation time on the insulating film is longer than that on the first metal film; and (b) supplying an etching gas onto the substrate to remove the second metal film formed on the insulating film while allowing the second metal film to remain on the first metal film, wherein the second metal film is selectively grown on the first metal film by alternately repeating (a) and (b).
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: October 19, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Motomu Degai, Kimihiko Nakatani, Hiroshi Ashihara
  • Patent number: 11152261
    Abstract: Techniques for self-aligned top via formation at line ends are provided. In one aspect, a method of forming self-aligned vias at line ends includes: patterning (even/odd) metal lines including using a (first/second) hardmask; cutting the hardmask and a select metal line, even or odd, using a cut mask having a window that exposes the hardmask over a cut region of the select metal line; enlarging the window to expose the hardmask on either side of the cut region; selectively etching the hardmask using the enlarged window to form a T-shaped cavity within the cut region; filling the T-shaped cavity with a gap fill dielectric; removing the hardmask; and recessing the metal lines, wherein the gap fill dielectric overhangs portions of the select metal line that, by the recessing, form the self-aligned vias at ends of the metal lines. A structure is also provided.
    Type: Grant
    Filed: October 26, 2019
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, John Arnold, Dominik Metzler
  • Patent number: 11145612
    Abstract: A method for manufacturing an integrated circuit package includes depositing a first layer of metal at a location of a first metal post that is for connecting an IC die to an external circuit. The method also includes depositing a second layer of metal at the location of the first metal post, and a first layer of metal at a location of a second metal post that is for connecting the IC die to an external circuit.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: October 12, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rafael Jose Lizares Guevara, III
  • Patent number: 11139254
    Abstract: A semiconductor device includes: a semiconductor substrate; a first metal ring which is provided outside a periphery of a circuit region including a signal pad on one surface side of the semiconductor substrate and is interrupted by one or a plurality of openings; a second metal ring provided outside a periphery of the first metal ring; and a resistance layer that connects ends of the first metal ring interrupted by the one or the plurality of openings to each other, wherein the first metal ring includes a first wall portion and a second wall portion that sandwich the circuit region, and a third wall portion and a fourth wall portion that sandwich the circuit region and are connected to the first wall portion and the second wall portion, and the one or the plurality of openings is arranged in the first wall portion close to the signal pad.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: October 5, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Yoichi Kawano
  • Patent number: 11139212
    Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first conductive element over a substrate and a second conductive element over the substrate. A dielectric region is over a top surface of the substrate and between the first conductive element and the second conductive element. An electrically conductive structure is over the first conductive element, the second conductive element, and the dielectric region.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yueh-Chuan Lee, Chia-Chan Chen
  • Patent number: 11139246
    Abstract: According to one embodiment, a semiconductor device includes: a semiconductor substrate; a first via provided on the semiconductor substrate; a metal wiring provided on the first via; and a second via provided on the metal wiring. One of the side surfaces facing each other in the first direction of the metal wiring and one of the side surfaces facing each other in the first direction of the second via are aligned in the first direction.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: October 5, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masayuki Kitamura, Atsushi Kato
  • Patent number: 11133253
    Abstract: A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: September 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Juik Lee, Joongwon Shin, Jihoon Chang, Junghoon Han, Junwoo Lee
  • Patent number: 11133265
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an active surface, a plurality of sidewalls connected to the active surface, and a plurality of pads distributed on the active surface. The insulating encapsulation encapsulates the active surface and the sidewalls of the integrated circuit. The insulating encapsulation includes a plurality of first contact openings and a plurality of through holes, and the pads are exposed by the first contact openings. The redistribution circuit structure includes a redistribution conductive layer, wherein the redistribution conductive layer is disposed on the insulating encapsulation and is distributed in the first contact openings and the through holes. The redistribution conductive layer is electrically connected to the pads through the first contact openings. A method of fabricating the integrated fan-out package is also provided.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Hung-Jui Kuo, Yi-Wen Wu
  • Patent number: 11133277
    Abstract: A semiconductor device includes a first semiconductor chip having a first bonding layer and a second semiconductor chip stacked on the first semiconductor chip and having a second bonding layer. The first bonding layer includes a first bonding pad, a plurality of first internal vias, and a first interconnection connecting the first bonding pad and the plurality of first internal vias. The second bonding layer includes a second bonding pad bonded to the first bonding pad. An upper surface of the first interconnection and an upper surface of the first bonding pad are coplanar with an upper surface of the first bonding layer. The first interconnection is electrically connected to the plurality of different first internal lines through the plurality of first internal vias.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: September 28, 2021
    Inventors: Jin Nam Kim, Tae Seong Kim, Hoon Joo Na, Kwang Jin Moon
  • Patent number: 11133268
    Abstract: Embodiments of the present invention are directed to a new crack stop system and a method for providing an interlayer dielectric (ILD) crack bifurcation in semiconductor back-end-of-line (BEOL). In a non-limiting embodiment of the invention, a crack stop is formed over a substrate. The crack stop can span one or more dielectric layers. A topologically interlocking composite structure is formed adjacent to the crack stop and over the substrate. The topologically interlocking composite structure spans the one or more dielectric layers. A capping film is formed over the topologically interlocking composite structure and one or more metal interconnect layers are formed over the capping film. The composite structure includes a bulk matrix material and embedded inclusions. To promote crack bifurcation, materials of the inclusions and bulk matrix material are selected to ensure that the Young's modulus of the inclusions is greater than the Young's modulus of the bulk matrix material.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tuhin Sinha, Naftali Eliahu Lustig
  • Patent number: 11127629
    Abstract: A method of fabricating a semiconductor device includes: forming a trench on an insulating layer to expose a first conductive feature disposed under the insulating layer; forming a barrier layer over the insulating layer, a sidewall of the trench, and the first conductive feature; etching a bottom of the barrier layer to expose the first conductive feature; and forming a second conductive feature over an exposed portion of the first conductive feature.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Su-Horng Lin
  • Patent number: 11127684
    Abstract: A contact structure of a semiconductor device includes a gate contact in contact with a gate structure and extending through a first dielectric layer, a source/drain contact in contact with a source/drain feature and extending through the first dielectric layer, a common rail line in contact with the gate contact and the source/drain contact, and a power rail line in contact with the common rail line and electrically coupled to a ground of the semiconductor device.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Kuo-Yi Chao, Mei-Yun Wang, Ru-Gun Liu
  • Patent number: 11121028
    Abstract: Semiconductor devices and methods of forming are provided. In some embodiments the semiconductor device includes a substrate, and a dielectric layer over the substrate. A first conductive feature is included in the dielectric layer, the first conductive feature comprising a first number of material layers. A second conductive feature is included in the dielectric layer, the second conductive feature comprising a second number of material layers, where the second number is higher than the first number. A first electrical connector is included overlying the first conductive feature.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wei Hsu, Ling-Fu Nieh, Pinlei Edmund Chu, Chi-Jen Liu, Yi-Sheng Lin, Ting-Hsun Chang, Chia-Wei Ho, Liang-Guang Chen