Multiple Metal Levels On Semiconductor, Separated By Insulating Layer (e.g., Multiple Level Metallization For Integrated Circuit) Patents (Class 257/758)
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Patent number: 12107008Abstract: A method of manufacturing a semiconducting device that includes forming first opening for forming bottom electrode hole in a first area of a semiconductor wafer; forming a deeper second opening for overlay/alignment hole in second area; depositing a bottom electrode metal layer filling the first opening to form a bottom electrode and partially filling the second opening. A layer of sacrificial material is then deposited above the bottom electrode layer and completely filling the second opening. A chemical-mechanical planarization process is performed to remove the -bottom electrode metal and -sacrificial layer, the -sacrificial material layer being removed above a surface defined atop the filled remaining portion above the second opening. The sacrificial layer material is removed in the remaining portion of the second opening. The second opening providing an overlay/alignment feature topography detectable for alignment by lithography and for overlay measurement on the overlay metrology tool.Type: GrantFiled: November 10, 2021Date of Patent: October 1, 2024Assignee: International Business Machines CorporationInventors: Soon-Cheon Seo, Dexin Kong, Muthumanickam Sankarapandian, Raghuveer Reddy Patlolla
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Patent number: 12062716Abstract: A semiconductor device includes an active layer having first and second active regions, first and second source electrodes, first and second drain electrodes, first and second gate electrodes, a first source metal layer, first and second drain metal layers, and a source pad electrically connected to the first source metal layer. The second drain metal layer is electrically connected to the second drain electrode and the first source metal layer. A projection of the second drain metal layer on the active layer forms a drain metal layer region. An projection of the source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.Type: GrantFiled: October 6, 2023Date of Patent: August 13, 2024Assignee: Ancora Semiconductors Inc.Inventors: Li-Fan Lin, Chun-Chieh Yang, Ying-Chen Liu
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Patent number: 12057469Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.Type: GrantFiled: May 28, 2021Date of Patent: August 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chiun Lin, Po-Nien Chen, Chen Hua Tsai, Chih-Yung Lin
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Patent number: 12057395Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A high modulus material layer is formed on a conductive stack. A trench is formed that exposes a surface of the liner and filled with metal. The metal is patterned to form interconnect lines and vias. The high modulus material is removed. A conformal layer is formed on exposed surfaces of the stack and the interconnect lines and vias. A low-? dielectric is formed on the conformal layer such that the low-? dielectric is of a height coplanar with the top surface of the vias. The conformal layer is removed from a top surface of the vias. A next level metal layer is formed on the top surface of the vias and low-? dielectric layer such that added vias of the next level metal layer are directly on the top surface of the vias.Type: GrantFiled: September 14, 2021Date of Patent: August 6, 2024Assignee: International Business Machines CorporationInventors: Koichi Motoyama, Kenneth Chun Kuen Cheng, Chanro Park, Chih-Chao Yang
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Patent number: 11996356Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a redistribution layer including a first conductive feature and a second conductive feature, a first contact feature disposed over and electrically coupled to the first conductive feature, a second contact feature disposed over and electrically coupled to the second conductive feature, and a passivation feature extending from between the first conductive feature and the second conductive feature between the first contact feature and the second contact feature. The passivation feature includes a dielectric feature and a dielectric layer. The dielectric layer is disposed on a planar top surface of the dielectric feature and a composition of the dielectric feature is different from a composition of the dielectric layer.Type: GrantFiled: June 5, 2023Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsiang-Ku Shen, Chun-Li Lin, Dian-Hau Chen
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Patent number: 11980455Abstract: A measuring device is provided for reducing the occurrence of damage to a sensor section. The sensor section includes a substrate, a pair of comb electrodes on a first principal surface, and a pair of back-side electrodes disposed on a second principal surface and corresponding to the pair of comb electrodes, respectively. The pair of comb electrodes includes a plurality of tooth sections and connection sections that connect the tooth sections to each other, respectively. The substrate includes via-hole conductors in positions corresponding to the tooth sections inside a region surrounded by the outer tooth sections on opposite ends in a direction in which the tooth sections in the pair of comb electrodes are aligned and the connection sections. The via-hole conductors connect the comb electrodes and the back-side electrodes.Type: GrantFiled: November 30, 2021Date of Patent: May 14, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Jun Takagi, Kenji Tanaka, Tomoki Takahashi
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Patent number: 11978663Abstract: A semiconductor structure includes a first dielectric layer, a first metallic feature over the first dielectric layer, an air gap over the first dielectric layer and adjacent to the first metallic feature, a second dielectric layer disposed above the air gap and on a sidewall of the first metallic feature, and a third dielectric layer disposed above the air gap and on a sidewall of the second dielectric layer. A lower portion of the first metallic feature is exposed in the air gap. The third and the second dielectric layers are substantially co-planar.Type: GrantFiled: March 13, 2023Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Lung Chung, Shin-Yi Yang, Ming-Han Lee
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Devices and methods of vertical integrations of semiconductor chips, magnetic chips, and lead frames
Patent number: 11973029Abstract: Techniques for providing vertical integrations of semiconductor chips, magnetic chips, and lead frames. The techniques can include fabricating an integrated circuit (IC) device as a multi-layer IC structure that includes, within a sealed protective enclosure, a first layer including at least one magnetic chip, a second layer including at least one semiconductor chip or die, and a lead frame. The techniques can further include vertically bonding the magnetic chip in the first layer onto the topside of the lead frame, and vertically bonding the semiconductor chip or die in the second layer on top of the magnetic chip to form a multi-layer IC structure.Type: GrantFiled: February 9, 2022Date of Patent: April 30, 2024Assignee: SUZHOU QING XIN FANG ELECTRONICS TECHNOLOGY CO., LTD.Inventor: Jerry Zhijun Zhai -
Patent number: 11961783Abstract: To provide a semiconductor apparatus that makes it possible to further improve the efficiency in heat dissipation, and to provide an electronic apparatus that includes the semiconductor apparatus. A semiconductor apparatus is provided that includes a substrate, a plurality of chips each stacked on the substrate, and a plurality of guard rings each formed on an outer peripheral portion of a corresponding one of the plurality of chips to surround the corresponding one of the plurality of chips, in which at least portions of at least two of the plurality of guard rings are connected to each other through a thermally conductive material. Further, an electric apparatus is provided that includes the semiconductor apparatus.Type: GrantFiled: February 7, 2020Date of Patent: April 16, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Hitoshi Okano
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Patent number: 11901320Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.Type: GrantFiled: December 12, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chang-Chia Huang, Tsung-Shu Lin, Cheng-Chieh Hsieh, Wei-Cheng Wu
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Patent number: 11881453Abstract: The present disclosure provides a method for preparing a semiconductor device. The method includes forming a sacrificial source/drain structure over a first carrier substrate; forming a redistribution structure over the sacrificial source/drain structure; attaching the redistribution structure to a second carrier substrate; removing the first carrier substrate after the redistribution structure is attached to the second carrier substrate; replacing the sacrificial source/drain structure with a first source/drain structure; forming a backside contact over and electrically connected to the first source/drain structure; and forming an interconnect part over the backside contact.Type: GrantFiled: March 22, 2023Date of Patent: January 23, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chia-Hsiang Hsu
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Patent number: 11869845Abstract: A semiconductor wiring substrate includes a first circuit layer, a second circuit layer and a first dielectric layer. The first circuit layer includes a plurality of first signal traces and a plurality of first ground traces, wherein the first signal traces and the first ground traces are alternatively arranged on the first circuit layer, and one of the first signal traces is spaced at a first spacing from adjacent one of the first ground traces. The first dielectric layer is between the first circuit layer and the second circuit layer and has a first thickness in an arrangement direction of the first circuit layer, the first dielectric layer and the second circuit layer, wherein the first spacing substantially ranges from 0.78 to 1.96 times the first thickness.Type: GrantFiled: August 29, 2022Date of Patent: January 9, 2024Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Fan Yang, Wei-Chiao Wang, Yi-Tzeng Lin
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Patent number: 11832442Abstract: The present disclosure provides a semiconductor memory device with improved element performance and reliability. The semiconductor memory device comprises a substrate, a gate electrode extending in a first direction in the substrate, a plurality of buried contacts on the substrate, and a fence in a trench between adjacent ones of the buried contacts. The fence is on the gate electrode. The fence includes a spacer film on side walls of the trench and extending in a second direction intersecting the first direction, and a filling film in the trench and on the spacer film. An upper surface of the spacer film is lower than an upper surface of the filling film with respect to the substrate.Type: GrantFiled: October 4, 2021Date of Patent: November 28, 2023Inventors: Hyeon Woo Jang, Soo Ho Shin, Dong Sik Park, Jong Min Lee, Ji Hoon Chang
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Patent number: 11817494Abstract: A semiconductor device includes an active layer having an active region, a source electrode, a drain electrode, a gate electrode, a source metal layer, a drain metal layer, and a source pad. The source metal layer and the drain metal layer are electrically connected to the source electrode and the drain electrode, respectively. An orthogonal projection of the drain metal layer on the active layer each forms a drain metal layer region. The source pad is electrically connected to the source metal layer. An orthogonal projection of the source pad on the active layer forms a source pad region overlapping the drain metal layer. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.Type: GrantFiled: December 14, 2020Date of Patent: November 14, 2023Assignee: ANCORA SEMICONDUCTORS INC.Inventors: Li-Fan Lin, Chun-Chieh Yang, Ying-Chen Liu
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Patent number: 11784460Abstract: Various embodiments of the present disclosure are directed towards a method for forming a vertical cavity surface emitting laser (VCSEL) device. The method includes forming a bond bump and a bond ring over a substrate. A semiconductor die is bonded to the bond ring. A molding layer is formed around the semiconductor die. The molding layer is laterally offset from a cavity between the semiconductor die and the substrate. A VCSEL structure is formed over the bond bump.Type: GrantFiled: May 17, 2021Date of Patent: October 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhih-Bin Chen, Ming Chyi Liu
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Patent number: 11774392Abstract: A chip crack detection structure, including a substrate, a first chip crack detection ring, a second chip crack detection ring, and a seal ring, is provided. The first chip crack detection ring includes multiple first conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the first conductive layers is not in contact with any plug. The second chip crack detection ring surrounds the first chip crack detection ring. The second chip crack detection ring includes multiple second conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the second conductive layers is not in contact with any plug. The seal ring surrounds the second chip crack detection ring. The seal ring includes multiple third conductive layers stacked over the substrate and electrically connected to each other.Type: GrantFiled: March 23, 2022Date of Patent: October 3, 2023Assignee: United Microelectronics Corp.Inventors: Tsong-Lin Shen, Tsung-Yu Yang
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Patent number: 11744059Abstract: Certain aspects are directed to a static random access memory (SRAM) including an SRAM cell with a pass-gate (PG) transistor having increased threshold voltage to improve the read margin of the SRAM cell. The SRAM generally includes a first SRAM cell having a pull-down (PD) transistor and a PG transistor coupled to the PD transistor. In certain aspects, the SRAM includes a second SRAM cell, the second SRAM cell being adjacent to the first SRAM cell and having a PD transistor and a PG transistor coupled to the PD transistor of the second SRAM cell. The SRAM may also include a gate contact region coupled to a gate region of the PG transistor of the first SRAM cell, wherein at least a portion of the gate contact region is offset from a midpoint between the first SRAM cell and the second SRAM cell.Type: GrantFiled: December 12, 2019Date of Patent: August 29, 2023Assignee: QUALCOMM INCORPORATEDInventors: Xia Li, Haining Yang, Bin Yang
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Patent number: 11728441Abstract: A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer, and a structure provided between the first and second semiconductor layers. The semiconductor apparatus further includes a first electrode supported by a first insulating layer, a second electrode supported by a second insulating layer, a first wire bonded to the first electrode through a first opening provided in the first semiconductor layer, and a second wire bonded to the second electrode through a second opening provided in the first semiconductor layer, and an annular member made of a non-insulating material and provided between the first semiconductor layer and the first electrode. A distance from the second semiconductor layer to a first joint between the first electrode and the first wire is longer than a distance from the second semiconductor layer to a second joint between the second electrode and the second wire.Type: GrantFiled: March 26, 2021Date of Patent: August 15, 2023Assignee: Canon Kabushiki KaishaInventors: Hideki Hayashi, Junji Iwata, Keita Torii, Yusuke Todo
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Patent number: 11721624Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.Type: GrantFiled: November 19, 2020Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Yuan Ting, Chung-Wen Wu
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Patent number: 11721597Abstract: A semiconductor device and a method for detecting a defect in a semiconductor device are provided. The semiconductor device includes a packaging structure. The packaging structure includes a redistribution layer and a detecting component disposed in the redistribution layer. The semiconductor device further includes a cooling plate over the packaging structure and a fixing component penetrating through the packaging structure and the cooling plate. The packaging structure and the cooling plate are fixed by the fixing component. The detecting component is in a chain configuration having a ring shaped structure circling around the fixing component.Type: GrantFiled: August 30, 2021Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Huang-Wen Tseng, Chwen-Ming Liu
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Patent number: 11688632Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.Type: GrantFiled: December 29, 2020Date of Patent: June 27, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alex Joseph Varghese, Marc A. Bergendahl, Andrew M. Greene, Dallas Lea, Matthew T. Shoudy, Yann Mignot, Ekmini A. De Silva, Gangadhara Raja Muthinti
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Patent number: 11682583Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.Type: GrantFiled: December 11, 2018Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang
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Patent number: 11676958Abstract: A semiconductor device includes: first and second core regions; first and second input/output (I/O) regions coupled to each other and to the first and second core regions; the first and second I/O regions being between an expendable region and correspondingly the first and second core regions; a sealing ring surrounding the core regions and the I/O regions; metallization layers and interconnection layers; inter-communication (inter-com) segments extending between the I/O regions; first and second parapets which extend from the first to third sides of the sealing ring or from first to second locations on corresponding third and fourth parapets, the latter extending from the first to third sides of the sealing ring; the first parapet being between the first core region and the first I/O region; and the second parapet being between the second core region and the second I/O region.Type: GrantFiled: March 26, 2021Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Liang-Chen Lin
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Patent number: 11659767Abstract: A thermoelectric element-containing package according to one aspect of the present disclosure includes a thermoelectric conversion module including: a first substrate having first and second main surfaces; a second substrate having third and fourth main surfaces; and a plurality of thermoelectric elements that are sandwiched between the first and second substrates and arranged along the second main surface and the third main surface. The thermoelectric element-containing package further includes: a frame joined to the first and second substrates so as to form a hermetically sealed space surrounding the plurality of thermoelectric elements and disposed between the first substrate and the second substrate; and a placement member that is disposed on the first main surface of the first substrate or the fourth main surface of the second substrate and to which an additional device is to be connected.Type: GrantFiled: February 14, 2018Date of Patent: May 23, 2023Assignees: NGK SPARK PLUG CO., LTD., FERROTEC MATERIAL TECHNOLOGIES CORPORATIONInventors: Masahiro Ogawa, Tetsuya Kato, Takayuki Hachida
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Patent number: 11621317Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an isolation layer covering the magnetic element and a portion of the semiconductor substrate. The isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding edges of the magnetic element.Type: GrantFiled: August 16, 2021Date of Patent: April 4, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Cheng Chen, Wei-Li Huang, Chun-Yi Wu, Kuang-Yi Wu, Hon-Lin Huang, Chih-Hung Su, Chin-Yu Ku, Chen-Shien Chen
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Patent number: 11610710Abstract: A module includes a circuit board and an inductor. The circuit board has a facing surface and a rear surface which are located at opposite sides to each other in an up-down direction. The inductor has a magnetic core and a coil. The magnetic core is made of a soft magnetic metal material. The magnetic core has a facing surface and a radiating surface which are located at opposite sides to each other in the up-down direction. The facing surface of the magnetic core is arranged to face the facing surface of the circuit board in the up-down direction. The radiating surface of the magnetic core is arranged to be radiatable heat outward. The coil has a coil portion and a connection end. The coil portion winds, at least in part, the magnetic core. The connection end is connected to the facing surface of the circuit board.Type: GrantFiled: December 5, 2019Date of Patent: March 21, 2023Assignee: TOKIN CORPORATIONInventors: Kenichi Chatani, Kenji Ikeda, Toshinori Tsuda
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Patent number: 11605558Abstract: A method includes providing a substrate, a dielectric layer over the substrate, and metallic features over the dielectric layer; and forming an organic blocking layer (OBL) over the dielectric layer and between lower portions of the metallic features. The OBL covers sidewall surfaces of the lower portions, but not upper portions, of the metallic features. The method further includes depositing a dielectric barrier layer over top surfaces of the metallic features and over the sidewall surfaces of the upper portions of the metallic features, wherein at least a portion of a top surface of the OBL is not covered by the dielectric barrier layer; forming an inter-metal dielectric (IMD) layer between the metallic features and above the OBL; and removing the OBL, leaving an air gap above the dielectric layer, below the dielectric barrier layer and the IMD layer, and laterally between the lower portions of the metallic features.Type: GrantFiled: March 26, 2021Date of Patent: March 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Lung Chung, Shin-Yi Yang, Ming-Han Lee
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Patent number: 11600563Abstract: Disclosed is an embedded multi-die interconnect bridge (EMIB) substrate. The EMIB substrate can comprise an organic substrate, a bridge embedded in the organic substrate and a plurality of routing layers. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. Each of the plurality of routing layers can have a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer.Type: GrantFiled: November 12, 2020Date of Patent: March 7, 2023Assignee: Intel CorporationInventors: Srinivas Venkata Ramanuja Pietambaram, Rahul N. Manepalli
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Patent number: 11600568Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.Type: GrantFiled: June 18, 2021Date of Patent: March 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang, Meng-Xiang Lee, Hao-Tien Kan, Jhih-Hong Ye
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Patent number: 11538826Abstract: A semiconductor device includes: an alternating stack of conductive layers and dielectric layers disposed over a substrate; a channel layer disposed in a through portion, penetrating through the alternating stack; a blocking layer disposed in the through portion, surrounding an outer wall of the channel layer; and a continuous etch stop layer disposed in the through portion, surrounding an outer wall of the blocking layer.Type: GrantFiled: June 9, 2020Date of Patent: December 27, 2022Assignee: SK hynix Inc.Inventor: Jinha Kim
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Patent number: 11532779Abstract: A piezoelectric element includes a piezoelectric body layer, a first electrode, a second electrode, a third electrode, and a conductor. The piezoelectric body layer has rectangular first and second principal surfaces opposing each other, and includes a piezoelectric material. The first electrode is provided on the first principal surface. The second electrode is provided on the first principal surface in such a way that the second electrode is separated from the first electrode. The third electrode is provided on the second principal surface in such a way that the third electrode opposes the first electrode. The conductor is connected to the second electrode and the third electrode. The first electrode has a round corner being rounder than a corner part of the piezoelectric body layer when seen in an opposing direction of the first and second principal surfaces.Type: GrantFiled: March 11, 2020Date of Patent: December 20, 2022Assignee: TDK CORPORATIONInventors: Yoshiki Ohta, Hideya Sakamoto, Kazushi Tachimoto, Nobuo Furukawa, Akihiro Takeda
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Patent number: 11522130Abstract: A routing structure is disclosed. A first wiring line coupled to a programming access device and a routing block driver and receiver enabling device and a second wiring line coupled to a programming access device and a routing block driver and receiver enabling device. An insulator-metal-transistor device that includes a top electrode, a middle electrode and a bottom electrode, coupled at the intersection of the first wiring line and the second wiring line.Type: GrantFiled: June 28, 2018Date of Patent: December 6, 2022Assignee: Intel CorporationInventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
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Patent number: 11508665Abstract: A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.Type: GrantFiled: June 23, 2020Date of Patent: November 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Yuan Teng, Kuo Lung Pan, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chen-Hua Yu
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Patent number: 11502000Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.Type: GrantFiled: August 24, 2020Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han Chou, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11488893Abstract: Provided is a semiconductor device having high planarity in an in-plane direction. This semiconductor device includes a semiconductor substrate, a first plating film pattern, a second plating film pattern, and an insulating layer. The semiconductor substrate has a first surface, and a second surface on a side opposite to the first surface. The first plating film pattern includes a first portion that covers a first regional portion of the first surface, and a second portion that is stacked to cover a portion of the first portion. The second plating film pattern includes a third portion that covers a second regional portion different from the first regional portion of the first surface, and also includes a fourth portion that is stacked to cover a portion of the third portion. A portion between the second portion and the fourth portion is filled with the insulating layer.Type: GrantFiled: February 18, 2019Date of Patent: November 1, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takahiro Kamei, Yoichi Ootsuka
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Patent number: 11476213Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.Type: GrantFiled: January 13, 2020Date of Patent: October 18, 2022Assignee: INVENSAS BONDING TECHNOLOGIES, INC.Inventors: Belgacem Haba, Rajesh Katkar, Ilyas Mohammed, Javier A. DeLaCruz
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Patent number: 11469202Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern.Type: GrantFiled: September 23, 2020Date of Patent: October 11, 2022Inventors: Seong-Min Son, Jeong-Gi Jin, Jin-Ho An, Jin-Ho Chun, Kwang-Jin Moon, Ho-Jin Lee
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Patent number: 11444118Abstract: A method of manufacturing an optoelectronic device, including: a) transferring, onto a connection surface of a control circuit, an active diode stack including at least first and second semiconductor layers of opposite conductivity types, so that the second semiconductor layer in the stack faces the connection surface of the control circuit and is separated from the connection surface of the control circuit by at least one insulating layer; b) forming in the active stack trenches delimiting a plurality of diodes, the trenches extending through the insulating layer and emerging onto the connection surface of the control circuit; and c) forming in the trenches metallizations connecting the second semiconductor layer to the connection surface of the control circuit.Type: GrantFiled: September 12, 2019Date of Patent: September 13, 2022Assignee: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Hubert Bono, Julia Simon
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Patent number: 11444071Abstract: An integrated circuit disclosed here includes several cell rows extending in a first direction and a multi-bit cell having several bit cells included in the cell rows. The bit cells include M bit cells, and an output signal of a N-th bit cell of the M bit cells is an input signal of a (N+1)-th bit cell of the M bit cells, N and M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell, and the N-th bit cell and the (N+1)-th bit cell are arranged diagonally in different cell rows in the multi-bit cell.Type: GrantFiled: June 29, 2020Date of Patent: September 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shao-Lun Chien, Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
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Patent number: 11430764Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a semiconductor article having a package substrate, a first semiconductor die coupled to the package substrate, a second semiconductor die coupled to the package substrate and adjacent the first semiconductor die, and a bridge component therebetween coupling the first semiconductor die to the second semiconductor die. The bridge component can include a bridge substrate, a conductive trace therein, and a passive component coupled to the conductive trace.Type: GrantFiled: September 17, 2020Date of Patent: August 30, 2022Assignee: Intel CorporationInventors: Bok Eng Cheah, Seok Ling Lim, Jenny Shio Yin Ong, Jackson Chung Peng Kong, Kooi Chi Ooi
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Patent number: 11423278Abstract: A Radio Frequency Identification (RFID) integrated circuit (IC) is at least partially covered by a repassivation layer that is, in turn, at least partially covered by a large, electrically conductive contact pad. The repassivation layer is disposed so as to leave uncovered at least one IC contact. The large contact pad is disposed so as to cover the IC IC contact. The large contact pad forms a first galvanic coupling to the IC contact and a second galvanic coupling to a tag antenna. The surface area of the first galvanic coupling is substantially smaller than the surface area of the second galvanic coupling.Type: GrantFiled: March 23, 2021Date of Patent: August 23, 2022Assignee: Impinj, Inc.Inventors: Ronald L. Koepp, Harley K. Heinrich, Christopher J. Diorio, Tan Mau Wu
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Patent number: 11410944Abstract: A stacked structure includes a lower structure and an upper structure. The lower structure includes at least one lower dielectric layer and at least one lower metal layer in contact with the lower dielectric layer. The upper structure includes at least one upper dielectric layer and at least one upper metal layer in contact with the upper dielectric layer. The upper dielectric layer includes a first upper dielectric layer attached to the lower structure. The first upper dielectric layer includes a first portion and a second portion. A difference between a thickness of the first portion and a thickness of the second portion is greater than a gap between a highest point of a top surface of the first upper dielectric layer and lowest point of the top surface of the first upper dielectric layer.Type: GrantFiled: August 30, 2019Date of Patent: August 9, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Wen Hung Huang
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Patent number: 11410848Abstract: A method of forming a pattern of an embodiment includes: forming an etch mask on a film to be processed by using a pattern-forming material containing an organic polymer; and patterning the etch mask. In the method of the embodiment, the organic polymer contains 70 atom % or more carbon atoms having an sp2 orbital and 5 atom % or more carbon atoms having an sp3 orbital among the carbon atoms constituting the organic polymer. The patterned etch mask is used for etching of the film to be processed with a gas containing a fluorine atom.Type: GrantFiled: August 19, 2020Date of Patent: August 9, 2022Assignee: KIOXIA CORPORATIONInventors: Koji Asakawa, Norikatsu Sasao, Shinobu Sugimura
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Patent number: 11398539Abstract: Arrangements of the present disclosure relate to an array substrate, a display panel and a display device. The array substrate includes a circuit region and a boundary region. The circuit region includes a plurality of stacked conductive layers and an interlayer dielectric disposed between every two adjacent conductive layers. One or more first via holes are provided on the interlayer dielectric. The boundary region is disposed outside the circuit region. One or more second via holes for improving uniformity of the first via holes in the circuit region are disposed within a preset range of the boundary region close to one side of the circuit region. The second via holes and the first via holes are disposed on the same interlayer dielectric.Type: GrantFiled: April 4, 2019Date of Patent: July 26, 2022Assignee: BOE Technology Group Co., Ltd.Inventors: Pan Li, Yong Qiao, Xueguang Hao
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Patent number: 11393864Abstract: An image sensor is provided. The image sensor includes a first substrate; a plurality of photoelectric conversion units positioned in the first substrate; a first connection layer disposed on the first substrate; a plurality of first pixel pads disposed on the first connection layer; a plurality of first peripheral pads disposed on the first substrate; a plurality of second pixel pads respectively positioned on the plurality of first pixel pads; a plurality of second peripheral pads respectively positioned on the plurality of first peripheral pads; a second connection layer disposed on the plurality of second pixel pads and the plurality of second peripheral pads; a device disposed on the second connection layer; and a second substrate disposed on the second connection layer and the device, wherein a pitch of the plurality of first pixel pads is substantially the same as a pitch of the plurality of pixel regions of the first substrate.Type: GrantFiled: March 17, 2020Date of Patent: July 19, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ingyu Baek, Doowon Kwon
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Patent number: 11387210Abstract: A semiconductor module is provided, including: a semiconductor chip having an upper surface electrode and a lower surface electrode opposite to the upper surface electrode; a metal wiring plate electrically connected to the upper surface electrode of the semiconductor chip; and a sheet-like low elastic sheet provided on the metal wiring plate, the low elastic sheet having elastic modulus lower than that of the metal wiring plate. A manufacturing method for a semiconductor module is provided, including: providing a semiconductor chip; solder-bonding a metal wiring plate above said semiconductor chip; and applying a sheet-like low elastic sheet having the elastic modulus lower than that of said metal wiring plate to said metal wiring plate.Type: GrantFiled: February 19, 2020Date of Patent: July 12, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takafumi Yamada, Hiromichi Gohara
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Patent number: 11387191Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die; and a redistribution structure including: a plurality of dielectric layers over the encapsulant and the integrated circuit die; a plurality of metallization patterns in the dielectric layers, the metallization patterns being electrically coupled to the integrated circuit die; and a sealing ring in the dielectric layers, the sealing ring extending around the metallization patterns, the sealing ring being electrically isolated from the metallization patterns and the integrated circuit die, the sealing ring including a plurality of sealing ring layers, each of the sealing ring layers including a via portion extending through a respective one of the dielectric layers, the via portion of each of the sealing ring layers being aligned along a same common axis.Type: GrantFiled: July 18, 2019Date of Patent: July 12, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Tzu Yun Huang, Ming-Che Ho, Hung-Jui Kuo
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Patent number: 11387204Abstract: A semiconductor structure including a semiconductor substrate, an interconnect structure disposed over the semiconductor substrate, and a bonding structure disposed over the interconnect structure is provided. The bonding structure includes a dielectric layer covering the interconnect structure, signal transmission features penetrating through the dielectric layer, and a thermal conductive feature penetrating through the dielectric layer. The thermal conductive feature includes a thermal routing and thermal pads, and the thermal pads are disposed on and share the thermal routing.Type: GrantFiled: January 16, 2020Date of Patent: July 12, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jie Chen, Hsien-Wei Chen
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Patent number: 11387185Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.Type: GrantFiled: October 6, 2020Date of Patent: July 12, 2022Assignee: Sony Group CorporationInventors: Naoki Saka, Daisaku Okamoto, Hideki Tanaka
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Patent number: 11380837Abstract: A piezoelectric device that includes a sintered body in which a first conductor portion and a second conductor portion are disposed on both principal surfaces of a piezoelectric ceramic base body. The first conductor portion includes conductive films having a predetermined pattern. An insulating film is formed on the principal surface of the piezoelectric ceramic base body on which the conductive films are disposed such that portions of the conductive films are exposed therethrough. The insulating film has a malleability equal to or greater than that of the conductive films.Type: GrantFiled: April 9, 2018Date of Patent: July 5, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Shinsuke Tani