Multiple Metal Levels On Semiconductor, Separated By Insulating Layer (e.g., Multiple Level Metallization For Integrated Circuit) Patents (Class 257/758)
  • Patent number: 10817643
    Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Chen Chen, Hung-Chih Ou
  • Patent number: 10811380
    Abstract: The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first substrate; a first adhesive layer disposed on a surface of the first substrate; and a first bonding layer disposed on a surface of the first adhesive layer. A density of the first adhesive layer is greater than a density of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and first bonding layer, such that it is advantageous to improve a performance of the semiconductor structure.
    Type: Grant
    Filed: April 7, 2019
    Date of Patent: October 20, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xinsheng Wang, Li Zhang, Gaosheng Zhang, Xianjin Wan, Ziqun Hua, Jiawen Wang, Taotao Ding, Hongbin Zhu, Weihua Cheng, Shining Yang
  • Patent number: 10804230
    Abstract: The present disclosure provides a semiconductor package, including a first conductive feature configured as an I/O terminal of the semiconductor package, a first passivation layer, a capacitor, and a second passivation layer. The first conductive feature includes a redistribution portion and a via portion. The maximum width of the redistribution portion along a first direction is more than 10 times the maximum width of the via portion along the first direction. The first passivation layer is surrounding the via portion of the first conductive feature. The capacitor is substantially within the first passivation layer and electrically coupled to the first conductive feature. The second passivation layer is formed on the first passivation layer and surrounding the redistribution portion of the first conductive feature. A method of manufacturing the semiconductor package is also provided.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Tung-Jiun Wu
  • Patent number: 10804184
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate, a restraint layer, a plurality of contact plugs, and a plurality of through silicon vias. The restraint layer is disposed on the semiconductor substrate, and the contact plugs are inserted into the restraint layer. The through silicon vias extend from a bottom surface of the semiconductor substrate to a front surface opposite to the back surface and the through silicon vias are in contact with the contact plugs, respectively.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: October 13, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 10804150
    Abstract: Semiconductor structures are provided. A semiconductor structure includes a substrate having a device region, a seal ring region surrounding the device region, and a dielectric layer disposed thereon. A first seal ring structure is located within the dielectric layer on the seal ring region, and includes a plurality of first connection layers overlappingly disposed and separated by the dielectric layer. At least one first connection layer is formed by a plurality of discrete sub-connection layers. The first seal ring structure further includes a plurality of first conductive plugs between vertically adjacent first connection layers. A top of each first conductive plug is connected to an upper first connection layer. A bottom of each first conductive plug between at least two vertically adjacent first connection layers extends into the dielectric layer between horizontally adjacent sub-connection layers of a lower first connection layer.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: October 13, 2020
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Xianjie Ning
  • Patent number: 10804147
    Abstract: A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level. The second portion is in electrical contact with the first portion.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: October 13, 2020
    Assignee: Tessera, Inc.
    Inventors: Conal E. Murray, Chih-Chao Yang
  • Patent number: 10804149
    Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tsang Hsieh, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Patent number: 10797003
    Abstract: A circuit module 2 comprises: a wiring structure 4; an electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which the electronic component 6a, 6b is embedded; and a metal layer 10 provided on a side surface S1 of the insulating resin layer 8 and a side surface S2 of the wiring structure 4. The surface roughness of the side surface S1 of the insulating resin layer 8 is expressed as R1. The surface roughness of the side surface S2 of the wiring structure 4 is expressed as R2. R1 and R2 differ from each other.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: October 6, 2020
    Assignee: TDK CORPORATION
    Inventors: Shuichi Takizawa, Hironori Sato, Atsushi Yoshino
  • Patent number: 10790392
    Abstract: In accordance with some embodiments of the present disclosure, a semiconductor structure and a fabricating method thereof are provided. The method for forming a semiconductor structure comprises: forming a base substrate; forming a gate structure on the base substrate; forming openings in the base substrate on both sides of the gate structure; forming a barrier layer on sidewalls of the openings adjacent to the gate structure; and forming a doped layer in the openings, and forming a source region or a drain region in the doped layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: September 29, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10790240
    Abstract: A hybrid-bonding structure and a method for forming a hybrid-bonding structure are provided. The hybrid-bonding structure includes a first semiconductor substrate, a first conductive line and a first dielectric dummy pattern. The first conductive line is formed over the first semiconductor substrate. A surface of the first conductive line is configured to hybrid-bond with a second conductive line over a second semiconductor substrate. The first dielectric dummy pattern is formed over the first semiconductor substrate and embedded in the first conductive line.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Ming Wu, Kuan-Liang Liu, Pao-Tung Chen
  • Patent number: 10763208
    Abstract: A semiconductor device includes a semiconductor substrate, a metal layer, a dielectric layer, and a via. The metal layer is disposed above the semiconductor substrate. The dielectric layer is disposed between the metal layer and the semiconductor substrate. The via is embedded in the dielectric layer and comprises a first portion and a second portion between the first portion and the semiconductor substrate. The first portion of the via has a first width. The second portion of the via has a second width greater than the first width of the first portion.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10763162
    Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 10741441
    Abstract: A via and a method of fabricating a via in an integrated circuit involve forming a trench in dielectric material deposited above a first cap of a first metal level. The method includes patterning a collar from insulator material directly above the first cap, and etching through the first cap, within an area surrounded by the collar, to a first metal layer of the first metal level directly below the first cap. A liner is conformally deposited. The liner lines sidewalls of the collar. A metal conductor is deposited to form the via and a second metal layer of a second metal level.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Baozhen Li, Chih-Chao Yang, Andrew Tae Kim
  • Patent number: 10741489
    Abstract: A rectangular via extending between interconnects in different metallization levels can have a planform with a width equal to the width of the interconnects and a length equal to twice the width and can be aligned along a long dimension with a length of the upper interconnect. In an integrated circuit layout, the planform can be centered over the width of the lower interconnect, allowing for misalignment during fabrication while maintaining a robust electrical connection. The bottom of the via may be aligned with an upper surface of the lower interconnect or may include portions below the lower interconnect's upper surface. Fewer adjacent routing tracks are blocked by use of the rectangular via than would be blocked using redundant square vias, while ensuring reliability of the electrical connection despite potential misalignment during fabrication.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: August 11, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: James Walter Blatchford
  • Patent number: 10734321
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Yu-Jung Chang, Guo-Huei Wu, Shih-Ming Chang
  • Patent number: 10734336
    Abstract: Reliability of a semiconductor device is improved. A first pad electrode is formed in an uppermost layer of a multilayer wiring layer, an insulating film of a non-organic material is formed over the first pad electrode, and an organic insulating film is formed over the insulating film. In the organic insulating film, an opening reaching the first pad electrode and a groove reaching the insulating film are formed. Over the organic insulating film, a plurality of re-wirings each having a barrier metal film and a conductive film are formed. In a plan view, the groove is formed in an area between the re-wirings. At the same time, a width of the groove is smaller than a width of a first portion or a width of a second portion of the re-wirings, respectively, neighboring to each other and extending in a first direction.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: August 4, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuya Usami
  • Patent number: 10727123
    Abstract: A method of increasing a tolerance to misalignment errors in forming an interconnect via includes: providing a dielectric substrate including at least first and second adjacent metal conductors laterally from one another in a lower metal wiring layer of the integrated circuit; forming a capping layer over at least a portion of an upper surface of the substrate; forming an insulting layer on at least a portion of the capping layer; forming an opening through the insulating and capping layers to expose the first metal conductor; forming a conductive pedestal on the first metal conductor, the conductive pedestal capping an overlay region in the substrate between the first and second metal conductors resulting from misalignment of the opening relative to the first metal conductor; forming a conductive liner on sidewalls of the opening and on the conductive pedestal; and filling the opening with a conductive material to form the via.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kafai Lai, Chih-Chao Yang
  • Patent number: 10707163
    Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Vincent Chun Fai Lau, Jung-ho Do, Byung-sung Kim, Chul-hong Park
  • Patent number: 10700000
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10700005
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first metal wire arranged within an inter-level dielectric (ILD) layer over a substrate and laterally separated in a first direction from a first closest air-gap by a first distance. A second metal wire is arranged within the ILD layer and is laterally separated in the first direction from a second closest air-gap by a second distance that is larger than the first distance. A via is disposed on an upper surface of the second metal wire.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin
  • Patent number: 10700001
    Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mirng-Ji Lii, Chung-Shi Liu, Chin-Yu Ku, Hung-Jui Kuo, Alexander Kalnitsky, Ming-Che Ho, Yi-Wen Wu, Ching-Hui Chen, Kuo-Chio Liu
  • Patent number: 10700026
    Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Li-Hsien Huang
  • Patent number: 10686122
    Abstract: A variable resistance memory device includes a metal interconnection layer on a substrate, an interlayer insulating layer on the metal interconnection layer and defining a contact hole for exposing a portion of the metal interconnection layer, a barrier metal layer including a plurality of sub-barrier metal layers inside the contact hole, a plug metal layer on the barrier metal layer and burying the contact hole, and a variable resistance structure on the barrier metal layer and the plug metal layer.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hwan Park, Ju-hyun Kim, Se-chung Oh, Dong-kyu Lee, Jung-min Lee, Kyung-il Hong
  • Patent number: 10685870
    Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Hsu, Ming-Che Ku, Neng-Jye Yang, Yu-Wen Wang
  • Patent number: 10679934
    Abstract: A semiconductor interconnect structure and a method of fabricating the same are provided. The semiconductor interconnect structure includes a sea of interconnect lines including metal lines and neighboring dummy lines. The semiconductor interconnect structure further includes a dielectric layer arranged between the sea of lines.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Huai Huang, Christopher J. Penny, Michael Rizzolo, Hosadurga Shobha
  • Patent number: 10658233
    Abstract: Techniques for dielectric damage-free interconnects are provided. In one aspect, a method for forming a Cu interconnect structure includes: forming a via and trench in a dielectric over a metal line M1; depositing a first barrier layer into the via and trench; removing the first barrier layer from the via and trench bottoms using neutral beam oxidation, and removing oxidized portions of the first barrier layer such that the first barrier layer remains along only sidewalls of the via and trench; depositing Cu into the via in direct contact with the metal line M1 to form a via V1; lining the trench with a second barrier layer; and depositing Cu into the trench to form a metal line M2. The second barrier layer can instead include Mn or optionally CuMn so as to further serve as a seed layer. A Cu interconnect structure is also provided.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Koichi Motoyama, Benjamin D. Briggs, Gangadhara Raja Muthinti, Cornelius Brown Peethala, Lawrence A. Clevenger
  • Patent number: 10658337
    Abstract: Packages and packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a molding compound and a plurality of through-vias disposed in the molding compound. The package includes an interconnect structure disposed over the plurality of through-vias and the molding compound. The interconnect structure includes a metallization layer. The metallization layer includes a plurality of contact pads and a fuse.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Hsien-Wei Chen, Der-Chyang Yeh, An-Jhih Su
  • Patent number: 10644171
    Abstract: A solar cell can include a photoelectric conversion unit including a semiconductor substrate, a tunneling layer disposed on the semiconductor substrate, a first conductive type region and a second conductive type region disposed on the tunneling layer at a same side of the semiconductor substrate, and a barrier region disposed between the first and second conductive type regions; and an electrode disposed on the photoelectric conversion unit and including an adhesive layer disposed on the first and second conductive type regions, and an electrode layer disposed on the adhesive layer, in which the adhesive layer has a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of the photoelectric conversion unit and is less than a coefficient of thermal expansion of the electrode layer.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: May 5, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Jeongbeom Nam, Doohwan Yang, Eunjoo Lee, Ilhyoung Jung
  • Patent number: 10636703
    Abstract: A semiconductor device which prevents a crack from occurring on a pad region is provided. The semiconductor device includes a lower pad, an upper pad which is formed above the lower pad, an insulation layer which is formed between the lower pad and the upper pad, a via net for electrically connecting the lower pad and the upper pad in the insulation layer, the via net having a net shape in which a unit grid is connected with its adjacent unit grids to form a net structure, and at least one via hole for electrically connecting the lower pad and the upper pad in the unit grid of the via net.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: April 28, 2020
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jong-yeul Jeong
  • Patent number: 10622316
    Abstract: An apparatus comprises a plurality of conductive elements arranged within at least a first conductive layer and a dielectric layer comprising a plurality of microcapsules. The first conductive layer is arranged on a first side of the dielectric layer. The apparatus further comprises monitoring circuitry coupled with the plurality of conductive elements and configured to detect a change in an electrical parameter for at least a first conductive element of the plurality of conductive elements. The change in the electrical parameter indicates a physical intrusion of the dielectric layer that causes a rupture of one or more microcapsules of the plurality of microcapsules.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark J. Jeanson, Joseph Kuczynski
  • Patent number: 10622398
    Abstract: An image pickup apparatus includes a silicon layer, a wire layer that contains an insulator having a lower dielectric constant than silicon oxide, a cover glass that covers a light receiving portion on a light receiving surface of the silicon layer, and a silicon substrate that covers a back surface of the wire layer, in which a guard ring is formed along an outer edge on the wire layer, a through-hole having a bottom surface that is configured by an electrode pad configured by a conductor of the wire layer and having an outer periphery portion in contact with the silicon layer over a whole periphery is provided in a region of the silicon layer that is not covered with the cover glass, and the insulator of the wire layer is not exposed to an inner surface of the through-hole.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: April 14, 2020
    Assignee: OLYMPUS CORPORATION
    Inventor: Kazuhiro Yoshida
  • Patent number: 10609819
    Abstract: A high density region for a low density circuit. At least a first liquid dielectric layer is deposited on the first surface of a first circuitry layer. The dielectric layer is imaged to create plurality of first recesses. Surfaces of the first recesses are plated electro-lessly with a conductive material to form first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A plating resist is applied. A conductive material is electro-plated to the first conductive structure to substantially fill the first recesses, and the plating resist is removed.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: March 31, 2020
    Assignee: HSIO Technologies, LLC
    Inventor: James J. Rathburn
  • Patent number: 10607933
    Abstract: A structure having fully aligned via connecting metal lines on different Mx levels. The structure may include a first metal line and a second metal line in a first ILD, a cap covering the first ILD, the second metal line and a portion of the first metal line, a second ILD on the cap, and a via that electrically connects the first metal line to a third metal line, wherein the third metal line is above the first metal line and runs perpendicular to the first metal line, the via is fully aligned to the first metal line and the third metal line, and the via electrically connects the first metal line to the third metal line.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Nicholas C. Fuller, Elbert E. Huang, Satyanarayana V. Nitta, David L. Rath
  • Patent number: 10607940
    Abstract: A semiconductor module includes a metal core layer that includes: a first metal layer and a second metal layer on the first metal layer, wherein a portion of the second metal layer is removed to expose a surface of the first metal layer, the removed portion of the second metal layer defining a cavity in the metal core layer having the exposed surface of the first metal layer as a bottom surface, and at least one of a side wall and the bottom surface of the cavity has a smoother surface profile than a surface of the first metal layer that is not exposed by the cavity and under the second metal layer; and a semiconductor element provided in the cavity, affixed to the bottom surface of the cavity with a fixing material containing a resin component.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: March 31, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Yuichi Sugiyama, Masashi Miyazaki, Yoshiki Hamada
  • Patent number: 10600771
    Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Jun Iijima, Yumi Nakajima
  • Patent number: 10600789
    Abstract: A method of forming a micro-pattern including forming a mold layer and a supporting material layer on a substrate, patterning the mold layer and the supporting material layer to form recess patterns, forming conductor patterns in the recess patterns, removing a portion of an upper portion of the supporting material layer for causing upper portions of the conductor patterns to protrude, forming a block copolymer layer on the supporting material layer, processing the block copolymer layer to phase-separate the block copolymer layer into a plurality of block parts, selectively removing some of the phase-separated plurality of block parts, and removing the supporting material layer to expose the mold layer at a position corresponding to each of the removed block parts may be provided.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soon-mok Ha, Jae-hee Kim, Chan Hwang, Jong-hyuk Kim
  • Patent number: 10600681
    Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
  • Patent number: 10593607
    Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hong Wan Ng, Choon Kuan Lee, David J. Corisis, Chin Hui Chong
  • Patent number: 10593616
    Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: March 17, 2020
    Assignee: Tessera, Inc.
    Inventors: Toyohiro Aoki, Takashi Hisada, Akihiro Horibe, Sayuri Hada, Eiji I. Nakamura, Kuniaki Sueoka
  • Patent number: 10586768
    Abstract: A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: March 10, 2020
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Hiroshi Kudo, Takamasa Takano
  • Patent number: 10573512
    Abstract: Disclosed is a method of forming a nitride film on a substrate to be processed (“processing target substrate”) having a carbon-containing film that contains a carbon atom. The method includes placing the processing target substrate within a processing container of a film forming apparatus, and forming a first nitride film on the carbon-containing film by plasma of a first reaction gas including a gas of nitride species having no hydrogen atom, and an inert gas.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 25, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Takeshi Oyama, Noriaki Fukiage
  • Patent number: 10566378
    Abstract: Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: February 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuang-Ji Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Hsiao-Hui Tseng
  • Patent number: 10559533
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a stacked body that alternately includes a plurality of first films and a plurality of second films on a substrate. The method further includes performing a first process of forming N2 holes having N kinds of depths in the stacked body where N is an integer of three or more. The method further includes performing a second process of processing the N2 holes so as to have N2 kinds of depths after performing the first process.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: February 11, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Toshiyuki Sasaki
  • Patent number: 10559498
    Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Michael Rizzolo
  • Patent number: 10559543
    Abstract: A semiconductor device includes a substrate including a first region and a second region at least partially surrounding the first region in a plan view. A protection pattern is disposed on the second region of the substrate and at least partially surrounds the first region of the substrate in the plan view. A protection trench overlaps the protection pattern and at least partially surrounds the first region of the substrate in the plan view, along the protection pattern. A width of the protection trench is different from a width of the protection pattern.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sundae Kim, Yun-Rae Cho, Namgyu Baek
  • Patent number: 10553541
    Abstract: The present disclosure relates to a fan-out semiconductor package in which a plurality of semiconductor chips are stacked and packaged, and are disposed in a special form to be thus electrically connected to a redistribution layer of a connection member through vias rather than wires. The fan-out semiconductor package can further include a connection member having a through-hole, and at least one of the semiconductor chips can be disposed in the through-hole.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyung Joon Kim, Jung Ho Shim, Dae Hyun Park, Han Kim
  • Patent number: 10555421
    Abstract: A component-embedded resin substrate (1) includes a plurality of resin layers (2) made of a first resin and laminated on one another, and a component (3) arranged to be surrounded by each resin layer (2) in a first group (8) which is a group of two or more resin layers arranged successively in a thickness direction included in the plurality of resin layers (2). An auxiliary resin portion (9) made of a second resin different from the first resin is arranged to be in contact with and along at least one of surfaces of the component (3).
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: February 4, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yoshihito Otsubo
  • Patent number: 10552565
    Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: February 4, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Eugene Anikin, Fedor G. Pikus, Laurence Grodd, David A. Abercrombie, John W. Stedman
  • Patent number: 10546730
    Abstract: A method may include providing a cavity in a surface of a substrate, the cavity comprising a sidewall portion and a lower surface; directing depositing species to the surface of the substrate, wherein the depositing species condense to form a fill material on the sidewall portion and lower surface; and directing angled ions at the cavity at a non-zero angle of incidence with respect to a perpendicular to a plane defined by the substrate, wherein the angled ions strike an exposed part of the sidewall portion and do not strike the lower surface, and wherein the cavity is filled by the fill material in a bottom-up fill process.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: January 28, 2020
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC
    Inventors: Simon Ruffell, John Hautala
  • Patent number: 10535514
    Abstract: Provided are methods of sealing open pores of a surface of a porous dielectric material using an initiated chemical vapor deposition (iCVD) process. In one example method of sealing open pores, since the polymer thin film having a significantly thin thickness may be formed by a solvent-free vapor deposition method without plasma treatment, it is possible to minimize deterioration of characteristics of the dielectric material vulnerable to plasma and a chemical solution.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: January 14, 2020
    Assignees: Korea Advanced Institute of Science and Technology, Lam Research Corporation
    Inventors: Byung Jin Cho, Sung Gap Im, Seong Jun Yoon, Kwanyong Pak, Hyungsuk Alexander Yoon