At Least One Layer Containing Vanadium, Hafnium, Niobium, Zirconium, Or Tantalum Patents (Class 257/761)
  • Patent number: 10541265
    Abstract: A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: January 21, 2020
    Assignee: Sony Corporation
    Inventor: Atsushi Okuyama
  • Patent number: 10431506
    Abstract: Disclosed are a method of processing a substrate and a method of fabricating a semiconductor device using the same. The method of processing a substrate comprises forming a mask layer on a substrate, inspecting the mask layer, and forming a mask pattern based on an inspection result of the mask layer. The operation of inspecting the mask layer comprises using Raman spectrum analysis to detect defects in the mask layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dusik Bae, Yoonmi Lee, Hyeogki Kim, Kyoungsil Park, JungDae Park
  • Patent number: 10395983
    Abstract: A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 27, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10043754
    Abstract: A device having a conductive feature disposed on a substrate; a cap structure is disposed on top of the conductive feature and on at least two sidewalls of the conductive feature. An air gap cap disposed on the cap structure and defines an air gap adjacent the conductive feature.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: August 7, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yuan Ting, Jyu-Horng Shieh
  • Patent number: 9978941
    Abstract: A self-rectifying resistive random access memory (RRAM) cell structure is provided. The self-rectifying RRAM cell structure includes a first electrode. An insulator-metal-transition (IMT) material layer is disposed on the first electrode. A barrier layer is disposed on the IMT material layer. A second electrode is disposed on the barrier layer. The IMT material layer is separated from the second electrode by the barrier layer.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: May 22, 2018
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Tuo-Hung Hou, Chung-Wei Hsu, Chun-Tse Chou
  • Patent number: 9818710
    Abstract: An embodiment includes a semiconductor structure comprising: a backend portion including a plurality of metal layers between bottom and top metal layers; the top metal layer including a top metal layer portion having first and second opposing sidewall surfaces and a top surface that couples the sidewall surfaces to one another; an insulator layer directly contacting the top surface; and a via coupling a contact bump to the top metal layer portion; wherein a first vertical axis, orthogonal to a substrate coupled to the backend portion, intercepts the contact bump, the nitride layer, the via, and the top metal layer portion. Other embodiments are described herein.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Jiho Kang, Hiten Kothari, Carole C. Montarou, Andrew W. Yeoh
  • Patent number: 9484206
    Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a foundation layer including first and second layers being different from each other in material, and the foundation layer including a surface on which a boundary of the first and second layers is presented, a catalyst layer on the surface of the foundation layer, and the catalyst layer including a protruding area. The device further includes a graphene layer being in contact with the protruding area.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: November 1, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Taishi Ishikura, Akihiro Kajita, Tadashi Sakai, Atsunobu Isobayashi, Makoto Wada, Tatsuro Saito, Masayuki Kitamura, Atsuko Sakata
  • Patent number: 9455182
    Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: September 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 9395469
    Abstract: A method to prepare low reflective surface according to an example of the present invention comprises: the first step to prepare materials having pillar structure on the surface; the second step to prepare aluminum surface-materials by treating for the pillar structure to have aluminum surface; and the third step to prepare a low reflective surface with dual protuberance structure by forming nano-flake layer on the pillar surface of the material surface through oxidation of the surface aluminum of the aluminum surface-materials. The method to prepare low reflective surface can provide a low reflective surface structure that can be applied to photovoltaic device surface or various display surface as a surface able to reduce reflection significantly by absorbing wavelengths in the range of visible and infrared ray through internally total reflection with simple, low cost, and ecofriendly process.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: July 19, 2016
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Heon Ju Lee, Myoung Woon Moon, Kyu Hwan Oh, Seong Jin Kim, Eu Sun Yu, Tae Jun Ko, Seung Chul Kim
  • Patent number: 9041145
    Abstract: The performances of a semiconductor device are improved. Between a memory gate electrode and a p type well, and between a control gate electrode and the memory gate electrode of a split gate type nonvolatile memory, an insulation film having a charge accumulation layer therein is formed. The insulation film includes a lamination film of a silicon oxide film, a silicon nitride film formed thereover, another silicon oxide film formed thereover, and an insulation film formed thereover, and thinner than the upper silicon oxide film. The insulation film is in contact with the memory gate electrode including polysilicon. The insulation film is formed of a metal compound containing at least one of Hf, Zr, Al, Ta, and La, and hence can cause Fermi pinning, and has a high dielectric constant.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: May 26, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiyuki Kawashima
  • Patent number: 9030016
    Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: May 12, 2015
    Assignee: Sandisk Technologies Inc.
    Inventors: Vinod R. Purayath, James K. Kai, Jayavel Pachamuthu, Jarrett Jun Liang, George Matamis
  • Publication number: 20150115442
    Abstract: A redistribution layer for a chip is provided, wherein the redistribution layer comprises at least one electrical conductor path connecting two connection points with each other, wherein the at least one electrical conductor path is arranged on a planar supporting layer and wherein the electrical conductor path comprises copper and at least one other further electrical conductive material in an amount of more than 0.04 mass percent.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: Infineon Technologies AG
    Inventors: Georg MEYER-BERG, Reinhard Pufall
  • Patent number: 9018767
    Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Griselda Bonilla, Alfred Grill, Thomas J. Haigh, Jr., Satyanarayana V. Nitta, Son Nguyen
  • Patent number: 9006899
    Abstract: In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: April 14, 2015
    Assignee: Infineon Technologies AG
    Inventors: Paul Ganitzer, Kurt Matoy, Martin Sporn, Mark Harrison
  • Patent number: 8993440
    Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Masuda, Kei Watanabe, Kenichi Ootsuka
  • Patent number: 8974648
    Abstract: The present invention provides a reactive sputtering method and a reactive sputtering apparatus which suppress a film quality change caused by a temperature variation in continuous substrate processing. An embodiment of the present invention performs reactive sputtering while adjusting a flow rate of reactive gas according to the temperature of a constituent member facing a sputtering space. Specifically, a temperature sensor is provided on a shield and the flow rate is adjusted according to the temperature. Thereby, even when a degassing amount of a film adhering to the shield changes, a partial pressure of reactive gas can be set to a predetermined value. For a resistance change layer constituting a ReRAM, a perovskite material such as PrCaMn03 (PCMO), LaSrMnO3 (LSMO), and GdBaCoxOy (GBCO), a two-element type transition metal oxide material which has a composition shifted from a stoichiometric one, such as nickel oxide (NiO), vanadium oxide (V2O5), and the like are used.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: March 10, 2015
    Assignee: Canon Anelva Corporation
    Inventors: Yuichi Otani, Takashi Nakagawa
  • Patent number: 8969195
    Abstract: Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Felix P. Anderson, Steven P. Barkyoumb, Edward C. Cooney, III, Thomas L. McDevitt, William J. Murphy, David C. Strippe
  • Patent number: 8963330
    Abstract: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise an aluminum-containing compound and one or both of silane and silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventor: John Smythe
  • Patent number: 8962478
    Abstract: A method of forming a doped TaN Cu barrier adjacent to a Ru layer of a Cu interconnect structure and the resulting device are provided. Embodiments include forming a cavity in a SiO-based ILD; conformally forming a doped TaN layer in the cavity and over the ILD; conformally forming a Ru layer on the doped TaN layer; depositing Cu over the Ru layer and filling the cavity; planarizing the Cu, Ru layer, and doped TaN layer down to an upper surface of the ILD; forming a dielectric cap over the Cu, Ru layer, and doped TaN layer; and filling spaces formed between the dielectric cap and the doped TaN layer.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: February 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Kunaljeet Tanwar
  • Publication number: 20150035158
    Abstract: Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line in electrical contact with a device. The method further includes forming at least one staple structure in electrical contact with the at least one metal line. The at least one staple structure is formed such that electrical current passing through the at least one metal line also passes through the at least staple structure to reduce electromigration issues.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 5, 2015
    Inventors: Jeffrey P. GAMBINO, David L. HARAME, Baozhen LI, Timothy D. SULLIVAN, Bjorn K.A. ZETTERLUND
  • Publication number: 20150008583
    Abstract: A method for fabricating packaged semiconductor devices; attaching a batch-sized metallic grid with openings onto an adhesive tape having an insulating clear core covered by a layer of UV-releasable adhesive, the openings sized larger than a semiconductor chip; attaching a semiconductor chip onto the tape of each window, the chip terminals facing the adhesive surface; laminating insulating material of low coefficient of thermal expansion to fill gaps between each chip and respective grid; turning over assembly to place a carrier under backside of chips and lamination and to remove the tape; plasma-cleaning the assembly front side and sputtering uniform at least one metal layer across the assembly; optionally plating metal layers; and patterning the metal layers to form rerouting traces and extended contact pads for assembly.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 8, 2015
    Inventor: Mark A. Gerber
  • Patent number: 8907486
    Abstract: A gate containing ruthenium for a dielectric having an oxide containing a lanthanide and a method of fabricating such a combination gate and dielectric produce a reliable structure for use in a variety of electronic devices. A ruthenium or a conductive ruthenium oxide gate may be formed on a lanthanide oxide. A ruthenium-based gate on a lanthanide oxide provides a gate structure that can effectively prevent a reaction between the gate and the lanthanide oxide.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: December 9, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8896136
    Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Publication number: 20140327142
    Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.
    Type: Application
    Filed: October 18, 2012
    Publication date: November 6, 2014
    Inventors: Walter A Harrison, Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Patent number: 8878363
    Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: November 4, 2014
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
  • Patent number: 8872342
    Abstract: A device including a dielectric layer overlying a substrate, a conductive line with a sidewall in the dielectric layer, a Ta layer adjoining the sidewall of the conductive line, and a metal oxide formed between the Ta layer and the dielectric layer.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Chi-Yu Chou, Kuei-Pin Lee, Chen-Kuang Lien, Yu-Chang Hsiao, Yao-Hsiang Liang, Yu-Min Chang
  • Patent number: 8872341
    Abstract: One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gerald Dallmann, Heike Rosslau, Norbert Urbansky, Scott Wallace
  • Publication number: 20140299994
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Application
    Filed: June 24, 2014
    Publication date: October 9, 2014
    Inventor: Kenichi Watanabe
  • Publication number: 20140299993
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Application
    Filed: June 24, 2014
    Publication date: October 9, 2014
    Inventor: Kenichi Watanabe
  • Patent number: 8853072
    Abstract: Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Philip J. Ireland
  • Patent number: 8836129
    Abstract: A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 16, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao
  • Publication number: 20140252629
    Abstract: Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a method for forming a metal wiring layer on a wafer includes the following steps. A copper layer is formed on the wafer. A patterned hardmask is formed on the copper layer. The copper layer is subtractively patterned using the patterned hardmask to form a plurality of first copper lines. Spacers are formed on opposite sides of the first copper lines. A planarizing dielectric material is deposited onto the wafer, filling spaces between the first copper lines. One or more trenches are etched in the planarizing dielectric material. The trenches are filled with copper to form a plurality of second copper lines that are self-aligned with the first copper lines. An electronic device is also provided.
    Type: Application
    Filed: August 21, 2013
    Publication date: September 11, 2014
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Eric A. Joseph, Hiroyuki Miyazoe
  • Publication number: 20140232000
    Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes conductive lines having sidewalls angled between about 45° to about 90° relative to a plane in which bottom surfaces of the conductive lines lie. A dielectric layer is formed over the conductive lines, where forming the dielectric layer after the conductive lines are formed mitigates damage to the dielectric layer, such as by not subjecting the dielectric layer to etching. The angled sidewalls of the conductive lines cause the dielectric layer to pinch off before an area between adjacent conductive lines is filled, thus establishing an air gap between adjacent conductive lines, where the air gap has a lower dielectric constant than the dielectric material. At least one of the substantially undamaged dielectric layer or the air gap serves to reduce parasitic capacitance within the semiconductor arrangement, which improves performance.
    Type: Application
    Filed: April 30, 2014
    Publication date: August 21, 2014
    Inventors: Chien-Hua Huang, Hsin-Chieh Yao, Chung-Ju Lee
  • Publication number: 20140203438
    Abstract: Methods and apparatuses for forming an under-bump metallization (UBM) pad above a dielectric layer are disclosed. The dielectric layer may be above a metal layer and comprises a first opening and a second opening surrounding the first opening, which divide the dielectric layer into a first area and a second area. An UBM pad extends into and fills the first opening of the dielectric layer, above the first area between the first opening and the second opening, and may further extends down at least partly into the second opening covering a part or the whole of the second opening of the dielectric layer. The UBM pad may further extend over a part of the second area of the dielectric layer if the UBM pad fills the whole of the second opening of the dielectric layer. A solder ball may be mounted on the UBM pad.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Jie Chen, Ying-Ju Chen
  • Patent number: 8786085
    Abstract: One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: July 22, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Mathias Vaupel, Rainer Steiner, Werner Robl, Jens Pohl, Joern Plagmann, Gottfried Beer
  • Patent number: 8766443
    Abstract: An anisotropic conductive film composition for bonding an electronic device may include a hydrogenated bisphenol A epoxy monomer represented by Formula 1 or a hydrogenated bisphenol A epoxy oligomer represented by Formula 2: where n may be an integer from 1 to about 50.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: July 1, 2014
    Assignee: Cheil Industries, Inc.
    Inventors: Arum Yu, Nam Ju Kim, Kyoung Soo Park, Young Woo Park, Joon Mo Seo, Kyung Il Sul, Dong Seon Uh, Hyun Min Choi
  • Publication number: 20140167268
    Abstract: A graphene and metal interconnect structure and methods of making the same are disclosed. The graphene is a multiple layer graphene structure that is grown using a graphene catalyst. The graphene forms an electrical connection between two or more VIAs or components, or a combination of VIAs and components. A VIA includes a fill metal, with at least a portion of the fill metal being surrounded by a barrier metal. A component may be a routing track, a clock signal source, a power source, an electromagnetic signal source, a ground terminal, a transistor, a macrocell, or a combination thereof. The graphene is grown, using a graphene catalyst, from both solid and liquid carbon sources using chemical vapor deposition (CVD) at a temperature between 300° C.-400° C. The graphene catalyst can be an elemental form of, or alloy including, nickel, palladium, ruthenium, iridium or copper.
    Type: Application
    Filed: December 17, 2012
    Publication date: June 19, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 8749064
    Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyoshi Maekawa, Kenichi Mori
  • Patent number: 8736057
    Abstract: A substrate having, on a base material, a barrier film for preventing copper diffusion containing one or more metal elements selected from tungsten, molybdenum and niobium, a metal element having a catalytic function in electroless plating such as platinum, gold, silver and palladium, and nitrogen contained in the form of a nitride of the aforementioned one or more metal elements selected from tungsten, molybdenum and niobium. The barrier film for preventing copper diffusion is manufactured by sputtering in a nitrogen atmosphere using a target containing one or more metal elements selected from tungsten, molybdenum and niobium and the aforementioned metal element having a catalytic function in electroless plating.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: May 27, 2014
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Junichi Ito, Atsushi Yabe, Junnosuke Sekiguchi, Toru Imori
  • Patent number: 8716122
    Abstract: To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: May 6, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takuro Honma, Yoshifumi Takata
  • Patent number: 8698313
    Abstract: A nonvolatile semiconductor memory apparatus according to an embodiment includes: a semiconductor layer; a first insulating film formed on the semiconductor layer, the first insulating film being a single-layer film containing silicon oxide or silicon oxynitride; a charge trapping film formed on the first insulating film; a second insulating film formed on the charge trapping film; and a control gate electrode formed on the second insulating film. A metal oxide exists in an interface between the first insulating film and the charge trapping film, the metal oxide comprises material which is selected from the group of Al2O3, HfO2, ZrO2, TiO2, and MgO, the material is stoichiometric composition, and the charge trapping film includes material different from the material of the metal oxide.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: April 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Izumi Hirano, Shosuke Fujii, Yuichiro Mitani, Naoki Yasuda
  • Patent number: 8691688
    Abstract: A method of processing a substrate is provided. The method includes: providing a substrate, wherein the substrate includes a silicon layer; etching the substrate to form a cavity; filling a first conductor in part of the cavity; performing a first thermal treatment on the first conductor; filling a second conductor in the cavity to fill-up the cavity; and performing a second thermal treatment on the first conductor and the second conductor.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: April 8, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Yu Chen, Yu-Han Tsai, Chun-Ling Lin, Ching-Li Yang, Home-Been Cheng
  • Patent number: 8673769
    Abstract: Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: March 18, 2014
    Assignee: Lam Research Corporation
    Inventors: John Boyd, Fritz Redeker, Yezdi Dordi, Hyungsuk Alexander Yoon, Shijian Li
  • Publication number: 20140042630
    Abstract: Aspects of the present invention relate to a controlled collapse chip connection (C4) structures. Various embodiments include a method of forming a controlled collapse chip connection (C4) structure. The method can include: providing a precursor structure including: a substrate, a dielectric over the substrate, the dielectric including a plurality of trenches exposing a portion of the substrate, and a metal layer over the dielectric and the portion of the substrate in each of the plurality of trenches, forming a resist layer over the metal layer, forming a rigid liner over a surface of the resist layer and the metal layer, and forming solder over the rigid liner between portions of the resist layer.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen P. Ayotte, Timothy H. Daubenspeck, David J. Hill, Glen E. Richard, Timothy M. Sullivan
  • Patent number: 8642468
    Abstract: Embodiments of the invention generally provide methods for depositing metal-containing materials and compositions thereof. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: February 4, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Seshadri Ganguli, Srinivas Gandikota, Yu Lei, Xinliang Lu, Sang Ho Yu, Hoon Kim, Paul F. Ma, Mei Chang, Maitreyee Mahajani, Patricia M. Liu
  • Publication number: 20140008804
    Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.
    Type: Application
    Filed: September 10, 2013
    Publication date: January 9, 2014
    Applicant: SanDisk Technologies, Inc.
    Inventors: Vinod R. Purayath, James K. Kai, Jayavel Pachamuthu, Jarrett Jun Liang, George Matamis
  • Publication number: 20130307155
    Abstract: A semiconductor device according to the present invention includes a semiconductor substrate, a surface electrode provided on a front surface of the semiconductor substrate through an insulating film, a via, passing through the semiconductor substrate from a rear surface thereof up to the front surface to reach the surface electrode, having a wall including a flange portion inwardly projecting on a front surface portion of the semiconductor substrate, a via insulating film formed on the wall of the via, and a through-electrode embedded inside the via insulating film and electrically connected to the surface electrode, while the via insulating film has portions having different thickness compensating for a step between the flange portion and the remaining portion of the wall, to planarize a contact surface with the through-electrode.
    Type: Application
    Filed: May 9, 2013
    Publication date: November 21, 2013
    Applicant: ROHM CO., LTD.
    Inventor: Toshiro MITSUHASHI
  • Patent number: 8587135
    Abstract: A semiconductor device has a conductive member coupled to the surface of a bonding pad exposed from an opening formed in a passivation film. A second planar distance between a first end of an electrode layer and a first end of a bonding pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the bonding pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the bonding pad.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: November 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tamaki Wada, Akihiro Tobita, Seiichi Ichihara
  • Patent number: RE45361
    Abstract: The object of the present invention is to embed an insulating film in a hole having a high aspect ratio and a small width without the occurrence of a void. The thickness of a polishing stopper layer is reduced by making separate layers respectively serve as a mask during forming the hole in a semiconductor substrate, and a stopper during removing the insulating film filled in the hole.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: February 3, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Toshiyuki Hirota
  • Patent number: RE47708
    Abstract: In a semiconductor device including a semiconductor element and a wiring substrate on which the semiconductor element is mounted. The wiring substrate includes an insulating substrate and conductive wiring formed in the insulating substrate and electrically connected to the semiconductor element. The conductive wiring includes an underlying layer formed on the insulating substrate, a main conductive layer formed on the underlying layer, and an electrode layer covering side surfaces of the underlying layer and side surfaces and an upper surface of the main conductive layer. The underlying layer includes an adhesion layer being formed in contact with the insulating substrate and containing an alloy of Ti.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: November 5, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Takuya Noichi, Yuichi Okada