At Least One Layer Containing Silver Or Copper Patents (Class 257/762)
  • Patent number: 11410946
    Abstract: A semiconductor apparatus including a bonding region in which a wire is bonded, includes: a semiconductor substrate; an oxide film provided on a principal surface of the semiconductor substrate in the bonding region; a polysilicon layer provided on the oxide film; an interlayer film partially provided on the polysilicon layer; a barrier metal directly provided on the polysilicon layer and the interlayer film; and an electrode provided on the barrier metal.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: August 9, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Hirata, Akihisa Yamamoto
  • Patent number: 11398405
    Abstract: A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Wen Wu, Chih-Yuan Ting, Jyu-Horng Shieh
  • Patent number: 11393753
    Abstract: An interconnection structure of an integrated circuit semiconductor device includes: a first conductive layer on a semiconductor substrate; an interlayer insulating layer on the first conductive layer and including a trench and a via hole; a via layer in the via hole, the via layer penetrating the interlayer insulating layer through a bottom of the trench to contact the first conductive layer, the via layer including a protrusion protruding to a height greater than a height of the trench; a barrier layer selectively on the bottom and sidewalls of the trench and on sidewalls of the via layer in the trench; a cap layer on a surface of the via layer; and a second conductive layer in the trench on the barrier layer. The cap layer is electrically connected to the first conductive layer through the via layer.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: July 19, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jungha Lee, Woojin Jang
  • Patent number: 11374118
    Abstract: A method to form a 3D integrated circuit, the method including: providing a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; providing a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; and then performing a face-to-face bonding of the second wafer on top of the first wafer, where the face-to-face bonding includes copper to copper bonding; and thinning the second crystalline substrate to a thickness of less than 5 micro-meters.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: June 28, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Zeev Wurman
  • Patent number: 11322464
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of bond pad structures over an interconnect structure on a front-side of a semiconductor body. The plurality of bond pad structures respectively have a titanium contact layer. The interconnect structure and the semiconductor body are patterned to define trenches extending into the semiconductor body. A dielectric fill material is formed within the trenches. The dielectric fill material is etched to expose the titanium contact layer prior to bonding the semiconductor body to a carrier substrate. The semiconductor body is thinned to expose the dielectric fill material along a back-side of the semiconductor body and to form a plurality of integrated chip die. The dielectric fill material is removed to separate the plurality of integrated chip die.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Julie Yang, Chii-Ming Wu, Tzu-Chung Tsai, Yao-Wen Chang
  • Patent number: 11296044
    Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 5, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Guilian Gao, Javier A. Delacruz, Shaowu Huang, Liang Wang, Gaius Gillman Fountain, Jr., Rajesh Katkar, Cyprian Emeka Uzoh
  • Patent number: 11276639
    Abstract: Integrated chips and methods of forming lines in the same include forming a line layer on a substrate. An opening is etched into the line layer that exposes the substrate. A plug is formed in the opening. The line layer is patterned to form a line that terminates at the plug.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: March 15, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert Robison
  • Patent number: 11251106
    Abstract: The invention discloses a packaging structure and manufacturing method of a SiC MOSFET module, which is composed of SiC MOSFET chips, upper DBC substrate, lower DBC substrate, ceramic interposer, silicon oxide dielectric layer, nano silver pastes, redistribution layer, through-ceramic-hole conductive metals and power terminals. The SiC MOSFET chips are connected to the lower DBC substrate using nano silver pastes in the invention. Besides, some rectangular frames are made on the ceramic interposer, and the SiC MOSFET chips are embedded in the ceramic interposer by filling dielectric materials. The upper surfaces of the chips and the ceramic interposer are covered with a conductive metal redistribution layer, and the upper and lower surfaces of the ceramic interposer are interconnected with the upper and lower DBC substrates, respectively. The power terminals are led out from the conductive copper layers of the upper and lower DBC substrates.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: February 15, 2022
    Assignee: BEIJING UNIVERSITY OF TECHNOLOGY
    Inventors: Fei Qin, Shuai Zhao, Yanwei Dai, Pei Chen, Tong An
  • Patent number: 11228124
    Abstract: In some embodiments, connecting a component to a substrate by adhesion to an oxidized solder surface includes: forming one or more conductive solder connections between the component and one or more conductive portions of the substrate; adhering the component to an oxidized surface of a solder portion applied to the substrate.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: January 18, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark K. Hoffmeyer, Steven P. Ostrander, Thomas Weiss, Thomas E. Lombardi
  • Patent number: 11216123
    Abstract: The present invention provides a conductive film in which a change in the surface state is suppressed and the light-fast adhesiveness of a protective layer is excellent, a touch panel sensor, and a touch panel. The conductive film according to the present invention includes a substrate, a patterned layer to be plated which is arranged on at least one surface of the substrate and has a functional group interacting with a plating catalyst or a precursor thereof, a copper plating layer which is arranged to cover the patterned layer to be plated and is in contact with the substrate, a metal layer which is arranged to cover the copper plating layer and contains a metal that is electrochemically nobler than copper, a nitrogen-containing compound layer which is arranged to cover the metal layer that is electrochemically nobler than copper, and a protective layer which is arranged to cover the nitrogen-containing compound layer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: January 4, 2022
    Assignee: FUJIFILM Corporation
    Inventors: Chika Matsuoka, Takahiko Ichiki
  • Patent number: 11211353
    Abstract: A clip for a semiconductor package and a semiconductor having a clip is disclosed. In one example, the clip includes a first planar portion, a plurality of first pillars, and a plurality of first solder balls. Each first pillar of the plurality of first pillars is coupled to the first planar portion. Each first solder ball of the plurality of first solder balls is coupled to a corresponding first pillar of the plurality of first pillars.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: December 28, 2021
    Assignee: Infineon Technologies AG
    Inventors: Mohd Kahar Bajuri, Abdul Rahman Mohamed, Siang Kuan Chua, Ke Yan Tean
  • Patent number: 11183381
    Abstract: A semiconductor device of the embodiment includes first and second conductive layer; a silicon nitride layer between the first conductive layer and the second conductive layer; a silicon oxide layer between the silicon nitride layer and the second conductive layer; a silicon oxynitride layer between the silicon oxide layer and the second conductive layer; and a third conductive layer between the first conductive layer and the second conductive layer, the third conductive layer electrically connected to the first and second conductive layer, a first tilt angle of a plane where the third conductive layer is in contact with the silicon oxynitride layer with respect to an interface between the silicon nitride layer and the silicon oxide layer is smaller than a second tilt angle of a plane where the third conductive layer is in contact with the silicon oxide layer with respect to the interface.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 23, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Masaki Yamada
  • Patent number: 11177221
    Abstract: A semiconductor device package includes a first carrier, a first electronic component, a second electronic component, a second carrier and an electrical connection structure. The first carrier has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface of the first carrier. The second electronic component is disposed on the second surface of the first carrier. The second carrier has a first surface facing the second surface of the first carrier and a second surface opposite to the first surface. The electrical connection structure is electrically connecting the first carrier with the second carrier.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 16, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Hua Tai, Yueh-Ju Lin, Wen Shang Chang, Wen-Pin Huang
  • Patent number: 11171258
    Abstract: A method for manufacturing a radiation-emitting semiconductor device and radiation-emitting semiconductor device are disclosed. In an embodiment a method includes providing a radiation-emitting semiconductor chip having a first main surface including a radiation exit surface of the semiconductor chip, applying a metallic seed layer to a second main surface of the semiconductor chip opposite to the first main surface, galvanically depositing a first metallic layer on the seed layer for forming a first electrical contact point and a second electrical contact point, galvanically depositing a second metallic layer on the first metallic layer for forming the first electrical contact point and the second electrical contact point, wherein a material of the first metallic layer and a material of the second metallic layer are different, and applying a casting compound between the contact points.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: November 9, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Christian Leirer, Isabel Otto
  • Patent number: 11152317
    Abstract: A semiconductor device and a semiconductor package, the device including a pad interconnection structure that penetrates a first buffer dielectric layer and a second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin, the pad interconnection structure includes a central part, a first intermediate part surrounding the central part; a second intermediate part surrounding the first intermediate part, and an outer part surrounding the second intermediate part, a grain size of the outer part is less than a grain size of the second intermediate part, the grain size of the second intermediate part is less than a grain size of the first intermediate part, and the grain size of the first intermediate part is less than a grain size of the central part.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Il Choi, Pil-Kyu Kang, Hoechul Kim, Hoonjoo Na, Jaehyung Park, Seongmin Son
  • Patent number: 11145600
    Abstract: An electronic device is provided. The electronic device includes a first substrate. The electronic device also includes a multilayer electrode disposed on the first substrate. The multilayer electrode includes a first conductive layer, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. The electronic device further includes a second substrate facing the first substrate. In addition, the electronic device includes a working medium disposed between the first substrate and the second substrate. The chemical electromotive force of the second conductive layer is between that of the first conductive layer and the third conductive layer.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: October 12, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Chi Ho, Ming-Yen Weng, I-Yin Li
  • Patent number: 11121104
    Abstract: A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Chih-Wei Lin, Ming-Da Cheng, Chih-Hang Tung, Chung-Shi Liu
  • Patent number: 11107855
    Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 31, 2021
    Assignee: SONY CORPORATION
    Inventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
  • Patent number: 11094789
    Abstract: Embodiments of the present disclosure disclose a thin film transistor, a method for manufacturing a thin film transistor, an array substrate, and a display device. The thin film transistor includes a source electrode and a drain electrode, each of the source electrode and the drain electrode including a metal substrate and a conductive layer covering the metal substrate. An adhesion between the conductive layer and a photoresist material is larger than an adhesion between the metal substrate and the photoresist material. The metal substrate and the conductive layer are both formed on a base substrate, an orthographic projection of the conductive layer on the base substrate covers an orthographic projection of the metal substrate on the base substrate, and. an area of the orthographic projection of the conductive layer on the base substrate is larger than an area of the orthographic projection of the metal substrate on the base substrate.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 17, 2021
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaolong Li, Jinchao Bai, Huibin Guo, Xiao Han, Yongzhi Song
  • Patent number: 11088252
    Abstract: An alternating stack of insulating layers and spacer material layers is formed located over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack. A memory stack structure is formed within each memory opening. Each memory stack structure includes a memory film and a vertical semiconductor channel. A silicon nitride layer is formed over a sidewall of each memory opening as a component of the memory film. A silicon carbon nitride interfacial layer is formed on the silicon nitride layer, and a tunneling dielectric layer is formed on the silicon carbon nitride interfacial layer.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: August 10, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Yuki Kasai
  • Patent number: 11069788
    Abstract: To provide a semiconductor device including an electrode having a low contact resistance with the back surface of a GaN substrate and being suitably bonded with solder, and having a low electric resistance of the current flowing in a vertical direction. The semiconductor device has a GaN substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a body electrode, a drain electrode, a source electrode, and a gate electrode. The drain electrode has a Ti layer, an Al layer, a Ti layer, a TiN layer, a Ti layer, a Ni layer, and an Ag layer sequentially from the second surface of the GaN substrate.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: July 20, 2021
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Noriaki Murakami, Toru Oka
  • Patent number: 11063010
    Abstract: Provided is a redistribution layer (RDL) structure including a substrate, a pad, a dielectric layer, a self-aligned structure, a conductive layer, and a conductive connector. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The self-aligned structure is disposed on the dielectric layer. The conductive layer extends from the pad to conformally cover a surface of the self-aligned structure. The conductive connector is disposed on the self-aligned structure. A method of manufacturing the RDL structure is also provided.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: July 13, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Yen-Jui Chu, Jin-Neng Wu, Hsin-Hung Chou, Chun-Hung Lin
  • Patent number: 11050050
    Abstract: Provided are an electrolytic copper foil, an electrode, and a lithium-ion cell. The electrolytic copper foil comprising copper and chloride is analyzed by TOF-SIMS along its thickness direction to obtain a spectrum of a relative depth ratio as X-axis and a relative intensity of chloride versus copper as Y-axis. There is a chloride peak located between 20% and 80% of the relative depth ratio in the spectrum, and the chloride peak is characterized by a maximum relative intensity of chloride versus copper ranging from 0.77% to 5.13% and a full width at half maximum ranging from 2.31% to 5.78%. With above characteristics, the electrolytic copper foil has low density of copper particles, low degree of warpage, and good coating uniformity of the active material applied thereon, thereby optimizing the efficiency of a lithium-ion cell comprising the electrolytic copper foil.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: June 29, 2021
    Assignee: CHANG CHUN PETROCHEMICAL CO., LTD.
    Inventors: Ting-Chun Lai, Yao-Sheng Lai, Jui-Chang Chou
  • Patent number: 11004739
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani
  • Patent number: 10998478
    Abstract: A light-emitting element according to an embodiment comprises: a substrate; a light-emitting structure comprising a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, which are successively arranged on the substrate; and first and second electrodes, which are electrically connected to the first and second conductive semiconductor layers, respectively, wherein the first electrode comprises at least one first contact portion arranged on the first conductive semiconductor layer, which is exposed to at least a part of a first area of the light-emitting structure, and connected to the first conductive semiconductor layer, and a plurality of second contact portions connected to the first conductive semiconductor layer that is exposed in a second area, which is positioned, on a plane, closer to the inner side than the first area of the light-emitting structure, and the second electrode comprises a third contact part, which is arranged in the second area of the light-emitt
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: May 4, 2021
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Ji Hyung Moon, Woo Sik Lim
  • Patent number: 10950728
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure and an S/D contact structure formed over the fin structure. The FinFET device structure also includes an S/D conductive plug formed over the S/D contact structure, and the S/D conductive plug includes a first barrier layer and a first conductive layer. The FinFET device structure includes a gate contact structure formed over the gate structure, and the gate contact structure includes a second barrier layer and a second conductive layer. The FinFET device structure includes a first isolation layer surrounding the S/D conductive plug, and the first barrier layer is between the first isolation layer and the first conductive layer. A second isolation layer surrounding the gate contact structure, and the second barrier layer is between the second isolation layer and the second conductive layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Huai Chang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang
  • Patent number: 10937875
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, drain electrodes, a drain interconnect portion, and a drain conductive portion. The semiconductor member includes first and second semiconductor regions. The drain electrodes extend along a first direction, are arranged in a second direction crossing the first direction, and are provided at the first semiconductor region. A direction from the first semiconductor region toward the second semiconductor region is aligned with the first direction. The drain interconnect portion extends along the second direction and is electrically connected to the drain electrodes. The drain conductive portion is electrically connected to the drain interconnect portion. The drain conductive portion includes first and second conductive regions. A portion of the drain interconnect portion is between the first conductive region and the first semiconductor region in a third direction.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 2, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kajiwara, Aya Shindome, Masahiko Kuraguchi
  • Patent number: 10930580
    Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Sen-Bor Jan, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 10896865
    Abstract: A power electronics module includes a power electronics device, and an electrically-conductive substrate directly coupled to the power electronics device, the electrically-conductive substrate defining a plurality of channels extending through the electrically-conductive substrate, and a plurality of electrical pathways extending through the electrically-conductive substrate around the plurality of channels.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: January 19, 2021
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Shailesh N. Joshi, Naoya Take, Ercan Mehmet Dede, Yanghe Liu
  • Patent number: 10879144
    Abstract: A semiconductor package includes a semiconductor die including an active side, a redistribution layer over the active side of the semiconductor die, the redistribution layer including metal traces electrically connecting die pads on the active side of the semiconductor die to electrical contacts on an external surface of the semiconductor package, and a layered mold covering the semiconductor die opposite the redistribution layer. The layered mold includes a first resin layer adjacent to the redistribution layer, a fiber layer adjacent to the first resin layer and opposite the redistribution layer, and a second resin layer adjacent to the fiber layer and opposite the redistribution layer. A coefficient of thermal expansion (CTE) of the first resin layer is substantially different than a CTE of the second resin layer.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kengo Aoya, Masamitsu Matsuura, Takeshi Onogami, Hideaki Matsunaga
  • Patent number: 10868040
    Abstract: An integrated circuit device includes a first insulating film, a second insulating film provided on the first insulating film, and having a composition different from a composition of the first insulating film, a first interconnect extending in a first direction crossing a vertical direction, and having a lower portion disposed in the first insulating film, and an upper portion disposed in the second insulating film, and a second interconnect extending in the first direction, and having a lower portion disposed in the first insulating film, and an upper portion disposed in the second insulating film. An air gap is formed in the first insulating film and in the second insulating film and also between the first interconnect and the second interconnect. A lower end of the air gap is located lower than a lower surface of the first interconnect and a lower surface of the second interconnect.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: December 15, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Masayoshi Tagami
  • Patent number: 10847621
    Abstract: Supposing x is defined as a position of an end of a depletion layer extending when a rated voltage V [V] is applied to a rear surface electrode, W1 is defined as a distance between the position x and an outer peripheral edge of a surface electrode in an outer peripheral direction, W2 is defined as a distance between the position x and an outer peripheral edge of a field insulating film in the outer peripheral direction, t [?m] is defined as a film thickness t [?m] of the field insulating film, a layout of a terminal part is defined so that an electrical field in the field insulating film at the position x expressed as W2V/t(W1+W2) is 3 MV/cm or smaller.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: November 24, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kohei Ebihara, Hiroshi Watanabe
  • Patent number: 10790334
    Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: September 29, 2020
    Assignee: Unity Semiconductor Corporation
    Inventor: Bruce Lynn Bateman
  • Patent number: 10763211
    Abstract: A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Han Lee, Shau-Lin Shue
  • Patent number: 10734338
    Abstract: The present disclosure relates to a multi-ring bonding pad, a semiconductor structure having the multi-ring bonding pad, and a method of manufacturing the semiconductor structure. The bonding pad includes an inner ring member, an outer ring member, and multiple bridge members. The inner ring member has a pair of first inner edges opposite to each other, a pair of second inner edges opposite to each other, and multiple third inner edges for connecting the first inner edges to the second inner edges. The outer ring member surrounds the inner ring member and has a pair of first outer edges opposite to each other, a pair of second outer edges opposite to each other, and multiple third outer edges for connecting the first outer edges to the second outer edges. The bridge members are disposed between the inner ring member and the outer ring member for connecting the inner ring member to the outer ring member.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: August 4, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Pei-Jhen Wu, Chiang-Lin Shih, Hsih-Yang Chiu
  • Patent number: 10707168
    Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Amruthavalli Pallavi Alur, Sri Ranga Sai Boyapati, Robert Alan May, Islam A. Salama, Robert L. Sankman
  • Patent number: 10700029
    Abstract: A semiconductor package device includes a first conductive structure, a second conductive structure and a dielectric layer. The first conductive structure has a tapered portion. The second conductive structure surrounds the tapered portion of the first conductive structure and is in direct contact with a side wall of the tapered portion of the first conductive structure. The dielectric layer surrounds the tapered portion of the first conductive structure and is in direct contact with the side wall of the tapered portion of the first conductive structure.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: June 30, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10679936
    Abstract: Disclosed is a method of manufacturing a three dimensional (3D) metal-insulator-metal (MIM) capacitor in the back end of line, which can provide large and tunable capacitance values and meanwhile, does not interfere with the existing BEOL fabrication process.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun huan Wei, Pin Yu Hsu, Szu-Yuan Chen, Po-June Chen, Kuan-Yu Chen
  • Patent number: 10643967
    Abstract: An electrode is disposed on a semiconductor layer. A polyimide layer has an opening disposed on the electrode, covers the edge of the electrode, and extends onto the electrode. A copper layer is disposed on the electrode within the opening, and located away from the polyimide layer on the electrode. A copper wire has one end joined on the copper layer.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 5, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroaki Okabe, Yosuke Nakanishi
  • Patent number: 10643942
    Abstract: A method to produce a substrate suitable for diffusion bonding is described. A flexible dielectric substrate is provided. An alkaline modification is applied to the dielectric substrate to form a polyamic acid (PAA) anchoring layer on a surface of the dielectric substrate. A Ni—P seed layer is electrolessly plated on the PAA layer. Copper traces are plated within a photoresist pattern on the Ni—P seed layer. A surface finishing layer is electrolytically plated on the copper traces. The photoresist pattern and Ni—P seed layer not covered by the copper traces are removed to complete the substrate suitable for diffusion bonding.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: May 5, 2020
    Assignee: Compass Technology Company Limited
    Inventors: Kelvin Po Leung Pun, Chee Wah Cheung
  • Patent number: 10622314
    Abstract: A chip package structure includes a substrate, a die, a plurality of warpage retainers, and an encapsulant. The substrate has a surface, on which the die is provided. The warpage retainers are provided at at least one corner of the substrate. The encapsulant covers the surface of the substrate, the die and the warpage retainers.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: April 14, 2020
    Assignee: MEDIATEK INC.
    Inventor: You-Wei Lin
  • Patent number: 10615137
    Abstract: A method of manufacturing a bond pad structure may include depositing an aluminum-copper (Al—Cu) layer over a dielectric layer; and depositing an aluminum-chromium (Al—Cr) layer directly over the Al—Cu layer.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Jeffrey P. Gambino, Charles F. Musante, Christopher D. Muzzy, Wolfgang Sauter
  • Patent number: 10553475
    Abstract: An integrated circuit packaging is described, including a plurality of electrical circuits developed using a first patterned conductive layer on a base, wherein an electrical circuit is formed by using a masking material, and an interconnection is developed between the electrical circuits, where the interconnection is disposed on at least one side of the first patterned conductive layer and masking material, in which the interconnection is enclosed with a second masking material to form the integrated circuit packaging.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: February 4, 2020
    Assignee: QDOS Flexcircuits Sdn Bhd
    Inventors: Zalina Binti Abdullah, Roslan Bin Ahmad, Poh Cheng Ang, Poh Choon Whong, Hai San Tew, Shin Hung Hwang, Chee Can Lee, Tiyagarajan S/O Arumugham
  • Patent number: 10538846
    Abstract: The present disclosure relates to an etching solution composition for a tungsten layer including N-methylmorpholine N-oxide and water, which is effective in selectively etching only a tungsten-based metal without etching a titanium nitride-based metal or a titanium aluminum carbide layer.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: January 21, 2020
    Assignee: Dongwoo Fine-Chem Co., Ltd.
    Inventors: Seong-Min Kim, Yong-Jun Cho, Kyong-Ho Lee
  • Patent number: 10529602
    Abstract: Methods and apparatuses for substrate fabrication are provided herein.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: January 7, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Priyadarshi Panda, Gill Lee, Srinivas Gandikota, Sung-Kwan Kang, Sanjay Natarajan
  • Patent number: 10510845
    Abstract: The invention disclosed a method for manufacturing an electrode of a semiconductor device, comprising: forming a first interlayer dielectric layer having a first opening on a first surface of a semiconductor substrate; forming a first resist mask having a second opening on a surface of the first interlayer dielectric layer, wherein the first opening and the second opening are connected to form a first stacked opening; forming a first conductive layer on the first resist mask, wherein the first conductive layer comprises a first portion being located on a surface of the first resist mask and a second portion being located inside the first stacked opening; and removing the first resist mask, wherein the first portion of the first conductive layer is removed together with the first resist mask, and the second portion of the first conductive layer is retained as a first surface electrode.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: December 17, 2019
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventors: Dengping Yin, Shijun Wang, Fei Yao
  • Patent number: 10510658
    Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: December 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eui Bok Lee, Deok Young Jung, Sang Bom Kang, Doo-Hwan Park, Jong Min Baek, Sang Hoon Ahn, Hyeok Sang Oh, Woo Kyung You
  • Patent number: 10504938
    Abstract: The present application provides an array substrate and a method of manufacturing the same. The array substrate includes a first substrate having a drain electrode protruding from a side of the first substrate; a planarization layer at the side of the first substrate where the drain electrode protrudes, the planarization layer being provided with a stepped hole on the drain electrode, and a diameter of the stepped hole decreasing along a direction from a side of the planarization layer facing away the first substrate towards a side of the planarization layer facing the first substrate; a pixel electrode at the stepped hole and connected with the drain electrode; a passivation layer covering the planarization layer and the pixel electrode; and a common electrode on the passivation layer.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 10, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Yuelin Wang, Yanyan Zhao, Jingyi Xu, Lei Li, Yezhou Fang, Tienan Liu, Yanwei Ren, Yishan Fu, Weida Qin
  • Patent number: 10468269
    Abstract: Interconnect structures and processes generally include creating point defects in exposed surfaces of the dielectric layer to create a point defect region at a relatively shallow depth, wherein the point defect region is a fraction of the dielectric layer and is created with exposure to silicon, carbon, nitrogen, oxygen, or mixtures thereof such that the point defect region contains Si, C, N O, or mixtures containing at least one of the foregoing. A seed layer can be deposited and includes at least one alloying element that is effective to form an in situ self-aligned liner layer with the Si, C, N O, or mixtures containing at least one of the foregoing within the point defect region, which is formed at a depth of less than 10 nanometers. The in situ liner layer within the dielectric layer maximizes the volume fraction of the conductor of the interconnect structure.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: November 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chih-Chao Yang
  • Patent number: 10468370
    Abstract: There is provided a bonding wire for a semiconductor device including a coating layer having Pd as a main component on a surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on a surface of the coating layer, the bonding wire further improving 2nd bondability on a Pd-plated lead frame and achieving excellent ball bondability even in a high-humidity heating condition. The bonding wire for a semiconductor device including the coating layer having Pd as a main component on the surface of the Cu alloy core material and the skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing either or both of Pd and Pt in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in the 2nd bondability and excellent ball bondability in the high-humidity heating condition.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: November 5, 2019
    Assignees: NIPPON MICROMETAL CORPORATION, NIPPON STEEL CHEMICAL & MATERIAL CO., LTD.
    Inventors: Takashi Yamada, Daizo Oda, Ryo Oishi, Tomohiro Uno