Abstract: A metal-dielectric bonding method includes providing a first semiconductor structure including a first semiconductor layer, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, where the first metal layer has a metal bonding surface facing away from the first semiconductor layer; planarizing the metal bonding surface; applying a plasma treatment on the metal bonding surface; providing a second semiconductor structure including a second semiconductor layer, and a second dielectric layer on the second semiconductor layer, where the second dielectric layer has a dielectric bonding surface facing away from the second semiconductor layer; planarizing the dielectric bonding surface; applying a plasma treatment on the dielectric bonding surface; and bonding the first semiconductor structure with the second semiconductor structure by bonding the metal bonding surface with the dielectric bonding surface.

Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation.

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

Abstract: A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located

Abstract: A method for manufacturing a display panel includes: sequentially forming a conductive pattern, a light-emitting layer and a cathode layer on a substrate. The conductive pattern is formed by a one-time patterning process, and includes an auxiliary electrode layer. In a direction parallel to the substrate, both the first protective electrode and the second protective electrode in the auxiliary electrode layer extend over the metal electrode, a second orthographic projection of the second protective electrode on the substrate is within a first orthographic projection of the first protective electrode on the substrate, and an outer boundary of the second orthographic projection is staggered from an outer boundary of the first orthographic projection. The cathode layer is in contact with the first protective electrode and a sidewall of the metal electrode.

Abstract: There is provided a semiconductor device including: a semiconductor element; a support substrate configured to support the semiconductor element; an intermediate metal layer interposed between the semiconductor element and the support substrate in a thickness direction of the support substrate, wherein the semiconductor element and the intermediate metal layer are bonded by solid phase diffusion bonding; and a first positioning portion including a portion of the semiconductor element and a first portion of the intermediate metal layer and configured to suppress relative movement between the semiconductor element and the intermediate metal layer.

Abstract: The disclosed subject matter relates generally to methods of forming a semiconductor device, such as a moisture sensor. A plurality of electrodes and a bond pad are formed in a dielectric region. A passivation layer is formed on each electrode in the plurality of electrodes and the bond pad. A barrier layer is formed on the passivation layer. A plurality of trenches are formed to extend through the barrier layer and into the dielectric region. Formation of the trenches simultaneously exposes an upper surface of the bond pad. A moisture sensitive dielectric layer is formed on the barrier layer. Formation of the moisture sensitive dielectric layer also fills the trenches to form a plurality of projections, each projection being formed between two electrodes in the plurality of electrodes.

Abstract: A leadframe is formed by chemically half-etching a sheet of conductive material. The half-etching exposes a first side surface of a first contact of the leadframe. A solder wettable layer is plated over the first side surface of the first contact. An encapsulant is deposited over the leadframe after plating the solder wettable layer.

Abstract: A method of fabricating an IC device is disclosed, in which a dielectric layer is first etched to form a contact opening and a dummy opening. Both do not extend through the dielectric layer, the contact opening has a width greater than that of the dummy opening. A sacrificial layer, which covers inner surface of the dummy opening and the dielectric layer at side surface of the contact opening, and from which the dielectric layer at bottom surface of the contact opening is exposed, is then formed, and under protection of this sacrificial layer, the dielectric layer exposed in the contact opening is etched in a self-aligned manner, a self-aligned contact hole is formed, in which a surface of the conductive structure is exposed. In this way, reliability of a contact that extends in both contact opening and self-aligned contact hole is ensured, avoiding the problem of possible contact failure.

Abstract: Disclosed are semiconductor devices including through vias and methods of fabricating the same. The methods may include forming a first structure including a metal pattern and a second structure on the first structure. The metal pattern includes an upper surface facing the second structure. The methods may also include etching the second structure to form a via hole exposing the metal pattern, oxidizing a first etch residue in the via hole to convert the first etch residue into an oxidized first etch residue, and removing the oxidized first etch residue. After removing the oxidized first etch residue, the upper surface of the metal pattern may include a first portion that includes a recess and has a first surface roughness and a second portion that is different from the first portion and has a second surface roughness. The first surface roughness may be greater than the second surface roughness.

Abstract: A display panel is provided. The display panel includes a bank layer and a quantum dots material layer on a base substrate. The bank layer defines a plurality of bank apertures. The quantum dots material layer includes a plurality of quantum dots blocks respectively in at least some of the plurality of bank apertures. At least a portion of the bank layer between two adjacent bank apertures includes a first surface, a second surface opposite to the first surface, a third surface connecting the first surface and the second surface closer to a first bank aperture, and a fourth surface connecting the first surface and the second surface closer to a second bank aperture. At least a portion of a third surface or a fourth surface of a portion of the bank layer between two adjacent bank apertures is a wavy surface including alternating convex and concave portions.

Abstract: Examples herein include die to metallization structure connections that eliminate the solder joint to reduce the resistance and noise on the connection. In one example, a first die is attached to a metallization layer by a plurality of copper interconnections and a second is attached to the metallization layer opposite the first die through another plurality of copper interconnections. In this example, the copper interconnects may connect the respective die to a metallization structure in the metallization layer.

Abstract: A cavity may be formed in a dielectric material layer overlying a substrate. A layer stack including a metallic barrier liner, a metallic fill material layer, and a metallic capping material may be deposited in the cavity and over the dielectric material layer. Portions of the layer stack located above a horizontal plane including a top surface of the dielectric material layer may be removed. A contiguous set of remaining material portions of the layer stack includes a metal interconnect structure that is free of a pitted surface.

Abstract: There is set forth herein a photonics device. The photonics device can comprise a substrate, a conductive material formation, a dielectric stack, and a barrier layer. The photonics device can transmit a light signal.

Abstract: A semiconductor package includes: a first structure having a first insulating layer disposed on one surface, and first electrode pads and first dummy pads penetrating through the first insulating layer, a second structure having a second insulating layer having the other surface bonded to the one surface and the first insulating layer and disposed on the other surface, and second electrode pads and second dummy pads that penetrate through the second insulating layer, the second electrode pads being bonded to the first electrode pads, respectively, and the second dummy pads being bonded to the first dummy pads, respectively. In the semiconductor chip, ratios of surface areas per unit area of the first and second dummy pads to the first and second insulating layers on the one surface and the other surface gradually decrease toward sides of the first and second structures.

Abstract: Provided is a circuit structure including a substrate, a pad, a dielectric layer, a conductive layer, an adhesion layer, and a conductive bump. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The conductive layer contacts the pad and extends from the pad to cover a top surface of the dielectric layer. The adhesion layer is disposed between the dielectric layer and the conductive layer. The conductive bump extends in an upward manner from a top surface of the conductive layer. The conductive bump and the conductive layer are integrally formed. A method of manufacturing the circuit structure is also provided.

Abstract: Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

Abstract: A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.

Abstract: A bonding structure is provided. The bonding structure includes a conductive layer, a seed layer, and a nanotwinned copper (NT-Cu) layer. The seed layer is disposed on the conductive layer. The NT-Cu layer is disposed on the seed layer. The NT-Cu layer has anisotropic crystal structure.

Abstract: A printed circuit board according to an embodiment includes: an insulating layer; and a circuit pattern disposed on the insulating layer, wherein the circuit pattern includes an upper surface, a lower surface, a first side surface, and a second side surface, and surface roughness Ra of at least three surfaces of the upper surface, the lower surface, the first side surface, and the second side surface of the circuit pattern is 0.1 ?m to 0.31 ?m.

Abstract: The disclosure provides a display panel, a manufacturing method thereof, and a display device. The display panel includes a substrate layer, a gate layer, an insulating layer, and an active layer. The gate layer is disposed on the substrate layer and includes a first gate layer and a second gate layer. The second gate layer is disposed on a surface of the first gate layer. The insulating layer covers the gate layer and the substrate layer. The active layer is disposed on a surface of the insulating layer away from the gate layer. The active layer includes a first layer section and a second layer section connected to the first layer section, and a surface of the second layer section is above a surface of the first section layer.

Abstract: Embodiments of the invention include a stacked die system and methods for forming such systems. In an embodiment, the stacked die system may include a first die. The first die may include a device layer and a plurality of routing layers formed over the device layer. The plurality of routing layers may be segmented into a plurality of sub regions. In an embodiment no conductive traces in the plurality of routing layers pass over a boundary between any of the plurality of sub regions. In an embodiment, the stacked die system may also include a plurality of second dies stacked over the first die. According to an embodiment, at least a two of the second dies are communicatively coupled to each other by a die to die interconnect formed entirely within a single sub region in the first die.

Abstract: In sonic examples, a method includes pre-stressing a flange, heating the flange to a die-attach temperature, and attaching a die to the flange at the die-attach temperature using a die-attach material. In some examples, the flange includes a metal material, the die-attach temperature may be at least two hundred degrees Celsius, and the die-attach material may include solder and/or an adhesive. In some examples, the method includes cooling the semiconductor die and metal flange to a room temperature after attaching the semiconductor die to the metal flange at the die-attach temperature using a die-attach material.

Abstract: A semiconductor apparatus including a bonding region in which a wire is bonded, includes: a semiconductor substrate; an oxide film provided on a principal surface of the semiconductor substrate in the bonding region; a polysilicon layer provided on the oxide film; an interlayer film partially provided on the polysilicon layer; a barrier metal directly provided on the polysilicon layer and the interlayer film; and an electrode provided on the barrier metal.

Abstract: A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

Abstract: An interconnection structure of an integrated circuit semiconductor device includes: a first conductive layer on a semiconductor substrate; an interlayer insulating layer on the first conductive layer and including a trench and a via hole; a via layer in the via hole, the via layer penetrating the interlayer insulating layer through a bottom of the trench to contact the first conductive layer, the via layer including a protrusion protruding to a height greater than a height of the trench; a barrier layer selectively on the bottom and sidewalls of the trench and on sidewalls of the via layer in the trench; a cap layer on a surface of the via layer; and a second conductive layer in the trench on the barrier layer. The cap layer is electrically connected to the first conductive layer through the via layer.

Abstract: A method to form a 3D integrated circuit, the method including: providing a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; providing a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; and then performing a face-to-face bonding of the second wafer on top of the first wafer, where the face-to-face bonding includes copper to copper bonding; and thinning the second crystalline substrate to a thickness of less than 5 micro-meters.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of bond pad structures over an interconnect structure on a front-side of a semiconductor body. The plurality of bond pad structures respectively have a titanium contact layer. The interconnect structure and the semiconductor body are patterned to define trenches extending into the semiconductor body. A dielectric fill material is formed within the trenches. The dielectric fill material is etched to expose the titanium contact layer prior to bonding the semiconductor body to a carrier substrate. The semiconductor body is thinned to expose the dielectric fill material along a back-side of the semiconductor body and to form a plurality of integrated chip die. The dielectric fill material is removed to separate the plurality of integrated chip die.

Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation.

Abstract: Integrated chips and methods of forming lines in the same include forming a line layer on a substrate. An opening is etched into the line layer that exposes the substrate. A plug is formed in the opening. The line layer is patterned to form a line that terminates at the plug.

Abstract: The invention discloses a packaging structure and manufacturing method of a SiC MOSFET module, which is composed of SiC MOSFET chips, upper DBC substrate, lower DBC substrate, ceramic interposer, silicon oxide dielectric layer, nano silver pastes, redistribution layer, through-ceramic-hole conductive metals and power terminals. The SiC MOSFET chips are connected to the lower DBC substrate using nano silver pastes in the invention. Besides, some rectangular frames are made on the ceramic interposer, and the SiC MOSFET chips are embedded in the ceramic interposer by filling dielectric materials. The upper surfaces of the chips and the ceramic interposer are covered with a conductive metal redistribution layer, and the upper and lower surfaces of the ceramic interposer are interconnected with the upper and lower DBC substrates, respectively. The power terminals are led out from the conductive copper layers of the upper and lower DBC substrates.

Abstract: In some embodiments, connecting a component to a substrate by adhesion to an oxidized solder surface includes: forming one or more conductive solder connections between the component and one or more conductive portions of the substrate; adhering the component to an oxidized surface of a solder portion applied to the substrate.

Abstract: The present invention provides a conductive film in which a change in the surface state is suppressed and the light-fast adhesiveness of a protective layer is excellent, a touch panel sensor, and a touch panel. The conductive film according to the present invention includes a substrate, a patterned layer to be plated which is arranged on at least one surface of the substrate and has a functional group interacting with a plating catalyst or a precursor thereof, a copper plating layer which is arranged to cover the patterned layer to be plated and is in contact with the substrate, a metal layer which is arranged to cover the copper plating layer and contains a metal that is electrochemically nobler than copper, a nitrogen-containing compound layer which is arranged to cover the metal layer that is electrochemically nobler than copper, and a protective layer which is arranged to cover the nitrogen-containing compound layer.

Abstract: A clip for a semiconductor package and a semiconductor having a clip is disclosed. In one example, the clip includes a first planar portion, a plurality of first pillars, and a plurality of first solder balls. Each first pillar of the plurality of first pillars is coupled to the first planar portion. Each first solder ball of the plurality of first solder balls is coupled to a corresponding first pillar of the plurality of first pillars.

Abstract: A semiconductor device of the embodiment includes first and second conductive layer; a silicon nitride layer between the first conductive layer and the second conductive layer; a silicon oxide layer between the silicon nitride layer and the second conductive layer; a silicon oxynitride layer between the silicon oxide layer and the second conductive layer; and a third conductive layer between the first conductive layer and the second conductive layer, the third conductive layer electrically connected to the first and second conductive layer, a first tilt angle of a plane where the third conductive layer is in contact with the silicon oxynitride layer with respect to an interface between the silicon nitride layer and the silicon oxide layer is smaller than a second tilt angle of a plane where the third conductive layer is in contact with the silicon oxide layer with respect to the interface.

Abstract: A semiconductor device package includes a first carrier, a first electronic component, a second electronic component, a second carrier and an electrical connection structure. The first carrier has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface of the first carrier. The second electronic component is disposed on the second surface of the first carrier. The second carrier has a first surface facing the second surface of the first carrier and a second surface opposite to the first surface. The electrical connection structure is electrically connecting the first carrier with the second carrier.

Abstract: A method for manufacturing a radiation-emitting semiconductor device and radiation-emitting semiconductor device are disclosed. In an embodiment a method includes providing a radiation-emitting semiconductor chip having a first main surface including a radiation exit surface of the semiconductor chip, applying a metallic seed layer to a second main surface of the semiconductor chip opposite to the first main surface, galvanically depositing a first metallic layer on the seed layer for forming a first electrical contact point and a second electrical contact point, galvanically depositing a second metallic layer on the first metallic layer for forming the first electrical contact point and the second electrical contact point, wherein a material of the first metallic layer and a material of the second metallic layer are different, and applying a casting compound between the contact points.

Abstract: A semiconductor device and a semiconductor package, the device including a pad interconnection structure that penetrates a first buffer dielectric layer and a second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin, the pad interconnection structure includes a central part, a first intermediate part surrounding the central part; a second intermediate part surrounding the first intermediate part, and an outer part surrounding the second intermediate part, a grain size of the outer part is less than a grain size of the second intermediate part, the grain size of the second intermediate part is less than a grain size of the first intermediate part, and the grain size of the first intermediate part is less than a grain size of the central part.

Abstract: An electronic device is provided. The electronic device includes a first substrate. The electronic device also includes a multilayer electrode disposed on the first substrate. The multilayer electrode includes a first conductive layer, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. The electronic device further includes a second substrate facing the first substrate. In addition, the electronic device includes a working medium disposed between the first substrate and the second substrate. The chemical electromotive force of the second conductive layer is between that of the first conductive layer and the third conductive layer.

Abstract: A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).

Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.

Abstract: Embodiments of the present disclosure disclose a thin film transistor, a method for manufacturing a thin film transistor, an array substrate, and a display device. The thin film transistor includes a source electrode and a drain electrode, each of the source electrode and the drain electrode including a metal substrate and a conductive layer covering the metal substrate. An adhesion between the conductive layer and a photoresist material is larger than an adhesion between the metal substrate and the photoresist material. The metal substrate and the conductive layer are both formed on a base substrate, an orthographic projection of the conductive layer on the base substrate covers an orthographic projection of the metal substrate on the base substrate, and. an area of the orthographic projection of the conductive layer on the base substrate is larger than an area of the orthographic projection of the metal substrate on the base substrate.

Abstract: An alternating stack of insulating layers and spacer material layers is formed located over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack. A memory stack structure is formed within each memory opening. Each memory stack structure includes a memory film and a vertical semiconductor channel. A silicon nitride layer is formed over a sidewall of each memory opening as a component of the memory film. A silicon carbon nitride interfacial layer is formed on the silicon nitride layer, and a tunneling dielectric layer is formed on the silicon carbon nitride interfacial layer.

Abstract: To provide a semiconductor device including an electrode having a low contact resistance with the back surface of a GaN substrate and being suitably bonded with solder, and having a low electric resistance of the current flowing in a vertical direction. The semiconductor device has a GaN substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a body electrode, a drain electrode, a source electrode, and a gate electrode. The drain electrode has a Ti layer, an Al layer, a Ti layer, a TiN layer, a Ti layer, a Ni layer, and an Ag layer sequentially from the second surface of the GaN substrate.

Abstract: Provided is a redistribution layer (RDL) structure including a substrate, a pad, a dielectric layer, a self-aligned structure, a conductive layer, and a conductive connector. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The self-aligned structure is disposed on the dielectric layer. The conductive layer extends from the pad to conformally cover a surface of the self-aligned structure. The conductive connector is disposed on the self-aligned structure. A method of manufacturing the RDL structure is also provided.

Abstract: Provided are an electrolytic copper foil, an electrode, and a lithium-ion cell. The electrolytic copper foil comprising copper and chloride is analyzed by TOF-SIMS along its thickness direction to obtain a spectrum of a relative depth ratio as X-axis and a relative intensity of chloride versus copper as Y-axis. There is a chloride peak located between 20% and 80% of the relative depth ratio in the spectrum, and the chloride peak is characterized by a maximum relative intensity of chloride versus copper ranging from 0.77% to 5.13% and a full width at half maximum ranging from 2.31% to 5.78%. With above characteristics, the electrolytic copper foil has low density of copper particles, low degree of warpage, and good coating uniformity of the active material applied thereon, thereby optimizing the efficiency of a lithium-ion cell comprising the electrolytic copper foil.

Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

Abstract: A light-emitting element according to an embodiment comprises: a substrate; a light-emitting structure comprising a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, which are successively arranged on the substrate; and first and second electrodes, which are electrically connected to the first and second conductive semiconductor layers, respectively, wherein the first electrode comprises at least one first contact portion arranged on the first conductive semiconductor layer, which is exposed to at least a part of a first area of the light-emitting structure, and connected to the first conductive semiconductor layer, and a plurality of second contact portions connected to the first conductive semiconductor layer that is exposed in a second area, which is positioned, on a plane, closer to the inner side than the first area of the light-emitting structure, and the second electrode comprises a third contact part, which is arranged in the second area of the light-emitt

Abstract: A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure and an S/D contact structure formed over the fin structure. The FinFET device structure also includes an S/D conductive plug formed over the S/D contact structure, and the S/D conductive plug includes a first barrier layer and a first conductive layer. The FinFET device structure includes a gate contact structure formed over the gate structure, and the gate contact structure includes a second barrier layer and a second conductive layer. The FinFET device structure includes a first isolation layer surrounding the S/D conductive plug, and the first barrier layer is between the first isolation layer and the first conductive layer. A second isolation layer surrounding the gate contact structure, and the second barrier layer is between the second isolation layer and the second conductive layer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, drain electrodes, a drain interconnect portion, and a drain conductive portion. The semiconductor member includes first and second semiconductor regions. The drain electrodes extend along a first direction, are arranged in a second direction crossing the first direction, and are provided at the first semiconductor region. A direction from the first semiconductor region toward the second semiconductor region is aligned with the first direction. The drain interconnect portion extends along the second direction and is electrically connected to the drain electrodes. The drain conductive portion is electrically connected to the drain interconnect portion. The drain conductive portion includes first and second conductive regions. A portion of the drain interconnect portion is between the first conductive region and the first semiconductor region in a third direction.