Abstract: A process for forming a conducting structure layer that can reduce metal etching residues, in which a pre in-situ metal layer is added before a metal layer is deposited. The pre in-situ metal layer enables the crystalloid of the metal layer to grow more 5 evenly, and thus reduces the etching residues of the conducting structure layer. A structure of a conducting structure layer is also provided.

Abstract: A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

Abstract: The present invention provides a method in making a pillar-type structure (e.g. a storage node of stack capacitor) on a semiconductor substrate. By depositing a conductive polysilicon electrode layer, a nitride layer and a silicon layer on the substrate, and then required oxide pillars are formed in the silicon layer to act as a mask for etching the conductive polysilicon electrode layer.

Abstract: A method and system for providing a via structure for an integrated circuit is disclosed. The method and system includes providing a high conductivity metal that forms a metal structure consisting of the high conductivity metal. The method and system also includes a dielectric material surrounding the high conductivity metal. The dielectric material includes sidewalls to form a via hole. The method and system also include providing a via plug material other than the high conductivity metal. The via plug material covers the high conductivity metal and substantially fills the via hole. The via plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is for gettering the high conductivity metal sputtered on the sidewalls of the via hole.

Abstract: A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

Abstract: A method for selectively depositing a silicon oxide insulator spacer layer between multi-layer patterned metal stacks within an integrated circuit. Formed upon a semiconductor substrate is a silicon oxide insulator substrate layer which is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Upon the silicon oxide insulator substrate layer are formed multi-layer patterned metal stacks. The multi-layer patterned metal stacks have a top barrier metal layer formed from titanium nitride and a lower-lying conductor metal layer formed from an aluminum containing alloy. Formed selectively upon the portions of the silicon oxide insulator substrate layer exposed through the multi-layer patterned metal stacks and upon the edges of the aluminum containing alloy exposed through the multi-layer patterned metal stacks is a silicon oxide insulator spacer layer.

Abstract: A reduced CTE composite structure is made by providing a matrix material whose CTE is to be reduced, adding negative CTE bodies to the matrix material and mechanically coupling the matrix material to the negative CTE bodies as by deforming the composite structure. A preferred application is to make an improved composite material for use as a heat sink for semiconductor substrates with a minimum of thermal expansion mismatch.

Abstract: A method of forming a conductive line structure is provided. An adhesion layer is formed on a substrate surface. A seed layer is formed on the adhesion layer. A conductor is formed on the seed layer to form a partially complete structure. The partially complete structure is exposed to an electrolyte and undergoes an anodization process. At least a portion of the seed layer and a portion of the conductor are transformed to seed layer metal oxide and conductor metal oxide, respectively. At least a portion of the adhesion layer is transformed to an adhesion layer metal oxide and a further portion of the conductor is transformed to the conductor metal oxide.

Abstract: The integrated semiconductor memory configuration has a semiconductor body in which selection transistors and storage capacitors are integrated. The storage capacitors have a dielectric layer configured between two electrodes. At least the upper electrode is constructed in a layered manner with a platinum layer, that is seated on the dielectric layer, and a thicker, base metal layer lying above the platinum layer.

Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.

Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The interlayer dielectric layer 20 includes at least a first silicon oxide layer 20b that is formed by a polycondensation reaction of a silicon compound and hydrogen peroxide, and a second silicon oxide layer 20c formed over the first silicon oxide layer and containing an impurity. The pad section 30A includes a wetting layer 32, an alloy layer 34 and a metal wiring layer 37.

Abstract: A process for producing a semiconductor device comprises a step of polishing of a region of an electroconductive material serving as an electrode or a wiring line in an insulating layer formed on a semiconductor region, the region of the electroconductive material being electrically connected to the semiconductor region, wherein a region of another material is formed within the region of the electroconductive material to be polished. Also a semiconductor device having the region is provided. A process for producing an active matrix substrate comprises a step of polishing of picture element electrodes made of a metal provided on crossing portions of plural signal lines and plural scanning lines and a means for applying voltage to the picture elements, wherein a region of another material is formed within the region of the picture element electrode to be polished. An active matrix substrate has such picture element electrodes as mentioned above.

Abstract: An interconnect structure for use in semiconductor devices, comprising: (a) a thin and elongated aluminum wire connected to a first metal structure; and (b) a plurality of regularly spaced dummy tungsten plugs which are connected to the aluminum wire at one end and are buried in an underlying dielectric layer so that it is insulated at the other end. The dummy tungsten plugs absorb the mobile aluminum atoms generated through stress-induced migration when the interconnect structure is subject to a rapid temperature change, thus preventing the via bulging problem which could seriously damage the second metal structure above the first metal structure.

Abstract: A semiconductor device is constituted by embedding an Al wiring layer in a second object formed on an interlayer-insulating film on one principal plane of a semiconductor substrate and connecting with an Al wiring formed on the substrate and at least, an Nb liner film and NbAl alloy film are formed between the second object and the Al wiring layer.

Abstract: Disclosed is an integrated circuit structure having one or more metal lines thereon with metal line sidewall retention structures formed on the sides of the metal lines. The metal line sidewall retention structures comprise a material sufficiently hard to inhibit lateral distortion or expansion of portions of the metal line during subsequent processing or use of the metal line. The metal line sidewall retention structures are formed by anisotropically etching a layer of a material sufficiently hard to inhibit lateral distortion or expansion of portions of the metal line after formation of a layer of such a material over and around the sides of the metal lines.

Abstract: A method and apparatus is disclosed for sequential processing of integrated circuits, particularly for conductively passivating a contact pad with a material which resists formation of resistive oxides. In particular, a tank is divided into three compartments, each holding a different solution: a lower compartment and two upper compartments divided by a barrier, which extends across and partway down the tank. The solutions have different densities and therefore separate into different layers. In the illustrated embodiment, integrated circuits with patterned contact pads are passed through one of the upper compartments, in which oxide is removed from the contact pads. Continuing downward into the lower compartment and laterally beneath the barrier, a protective layer is selectively formed on the insulating layer surrounding the contact pads. As the integrated circuits are moved upwardly into the second upper compartment, a conducting monomer selectively forms on the contact pads prior to any exposure to air.

Abstract: A method and apparatus are provided for reducing and eliminating the First Wafer Effect. Specifically, in a method, or system that employs a separate hot chamber for hot deposition of material that may result in the First Wafer Effect (FWE material), a cold layer of the FWE material is deposited within the hot deposition chamber prior to deposition of the hot FWE material layer.

Abstract: A lower metal plate having a strip-like opening is used in a bond pad structure having metalplugs coupling the lower metal plate to an upper metal plate. A volume of relatively rigid material filling a volume above the strip-like opening transfers stress from the upper metal plate, through the strip-like opening, and to a foundation layer upon which the lower metal plate is disposed. The bond pad structure can be fabricated using the same semiconductor processing steps used to fabricate amorphous silicon antifuse structures having metal plugs.

Abstract: An interconnect structure of a semiconductor device includes: a bottom interconnect layer formed in a dielectric layer overlying a silicon substrate; a top interconnect layer having aluminum as a main component and connected with the bottom interconnect layer by way of a via plug formed in the dielectric layer; and a first barrier metal layer having higher <111> orientation. The higher <111> orientation degree of the first barrier metal layer aluminum suppresses occurrence and growth of electro-migration provide a reliable interconnect structure.

Abstract: There is disclosed a wiring structure for a semiconductor device being excellent in the resistance against electromigration and being able to lengthen a life of the wiring. The wiring structure is comprised of a refractory metal layer and an aluminum alloy layer being stacked on the refractory metal layer. The wiring structure contains a compound layer produced between the refractory metal layer and the aluminum alloy layer. The refractory metal layer is parted in the extended direction of the wiring to prevent the compound layer produced between the refractory metal layer and the aluminum alloy layer from being ranged in the extended direction of the wiring. A length of an interval between the parted refractory metal layer portions is set to exceed a value being twice as large as a thickness of the compound layer. This prevents the compound layer growing between faces of refractory metal layer portion being opposite to each other being ranged each other.

Abstract: First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and a thermal treatment process using annealing step is executed. At this time, all or part of aluminum oxide (AlOx) layer having a high resistivity, which is formed on the gate wire and/or the data wire during manufacturing process, may be removed. Then, the passivation layer is patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively.

Abstract: A semiconductor device having metal interconnects provides for a reduction of the recessing of metal in vias, particularly when the metal in the vias is aluminum or an aluminum alloy. The device includes a via in a device layer of the semiconductor device, a barrier layer formed over the device layer, and a metal layer formed over the barrier layer. The metal layer also fills the via to form a via structure. A portion of the metal layer is then removed and a remaining portion of the metal layer forms a conductive structure having a sidewall extending from a surface of the barrier layer. A spacer is formed along the sidewall of the conductive structure and a portion of the barrier layer is removed using the spacer to protect the via structure adjacent the surface of the device layer. In particular, the spacer protects a portion of the via structure that does not overlap with the conductive structure.

Abstract: A conductive layer connecting structure has a barrier layer preventing mutual diffusion between silicon and platinum group elements even when they are heated to a high temperature. The conductive layer connecting structure includes a plug containing doped polycrystalline silicon, a barrier layer formed on the plug and containing titanium, silicon and nitrogen, and a lower electrode layer formed on the barrier layer and containing platinum.

Abstract: In one aspect the invention includes a method of protecting aluminum within an aluminum-comprising layer from electrochemical degradation during semiconductor processing comprising, providing a material within the layer having a lower reduction potential than aluminum. In another aspect, the invention includes a semiconductor processing method of forming and processing an aluminum-comprising mass, comprising: a) forming the aluminum-comprising layer mass to comprise a material having a lower reduction potential than aluminum; and b) exposing the aluminum-comprising mass to an electrolytic substance, the material protecting aluminum within the aluminum-comprising layer from electrochemical degradation during the exposing. In yet another aspect, the invention includes an aluminum-comprising layer over or within a semiconductor wafer substrate and comprising a material having a lower reduction potential than aluminum.

Abstract: A connection between a contact plug and an interconnect in a semiconductor device is disclosed. A contact plug is formed in a hole within an insulating film with its upper and generally in flush with a surface of the interlayer insulating film. An Interconnect uses a laminated film structure that includes an aluminum film over the upper end of each of the contact plug.

Abstract: The present invention provides a bonding pad on a semiconductor chip such that peeling of bonding pads during interconnection in the packaging process is avoided. The bonding pad is used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The semiconductor chip comprises a first dielectric layer positioned in a predetermined area on the surface of the semiconductor chip, a second dielectric layer positioned on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer, and a bonding pad positioned on the first dielectric layer for electrically connecting anintegrated circuit (IC) in the semiconductor chip with an external circuit.

Abstract: Methods for making an aluminum-containing metallization structure, methods and solutions for cleaning a polished aluminum-containing layer, and the structures formed by these methods. The methods for making the aluminum-containing metallization structure are practiced by providing a substrate, forming a metal layer with an upper surface containing aluminum over the substrate, polishing the metal layer, and contacting the polished surface of the metal layer with a solution comprising water and at least one corrosion-inhibiting agent. The method for cleaning the polished aluminum-containing layer is practiced by contacting a polished aluminum-containing layer with a solution comprising water and a corrosion-inhibiting agent. In these methods and solutions, the water may be deionized water, the corrosion-inhibiting agent may be citric acid or one of its salts, and the solution may contain additional additives, such as chelating agents, buffers, oxidants, anti-oxidants, and surfactants.

Abstract: The present invention is directed toward the formation of implanted thermally and electrically conductive structures in a dielectric. An electrically conductive structure, such as an interconnect, is formed through ion implantation into several levels within a dielectric layer to penetrate into an electrically conductive region beneath the dielectric layer, such as a semiconductor substrate. Ion implantation continues in discreet, overlapping implantations of the ions from the electrical conductive region up to the top of the dielectric layer so as to form a continuous interconnect. Structural qualities achieved by the method of the present invention include a low interconnect-conductive region resistivity and a low thermal-cycle stress between the interconnect and the dielectric layer in which the interconnect has been implanted.

Abstract: Disclosed is a method for in situ formation of titanium aluminide. The disclosed method is directed to overcoming voiding problems which result in conventional titanium and aluminum metal interconnect stacks. The steps of the method comprise first providing a silicon substrate, which typically comprises an in-process integrated circuit wafer. Next, an insulating passivation layer is provided on the silicon substrate. The next step is the sputtering of a titanium layer of a given thickness over the passivation. Subsequently, an aluminum film of three times the thickness of the titanium layer is sputtered over the titanium layer. The next step comprises annealing the titanium layer and the aluminum film in situ in a metal anneal chamber to form titanium aluminide. Following the in situ anneal, the remainder of the needed aluminum is sputtered over the titanium aluminide and a further passivation layer of titanium nitride is then sputtered over the aluminum.

Abstract: Copper or copper alloy interconnection patterns are formed by a damascene technique. An aluminum or magnesium alloy is deposited in a damascene opening formed in a dielectric layer. Copper or a copper alloy is then electroplated or electroless plated on the aluminum or magnesium alloy, filling the opening. During low temperature annealing, aluminum or magnesium atoms diffuse through the copper or copper alloy layer and accumulate on its surface forming a self-encapsulated oxide to prevent corrosion and diffusion of copper atoms.

Abstract: The present invention provides a structure and a method for formation of interconnect having a barrier layer, aluminum layer on the barrier layer, a reaction prevention layer on the aluminum layer, an antireflective coating layer on the reaction prevention layer, a dielectric layer, a via, a conductive plug, and another aluminum layer on the via and the dielectric layer. This structure prevents interconnects from contact resistance failure caused by an aluminum nitride film AlF, a titanium fluorine film TixFF, aluminum overetching, and aluminum consumption. As a result of this invention, via electromigration and aluminum line electromigration characteristics are improved in semiconductor devices.

Abstract: A semiconductor configuration with an ohmic contact-connection includes a p-conducting semiconductor region made of silicon carbide. A p-type contact region serves for the contact-connection. The p-type contact region is composed of a material containing at least nickel and aluminum. A substantially uniform material composition is present in the entire p-type contact region. A method for contact-connecting p-conducting silicon carbide with a material containing at least nickel and aluminum is also provided. The two components nickel and aluminum are applied simultaneously on the p-conducting semiconductor region.

Abstract: An interconnection contact structure assembly including an electronic component having a surface and a conductive contact carried by the electronic component and accessible at the surface. The contact structure includes an internal flexible elongate member having first and second ends and with the first end forming a first intimate bond to the surface of said conductive contact terminal without the use of a separate bonding material. An electrically conductive shell is provided and is formed of at least one layer of a conductive material enveloping the elongate member and forming a second intimate bond with at least a portion of the conductive contact terminal immediately adjacent the first intimate bond.

Abstract: Interlevel contacts in semiconductor integrated circuits are fabricated by formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

Abstract: Wire bonding to a Cu interconnect via and Al pad with reduced Al and Cu inter-diffusion is achieved by interposing a barrier layer between the Cu interconnect and Al pad. Embodiments include forming a barrier layer of Ti, Ta, W, alloy thereof or nitride thereof, between the Cu interconnect and the Al pad.

Abstract: A semiconductor device having a contact layer and a diffusion barrier layer is fabricated by preparing a semiconductor substrate forming a layer of titanium/aluminum alloy on the surface of the substrate and then heating the resultant structure in a nitrogen ambient to form a contact layer of titanium silicide interposed between the substrate and a diffusion barrier layer consisting of titanium/aluminum/nitride.

Abstract: A plurality of metal wires are formed on an underlying interlayer insulating film. Areas among the metal wires are filled with a buried insulating film of a silicon oxide film with a small dielectric constant (i.e., a first dielectric film), and thus, a parasitic capacitance of the metal wires can be decreased. On the buried insulating film, a passivation film of a silicon nitride film with high moisture absorption resistance (i.e., a second dielectric film) is formed, and thus, a coverage defect can be avoided. A bonding pad is buried in an opening formed in a part of a surface protecting film including the buried insulating film and the passivation film, so as not to expose the buried insulating film within the opening. Thus, moisture absorption through the opening can be prevented.

Abstract: A method is disclosed for forming a high aspect ratio submicron VLSI interconnect structure. The method makes use of the high diffusivity of aluminum alloyed with germanium and the low eutectic temperature of the alloy for more uniform filling of interconnect structure openings having high aspect ratios. The method comprises preparing a semiconductor device or portion of a semiconductor device that is to receive electrical contact, covering the semiconductor device with an insulating layer, forming an interconnect structure opening through the insulating layer, depositing a layer of germanium in the interconnect structure opening, and reflow sputtering aluminum or aluminum alloy into the interconnect structure opening. Alternatively, the aluminum or aluminum alloy can be cold sputtered into the interconnect structure opening, followed by a low temperature reflow. The aluminum will readily diffuse to the bottom of the interconnect structure opening, assisted by its high diffusivity with the germanium.

Abstract: Aluminum containing films having an oxygen content within the films. The aluminum-containing film is formed by introducing hydrogen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.

Abstract: In producing a metal-gate non-volatile memory cell, a layer of oxide is formed over a silicon substrate. A floating gate is then formed over the oxide. Source and drain regions are then formed in the silicon substrate such that at least one of the edges of the floating gate is aligned with its corresponding edge of one of the source and drain regions. A high temperature anneal cycle is then carried out to remove the defects in the source and drain regions. A composite layer of either Oxide-Nitride-Oxide-Polysilicon (ONOP) coupling dielectric or Oxide-Polysilicon (OP) coupling dielectric is then formed over the floating gate. Finally, a control gate made from metal is formed over the composite layer of ONOP or OP coupling dielectric.

Abstract: Semiconductor device and method for manufacturing the same prevent the spread of a tungsten film out of an opening portion of a contact hole when the tungsten is grown in the contact hole and avoid inferior wiring shape and inter-wiring shirt-circuit. After a titanium/titanium nitride film is formed along an inner surface of the contact hole, a photo-resist film is applied. Then, the photo-resist film is etched away until a distance from an upper end of the contact hole to the surface of photo-resist film is not smaller than one-half of a width of the contact hole when the titanium/titanium nitride film is formed. After the titanium/titanium nitride film is etched by using the photo-resist as a mask, the photo-resist film is removed and a tungsten layer is selectively grown by using the titanium/titanium nitride film as a seed.

Abstract: A ferroelectric thin film device comprises an Si substrate; a TiN thin film whose Ti component is partially replaced with Al, the TiN thin film being formed on the Si substrate; and a ferroelectric thin film of an oxide with a perovskite structure formed on the TiN thin film, wherein the amount of Al atoms present at Ti sites of the TiN thin film after partially replacing Ti with Al is within the range from about 1% to 30% and the oxygen atomic content of the TiN thin film is equal to or less than about 5%.

Abstract: An article comprising a metal circuit and/or a heat-radiating metal plate formed on a ceramic substrate, wherein the metal circuit and/or the heat-radiating metal plate comprise either (1) the following first metal-second metal bonded product, wherein the first metal and the second metal are different, or (2) the following first metal-third metal-second metal bonded product, and wherein in (1) and (2), the first metal is bonded to the ceramic substrate; first metal: a metal selected from the group consisting of aluminum (Al), lead (Pb), platinum (Pt) and an alloy containing at least one of these metal components; second metal: a metal selected from the group consisting of copper (Cu), silver (Ag), gold (Au), aluminum (Al) and an alloy containing at least one of these metal components; and third metal: a metal selected from the group consisting of titanium (Ti), nickel (Ni), zirconium (Zr), molybdenum (Mo), tungsten (W) and an alloy containing at least one of these metal components.

Abstract: Aluminum-containing films having an oxygen content within the films. The aluminum-containing film is formed by introducing hydrogen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.

Abstract: Titanium aluminum nitrogen (“Ti—Al—N”) is deposited onto a semiconductor substrate area to serve as an antireflective coating. For wiring line fabrication processes, the Ti—Al—N layer serves as a cap layer which prevents unwanted reflection of photolithography light (i.e., photons) during fabrication. For field emission display devices (FEDs), the Ti—Al—N layer prevents light originating at the display screen anode from penetrating transistor junctions that would hinder device operation. For the wiring line embodiment, an aluminum conductive layer and a titanium-aluminum underlayer are formed beneath the antireflective cap layer. The Ti—Al underlayer reduces the shrinkage which occurs in the aluminum conductive layer during heat treatment.

Abstract: In a semiconductor device having a laminated metal layer in which a metal layer whose main component is aluminum and a metal layer whose main component is nickel are laminated on each other, the ratio (tAl/tNi) of the thickness (tAl) of the metal layer whose main component is aluminum to that (tNi) of the metal layer whose main component is nickel is controlled to 5 or larger, so that part of the metal layer whose main component is aluminum remains even if an Al—Ni intermetallic compound is formed.

Abstract: A microelectronic structure including adjacent material layers susceptible of adverse interaction in contact with one another, and a barrier layer interposed between said adjacent material layers, wherein said barrier layer comprises a binary, ternary or higher order metal nitride-carbide material, whose metal constituents are different from one another and include at least one metal selected from the group consisting of transition metals Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W, Sc and Y, and optionally further including Al and/or Si. The barrier layer is stoichiometrically constituted to be amorphous or nanocrystalline in character, and may be readily formed by techniques such as chemical vapor deposition, sputtering, and plasma-assisted deposition, to provide a diffusional barrier of appropriate resistivity character for structures such as DRAMs or non-volatile ferroelectric memory cells.

Abstract: A thin film semiconductor device includes a glass supporting body having thereon an insulating substrate which is attached thereto by a layer of adhesive material. On the surface of the substrate facing the supporting body is a layer of semiconductor material which includes therein a semiconductor element, such surface further having thereon a metalization pattern of conductor tracks. An insulating layer is additionally provided between the metalization pattern and the adhesive layer, and has a dielectric constant &egr;r below 3 and a thickness in the range of approximately 20 &mgr;m to 60 &mgr;m. By virtue of such additional layer, parasitic capacitanees between the metalization pattern and an envelope in which the device is included or a printed circuit board on which the device is mounted are reduced substantially, thereby reducing the power consumption of the device.

Abstract: An electrode substrate comprises a backing substrate carrying thereon a metal electrode layer and/or a recording layer, the layer or layers having a smooth surface area with a surface roughness of less than 1 nm by more than 1 &mgr;m2. The smooth surface of the metal electrode layer and/or the recording layer is formed by firstly forming the layer on another substrate having a corresponding smooth surface and then peeling another substrate off the layer after the layer is bonded to the surface of the backing substrate, whereby the smooth surface profile of another substrate is transferred to the surface of the layer formed on the backing substrate.

Abstract: In an active matrix liquid crystal display (LCD) device, a conductor line interconnecting a drain of each thin-film transistor and a corresponding pixel electrode constructed with indium tin oxide (ITO) is formed in a three-layer structure in which an aluminum film is sandwiched between a pair of titanium films. This construction prevents poor contact and deterioration of reliability because electrical contact is established between one titanium film and semiconductor and between the other titanium film and ITO. The aluminum film has low resistance which is essential for ensuring high performance especially in large-screen LCDs.