Abstract: A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.

Abstract: A method for forming a line of an LCD device includes sequentially depositing first and second metal layers on a glass substrate, forming a mask pattern on the second metal layer, performing a first wet-etch process using a mixed acid solution as an etchant on the first and second metal layers with the mask pattern, and performing a second wet-etch process using the mask pattern.

Abstract: A lid material (1) according to the present invention comprises: a base layer (2) composed of a low thermal expansion metal; an intermediate metal layer (3) provided on one surface of the base layer (2) and composed of a low proof stress metal having a proof stress of not greater than 110 N/mm2; and a brazing material layer (4) provided on the intermediate metal layer (3) and composed of a silver brazing alloy mainly comprising silver. The intermediate metal layer (3) and the brazing material layer (4) are press- and diffusion-bonded to each other, and the brazing material layer (4) has a blistered area ratio of not greater than 0.5% as observed on an outer surface of the brazing material layer. The low proof stress metal is preferably oxygen-free copper. A lid produced from the lid material (1) exhibits an excellent bonding property when the lid is brazed to a case mainly composed of a ceramic material for an electronic component package.

Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.

Abstract: There is disclosed a semiconductor device comprising a first wire and a pad portion thereof provided in a portion from an upper surface to an inner portion of a first insulation film provided above a substrate, a second insulation film provided on the first insulation film and the first wire, a second wire provided to be exposed from an upper surface of the second insulation film in an upper portion of the pad portion of the first wire, and a contact plug provided to reach an inner portion of the pad portion of the first wire from an undersurface of the second wire.

Abstract: There is provided a semiconductor device comprising a Cu film provided above a main surface of a semiconductor substrate and used as a wiring, an intermediate layer formed at least on the Cu film, and an Al film formed on the intermediate layer and used as a pad, wherein the intermediate layer comprises a refractory metal nitride film and a refractory metal film formed on the refractory metal nitride film.

Abstract: The semiconductor device of the present invention includes: a substrate; a first conductor film supported by the substrate; an insulating film formed on the substrate to cover the first conductor film, an opening being formed in the insulating film; and a second conductor film, which is formed within the opening of the insulating film and is in electrical contact with the first conductor film. The second conductor film includes: a silicon-containing titanium nitride layer formed within the opening of the insulating film; and a metal layer formed over the silicon-containing titanium nitride layer. The metal layer is mainly composed of copper.

Abstract: This invention relates to a method of forming a local interconnect and a semiconductor device comprising a local interconnect. The semiconductor device comprises: a) a dielectric outside layer; and b) a conductivity structure comprising: i) at least one barrier layer having a thickness of 10-200 ? on a surface of said oxide layer; and ii) a conductive layer comprising titanium, on said at least one barrier layer, said at least one barrier layer preventing diffusion of oxygen from said dielectric oxide layer into said conductive layer and having a corresponding oxide that is not soluble in said conductive layer.

Abstract: An aluminum-containing film having an oxygen content within the film. The aluminum-containing film is formed by introducing hydrogen gas and oxygen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.

Abstract: An active matrix substrate comprises a matrix array of TFTs. A double-layered film includes an under-layer of aluminum-neodymium (Al—Nd) alloy and an over-layer of high melting point metal. The double-layered film forms first interconnection lines for connection to the TFTs. A triple-layered film includes an under-layer of said high melting point metal, a middle-layer of said Al—Nd alloy and an over-layer of the high melting point metal. The triple-layered film forms second interconnection lines for connection to the TFTs.

Abstract: An under-bump-metallurgy layer is provided. The under-bump-metallurgy layer is formed over the contact pad of a chip and a welding lump is formed over the under-ball-metallurgy layer. The under-bump-metallurgy layer comprises an adhesion layer, a barrier layer and a wettable layer. The adhesion layer is directly formed over the contact pad. The barrier layer made from a material such as nickel-vanadium alloy is formed over the adhesion layer. The wettable layer made from a material such as copper is formed over the barrier layer. The wettable layer has an overall thickness that ranges from about 3 ?m to about 8 ?m.

Abstract: A contact and a copper interconnect line as an uppermost interconnect layer are buried in an interlayer insulating film. A pad area including aluminum alloy (such as AlCu or AlSiCu) is buried in a predetermined area of the copper interconnect line. A gold wire is bonded to the pad area.

Abstract: The present invention is to improve yield and reliability in a wiring step of a semiconductor device. When an Al wiring on an upper layer is connected through an connection pillar onto an Al wiring on a lower layer embedded in a groove formed on an interlayer insulation film, a growth suppression film having an opening whose width is wider than that of the Al wiring is formed on the interlayer insulation film and the Al wiring. In this condition, Al and the like are grown by a selective CVD method and the like. Accordingly, the connection pillar is formed on the Al wiring within the opening, in a self-matching manner with respect to the Al wiring.

Abstract: A structure includes a diffusion barrier layer pattern, a conductive layer pattern, an adhesion layer pattern, and a tantalum nitride layer pattern that are sequentially stacked over a semiconductor substrate. According to the method of forming the structure, a tantalum nitride layer is formed by using a PVD, CVD, or ALD process and patterned to form a tantalum nitride layer pattern. The structure and the method prevents process failures such as ring defects, simplifies associated processes, and allows relatively easy exposure of only an anti-refractive layer when forming a via hole in the structure.

Abstract: An organic-inorganic hybrid film is deposited on a substrate by introducing, into a vacuum chamber, a gas mixture of a silicon alkoxide and an organic compound and generating a plasma derived from the gas mixture. Then, a hydrogen plasma process is performed with respect to the organic-inorganic hybrid film by introducing, into the vacuum chamber, a gas containing a reducing gas and generating a plasma derived from the gas. As a result, an organic component in the organic-inorganic hybrid film eliminates therefrom and numerous fine holes are formed in hollow portions from which the organic component has eliminated, whereby a porous film composed of the organic-inorganic hybrid film is obtained.

Abstract: A wiring layer is covered with a first organic SOG layer, a reinforcement insulating layer consisting of a silicon oxide film or a silicon nitride film formed by means of a plasma CVD method, and a second organic SOG layer, in this order. A via hole is formed in the first organic SOG layer and the reinforcement insulating layer, and a trench is formed in the second organic SOG layer to correspond to the via hole. A conductive via plug and an electrode pad are embedded in the via hole and the trench, respectively. The second SOG layer is covered with a passivation layer in which a through hole is formed to expose the electrode pad. A wire is connected to the exposed electrode pad in the through hole.

Abstract: In extremely minute copper wiring the width or the thickness of which is equal to or shorter than approximately the double length of the mean free path of a copper atom, a value of the resistance may be larger, compared with aluminum wiring of the same extent and it is difficult to realize wiring having small resistance. To solve such a problem, aluminum wiring is used for wiring having form in which the respective resistivities ? of both wirings have the relation of ?Al<?Cu and copper wiring is used for wiring having form in which the respective resistivities ? of both wirings have the relation of ?Al??Cu. As a result, a semiconductor device which has small resistance, transmits a signal at high speed and is provided with a multilayer wiring layer can be realized.

Abstract: A carrier has a metal area that is essentially composed of copper. A chip has a rear side metallization layer. A buffer layer, essentially composed of nickel and having a thickness of between 5 ?m and 10 ?m, is arranged on the metal area. The chip does not have a chip housing and is arranged on the metal area, which has been provided with the buffer layer, such that only one connecting medium is arranged between the rear side metallization layer of the chip and the buffer layer.

Abstract: In order to form an aluminum system wiring that does not peel off on an insulating film containing fluorine and to improve the reliability thereof, a semiconductor device according to the present invention includes an insulating film (14) containing fluorine formed on a substrate (11), a titanium aluminum alloy film (17a) formed on the insulating film (14) containing fluorine, and a metallic film (17b) comprising aluminum or an aluminum alloy formed on the titanium aluminum alloy film (17a).

Abstract: A contact structure and manufacturing method thereof is provided. A substrate having a first conductive layer and a dielectric layer thereon is provided. The dielectric layer has a contact opening that exposes a portion of the first conductive layer. A conductive nano-particle layer is formed on the exposed surface of the first conductive layer. Thereafter, a second conductive layer is formed inside the contact opening to cover the conductive nano-particle layer and form a contact structure. The conductive nano-particle layer at the bottom of the contact prevents the second conductive layer from peeling off and costs much less to produce.

Abstract: An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×1018 atoms·cm?3 or less, carbon atoms at a concentration of 5×1018 atoms·cm?3 or less, and nitrogen atoms at a concentration of 7×1017 atoms·cm?3 or less; furthermore, a silicon nitride film is formed on the aluminum gate, and an anodic oxide film is formed on the side planes thereof.

Abstract: A mold type semiconductor device includes a semiconductor chip including a semiconductor part; a metallic layer; a solder layer; and a metallic member connecting to the semiconductor chip through the metallic layer and the solder layer. The solder layer is made of solder having yield stress smaller than that of the metallic layer. Even when the semiconductor chip is sealed with a resin mold, the metallic layer is prevented from cracking.

Abstract: A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation. The enhanced vias are useful in a wide variety of semiconductor devices, including SRAMS and DRAMs.

Abstract: A liquid application material that is capable of forming an oxidized insulator as a result of baking is applied onto a support substrate to produce an object of processing. Then, a mold having projection structures with intervals of nanometers is pressed against the applied liquid material to produce corresponding recess structures. Thereafter, the applied liquid material is baked in oxygen-containing gas or oxidized in ozone or oxygen plasma to make it electrically highly resistive. Subsequently, a layer to be anodized is formed on said oxidized insulator. Then, the layer to be anodized is actually anodized in an acidic solution to form fine holes that are aligned with the respective recess structures in the anodized layer. Accordingly, fine recess structures can be manufactured with ease.

Abstract: In an integrated circuit configuration, above a first conductive structure which is embedded in a first insulating layer there are arranged a first barrier layer and a second insulating layer, in which a contact hole is provided which reaches down to the first conductive structure. Above the first barrier layer, the side walls of the contact hole are provided with spacers which act as a diffusion barrier and which reach down to the surface of the first barrier layer. A second conductive structure is arranged in the contact hole. The second conductive structure is conductively connected to the first conductive structure. During the production of the contact hole, the spacers prevent deposition of material from the first conductive structure on the surface of the second insulating layer.

Abstract: The invention includes integrated circuitry having an electrically insulative layer over a substrate and an opening within the electrically insulative layer. The opening has a periphery defined at least in part by a bottom surface and a sidewall surface. A first titanium layer is disposed within the opening in contact with the bottom surface and is thicker along the bottom surface than along the sidewall. A layer of TiN is provided over the first titanium layer along the bottom surface and along the sidewall surface of the opening, and a second layer of titanium is disposed over the electrically insulative layer but substantially not within the opening. The second titanium layer has a thickness of less then 50 Å along the sidewall surface and over the bottom surface. An aluminum-comprising layer is within the opening and over the second layer.

Abstract: An integrated circuit device which includes a surface alloy layer, where the alloy layer forms a protective and adherent thin layer which improves electromigration performance. A method includes steps of forming one or more trench and/or via structures, depositing a thin TaN/Ta barrier layer stack and then a Copper seed layer, depositing and filling the via/trench with a thick Copper layer, removing the metal layers over in the field area, depositing, for example, a layer of Aluminum over the structure, annealing the devices in a protective atmosphere to allow Aluminum to react with Copper to form a thin Copper-Aluminum alloy, and removing the Aluminum metal layers over the field area, forming a thin layer of Al2O3, AlN or Al3C4 over the Copper-Aluminum for protection. During subsequent deposition of barrier and seed, the top surface layer of the Al2O3, AlN or Al3C4 is preferably removed to ensure the integrity of metal contact.

Abstract: A semiconductor device which includes, between a copper conductive layer and a low-k organic insulator, a barrier layer comprising an amorphous metallic glass, preferably amorphous tantalum-aluminum. A method of making the semiconductor device is also disclosed.

Abstract: An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.

Abstract: A terminal interconnection 45a including an aluminum alloy film 4a and a nitrogen-containing aluminum film 5a layered together is formed on a glass substrate 2. Nitrogen-containing aluminum film 5a in a contact portion 12a within a contact hole 11a exposing the surface of terminal interconnection 45a has a predetermined thickness d1 determined based on a specific resistance of the nitrogen-containing aluminum film. The thickness of the nitrogen-containing aluminum film outside the contact portion is larger than that of the nitrogen-containing aluminum film within the contact portion. Thereby, a semiconductor device or a liquid crystal display device having a reduced contact resistance and an appropriate resistance against chemical liquid is achieved.

Abstract: A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug.

Abstract: A method of fabricating a nitride-based semiconductor device capable of reducing contact resistance between a nitrogen face of a nitride-based semiconductor substrate or the like and an electrode is provided. This method of fabricating a nitride-based semiconductor device comprises steps of etching the back surface of a first semiconductor layer consisting of either an n-type nitride-based semiconductor layer or a nitride-based semiconductor substrate having a wurtzite structure and thereafter forming an n-side electrode on the etched back surface of the first semiconductor layer.

Abstract: A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of metal alloy which contains alloy dopant precipitates, and performing a first anneal of the integrated circuit to drive the alloy dopants into solid solution. The metal is quenched to prevent the alloy dopants from coming out of solution prior to removing excess metal alloy with a polish process. To improve conductivity after polishing, the dopants are allowed to come out of solution. The metal alloy is described as aluminum with alloy dopants of silicon and copper where the first anneal is performed at 400 to 500° C. This process is particularly applicable to fabrication of interconnects formed using a dual damascene process. The integrated circuit is described as any circuit, but can be a memory device such as a DRAM.

Abstract: A passive component is realized on-die by fabricating a first conductor from either a layer of interconnect metal comprising copper or aluminum and being between approximately 1.0 micron and approximately 2.0 microns thick, or from a layer of under bump metal comprising either copper or aluminum and being between approximately 2.0 microns to approximately 5.0 microns thick. Following, a first isolation layer is formed over the first conductor. A second conductor having at least one external pad and comprising under bump metal is next fabricated over the first isolation layer. The second conductor can be fabricated substantially directly above the first conductor, for example. Thereafter, a second isolation layer having a hole over the external pad of the second conductor is formed over the second conductor. Subsequently, a bump attach site is fabricated at the hole in the second isolation layer over the external pad of the second conductor.

Abstract: An interconnect structure, which can have three-levels, is formed by a metallization method in an electrical circuit. The method comprises providing a substrate assembly and depositing thereon a first dielectric layer thereover. A second dielectric layer is then deposited over the first dielectric layer. The second dielectric layer is patterned and anisotropically etched to form contact corridors. The second dielectric layer is again patterned and etched to form trenches, some of which are immediately above the contact corridors. An electrically conductive material is deposited to fill the contact corridors and trenches, and to leave a portion of the electrically conductive material above the second dielectric layer and directly above both the contact corridors and the trenches. The deposition forms a unitary three-level interconnect having a contiguous trench below a contact corridor below a metal line, where the metal line is above the second dielectric layer.

Abstract: An interconnection of an aluminum-copper-titanium alloy containing about 0.1 atomic percent titanium.

Abstract: A solder terminal and a fabrication method thereof are provided. According to one embodiment of the present invention, a solder terminal structure includes an adhesion metal layer formed on an electrode pad of a semiconductor device, a thermal diffusion barrier, a solder bonding layer, and a solder bump formed on upper portion of the solder bonding layer. With the thermal diffusion layer, the characteristic deterioration caused by the probe mark generated on the electrode pad can be prevented during a semiconductor reliability test, and at the same time, material movement between the layers of the electrode pad, the solder bonding layer and the adhesion metal layer can be reduced. Also, by having the thermal diffusion barrier act as a solder dam (a layer to confine the melted solder area to prevent the solder from being wetted), an additional deposition or etching process can be omitted.

Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.

Abstract: A semiconductor device includes a semiconductor structure including a semiconductor substrate having an integrated circuit portion, and a plurality of connecting pads connected to the integrated circuit portion. A plurality of distributing lines are formed on the semiconductor structure, connected to the connecting pads, and have connecting pad portions. An encapsulating layer made of a resin is formed on the semiconductor structure and upper surface of the distributing lines. A copper oxide layer is formed on at least a surface of each of the distributing lines except for the connecting pad portion.

Abstract: The present invention relates to a semiconductor device in which a capacitance element is mounted on a semiconductor substrate as well as a method of fabricating the device. According to the present invention, a substantial lower electrode is formed on a semiconductor substrate through a first insulation film; a peripheral electrode, i.e. the periphery of the lower electrode or a dummy electrode, which has the surface higher than the surface of the lower electrode being formed integrally with or separately from the lower electrode; an upper electrode being formed on the lower electrode through a dielectric film; a capacitance element being formed so that at least the surface of the dielectric film may lie on a level lower than the surface of the peripheral electrode; and a recess surrounded by the peripheral electrode being filled with a smoothing film.

Abstract: A hillock-free gate layer and method of manufacturing the same is disclosed. One or more pure aluminum layers are formed under high pressure and low sputtering power. An aluminum layer containing nitrogen is then formed on the pure aluminum layers to prevent the formation of hillocks and to reduce manufacturing costs.

Abstract: Isolated metal structures (110), (140) are formed adjacent to terminated metal lines (100), (130) that are connect by a via (120). The isolated structures (110), (140) act to suppress the stress created in the terminated metal lines (100), (130) during thermal cycling.

Abstract: A device having electrical and mechanical components. The device comprises multiple layers in which: a first layer or set of layers arranged is to function as one or more electrodes or conductors; and a second layer is arranged to function as one or more press contracts or wire contacts or wire bond pads. The second layer has different physical properties than the first layer, wherein the first layer or set of layers is relatively hard or tough and the second layer is relatively soft or malleable. A corresponding method is provided.

Abstract: A method of making a microelectronic device providing a base substrate having a bond pad, a first passivation layer overlying the base substrate and a portion of the bond pad, and a second passivation layer overlying the first passivation layer; forming a first sacrificial layer over the second passivation layer, wherein the first sacrificial layer includes an opening therethrough; etching the exposed portion of the second passivation layer to provide a recess therein; trimming a portion of the first sacrificial layer to enlarge the opening; etching the exposed portion of the second passivation layer to provide an enlarged recess and a first riser, a second tread, a second riser and a second tread; removing the first sacrificial layer; depositing a redistribution layer into the enlarged recess in the second passivation layer and over the first riser, first tread, second riser, and second tread.

Abstract: In a method of cutting a semiconductor wafer in which the semiconductor wafer 6 is cut by plasma etching, a protective sheet 30 on which a metallic layer 30b, a plasma etching rate of which is low, is formed on one face of an insulating sheet 30a is stuck on to a circuit forming face 6a by an adhesive layer 30c, and plasma is exposed onto an opposite side to the circuit forming face 6a from a mask side which is formed by covering regions except for cutting lines 31b with a resist film 31a so as to conduct plasma etching on portions of the cutting lines. Due to the above structure, it is possible to use the metallic layer as an etching stop layer for suppressing the progress of etching. Therefore, fluctuation of the progress of etching can be avoided and heat damage caused on the protective sheet can be prevented.

Abstract: There is provided a electronic parts packaging structure that includes a mounted body on which an electronic parts is mounted, the electronic parts having a connection pad, which has an etching stopper film (a copper film, a gold film, a silver film, or a conductive past film) as an uppermost film, and mounted on the mounted body to direct the connection pad upward, an interlayer insulating film for covering the electronic parts, a via hole formed in the insulating film on the connection pad of the electronic parts, and a wiring pattern connected to the connection pad via the via hole.

Abstract: A sputter target is made of a Ti—Al alloy containing Al in the range of 1 to 30 atm %. In the Ti—Al alloy constituting the sputter target, Al exists in at least one of a solid solution state in Ti and a state in which Al forms an intermetallic compound with Ti, and variation in Al content in the entire target is limited within 10%. Furthermore, an average crystal grain diameter of the Ti—Al alloy is 500 &mgr;m or less, and variation in crystal grain diameter in the entire target is limited within 30%. A Ti—Al—N film as a barrier film is formed by using the sputter target made of the Ti—Al alloy as described above. An electronic component includes a barrier film formed on a semiconductor substrate.

Abstract: A connection via hole is formed in an inter layer insulation film that covers a copper pad. Copper is formed within the connection via hole to form a connection copper via metal. An aluminum pad having a barrier metal thereunder for preventing reaction between copper and aluminum is formed on the connection copper via metal, thereby electrically connecting the copper pad and the aluminum pad to each other through the connection copper via metal. A step formed by the connection via hole that is formed in the inter layer insulation film is made substantially equal to zero with the aid of the connection copper via metal and at the same time, a film thickness of aluminum constituting the aluminum pad is reduced, thereby reducing manufacturing cost of the semiconductor device.

Abstract: A semiconductor device includes a first metal interconnection layer on a semiconductor substrate, an intermetal dielectric layer on the first metal interconnection layer and a second metal interconnection layer formed on the intermetal dielectric layer. A contact stud electrically connects the first and second metal interconnection layers through the intermetal dielectric layer, and includes a titanium/aluminum (TiAlx) core extending from the first metal interconnection layer toward the second metal interconnection layer. In method embodiments, a portion of an insulating layer of a semiconductor substrate is removed to form a hole that exposes an underlying conductive layer. A glue layer, e.g., a titanium (Ti) layer, is formed on bottom and sidewalls of the hole. A Ti seed layer is formed on the glue layer in the hole. An aluminum-containing layer is formed on the Ti seed layer. The substrate is thermally treated to form a contact stud including a TiAlx core.

Abstract: Embodiments of the invention include a capping layer of alloy material formed over a copper-containing layer, the alloy configured to prevent diffusion of copper through the capping layer. In another embodiment the alloy capping layer is self-aligned to the underlying conducting layer. Specific embodiments include capping layers formed of alloys of copper with materials including but not limited to calcium, strontium, barium, and other alkaline earth metals, as well as materials from other groups, for example, cadmium or selenium. The invention also includes methods for forming an alloy capping layer on a copper-containing conducting structure. One such method includes providing a substrate having formed thereon electrically conducting layer comprised of a copper-containing material and forming an alloy capping layer on the electrically conducting layer. In another method embodiment, forming the alloy capping layer includes forming a self-aligned capping layer over the conducting layer.