Resistive To Electromigration Or Diffusion Of The Contact Or Lead Material Patents (Class 257/767)
  • Patent number: 10128261
    Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: November 13, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Rahul Sharangpani, Sateesh Koka, Genta Mizuno, Naoki Takeguchi, Senaka Krishna Kanakamedala, George Matamis, Yao-Sheng Lee, Johann Alsmeier
  • Patent number: 10056342
    Abstract: A surface of at least one of a connection terminal of an electronic component and a connection terminal of a circuit board is covered with a protection layer made of a AgSn alloy. The connection terminal of the electronic component is soldered to the connection terminal of the circuit board.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: August 21, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Seiki Sakuyama, Toshiya Akamatsu, Nobuhiro Imaizumi, Keisuke Uenishi, Kenichi Yasaka, Toru Sakai
  • Patent number: 9876075
    Abstract: Aspects of the invention are directed to a method for forming a semiconductor device. A dielectric layer is formed on a semiconductor substrate. Subsequently, a metallic contact is formed in the dielectric layer such that it lands on the semiconductor substrate. A masking layer comprising a block copolymer is then formed on the dielectric layer. This block copolymer is caused to separate into two phases. One of the two phases is selectively removed to leave a patterned masking layer. The patterned masking layer is used to etch the dielectric layer. The patterned air gaps reduce the interconnect capacitance of the semiconductor device while leaving the dielectric layer with enough mechanical strength to serve as a middle-of-line dielectric.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: January 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar Van der Straten, Chih-Chao Yang
  • Patent number: 9793158
    Abstract: A method of fabricating a semiconductor device, the method including forming at least one interconnection structure that includes a metal interconnection and a first insulating pattern sequentially stacked on a substrate; forming barrier patterns covering sidewalls of the interconnection structure; forming second insulating patterns at sides of the interconnection structure, the second insulating patterns being spaced apart from the interconnection structure with the barrier patterns interposed therebetween; forming a via hole in the first insulating pattern by etching a portion of the first insulating pattern, the via hole exposing a top surface of the metal interconnection and sidewalls of the barrier patterns; and forming a via in the via hole.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: October 17, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Kong Siew, Hyunsu Kim
  • Patent number: 9633954
    Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Clinton Chao, Szu Wei Lu
  • Patent number: 9570398
    Abstract: An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed thereon, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: February 14, 2017
    Assignee: XINTEC INC.
    Inventors: Shu-Ming Chang, Yu-Ting Huang, Tsang-Yu Liu, Yen-Shih Ho
  • Patent number: 9524937
    Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: December 20, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongmin Baek, Sangho Rha, Sanghoon Ahn, Wookyung You, Naein Lee
  • Patent number: 9385038
    Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: July 5, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp, Thomas W. Dyer, Ronald G. Filippi, Stephen E. Greco, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 9334158
    Abstract: An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: May 10, 2016
    Assignee: XINTEC INC.
    Inventors: Yu-Ting Huang, Shu-Ming Chang, Yen-Shih Ho, Tsang-Yu Liu
  • Patent number: 9275948
    Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Clinton Chao, Szu Wei Lu
  • Patent number: 9087876
    Abstract: A vertical stack including a dielectric hard mask layer and a titanium nitride layer is formed over an interconnect-level dielectric material layer such as an organosilicate glass layer. The titanium nitride layer may be partially or fully converted into a titanium oxynitride layer, which is subsequently patterned with a first pattern. Alternately, the titanium nitride layer, with or without a titanium oxynitride layer thereupon, may be patterned with a line pattern, and physically exposed surface portions of the titanium nitride layer may be converted into titanium oxynitride. Titanium oxynitride provides etch resistance during transfer of a combined first and second pattern, but can be readily removed by a wet etch without causing surface damages to copper surfaces. A chamfer may be formed in the interconnect-level dielectric material layer by an anisotropic etch that employs any remnant portion of titanium nitride as an etch mask.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: July 21, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Son V. Nguyen, Tuan A. Vo, Christopher J. Waskiewicz
  • Patent number: 9041181
    Abstract: A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-chul Lee, Myung-kee Chung, Kun-dae Yeom
  • Patent number: 9030013
    Abstract: A structure includes a substrate, a low-k dielectric layer over the substrate, and a conductive barrier layer extending into the low-k dielectric layer. The conductive barrier layer includes a sidewall portion. A metal line in the low-k dielectric layer adjoins the conductive barrier layer. An organic buffer layer is between the sidewall portion of the conductive barrier layer and the low-k dielectric layer.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsien Peng, Hsin-Yen Huang, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 8975749
    Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8956918
    Abstract: A method for manufacturing a chip arrangement in accordance with various embodiments may include: placing a chip on a carrier within an opening of a metal structure disposed over the carrier; fixing the chip to the metal structure; removing the carrier to thereby expose at least one contact of the chip; and forming an electrically conductive connection between the at least one contact of the chip and the metal structure.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: February 17, 2015
    Assignee: Infineon Technologies AG
    Inventor: Petteri Palm
  • Patent number: 8937379
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a trench; mounting an integrated circuit device on the leadframe; forming a top encapsulation on the leadframe and the trench; forming a lead having a lead protrusion and a peripheral groove, the lead protrusion and the peripheral groove formed from etching the trench at a leadframe bottom side; and forming a bottom encapsulation surrounding a lead bottom side of the lead.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: January 20, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Asri Yusof, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8932911
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: January 13, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Torsten Huisinga, Carsten Peters, Andreas Ott, Axel Preusse
  • Patent number: 8907225
    Abstract: A method and an apparatus for mitigating electrical failures caused by intrusive structures. Such structures can be tin whiskers forming on electrical circuits. In an illustrative embodiment, nano-capsules are filled with some type of insulative and adhesive fluid that is adapted to bind to and coat an intrusive structure, e.g., a whisker, making the whisker electrically inactive and thereby reducing the electrical faults that can be caused by the whisker. In another illustrative embodiment, randomly oriented nano-fibers having an elastic modulus higher than tin or any other whisker material is used to arrest a growth or movement of a whisker and further reduce a likelihood that a whisker can cause an electrical fault.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: December 9, 2014
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Nishkamraj U Deshpande, H. Fred Barsun, Ron Shoultz
  • Patent number: 8907495
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Akihiro Kajita, Atsunobu Isobayashi, Tatsuro Saito
  • Patent number: 8872279
    Abstract: An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: David R. Greenberg, Jean-Olivier Plouchart, Alberto Valdes-Garcia
  • Patent number: 8860198
    Abstract: According to an exemplary embodiment, a dual compartment semiconductor package includes a conductive clip having first and second compartments. The first compartment is electrically and mechanically connected to a top surface of the first die. The second compartment electrically and mechanically connected to a top surface of a second die. The dual compartment semiconductor package also includes a groove formed between the first and second compartments, the groove preventing contact between the first and second dies. The dual compartment package electrically connects the top surface of the first die to the top surface of the second die. The first die can include an insulated-gate bipolar transistor (IGBT) and the second die can include a diode. A temperature sensor can be situated adjacent to, over, or within the groove for measuring a temperature of the dual compartment semiconductor package.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: October 14, 2014
    Assignee: International Rectifier Corporation
    Inventor: Henning M. Hauenstein
  • Patent number: 8791576
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8779574
    Abstract: A semiconductor die that includes a plurality of non-metallic slots that extend through a current routing line is disclosed. The semiconductor die comprises a semiconductor circuit that includes a plurality of semiconductor components and a current trace line that is coupled to a first semiconductor component. Further, the semiconductor die comprises a current routing line that is coupled with the current trace line. The current routing line includes a plurality of non-metallic slots that extend through the current routing line.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: July 15, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: John R. Agness, Mingying Gu
  • Patent number: 8759962
    Abstract: Various methods and apparatus for establishing thermal pathways for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor chip that has a substrate and a first active circuitry portion extending a first distance into the substrate. A barrier is formed in the first semiconductor chip that surrounds but is laterally separated from the first active circuitry portion and extends into the substrate a second distance greater than the first distance.
    Type: Grant
    Filed: October 27, 2012
    Date of Patent: June 24, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Michael Z. Su
  • Patent number: 8749064
    Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyoshi Maekawa, Kenichi Mori
  • Patent number: 8710660
    Abstract: A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tien-I Bao
  • Patent number: 8669182
    Abstract: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: March 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Daniel C. Edelstein
  • Patent number: 8669177
    Abstract: A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the first metal film, a layer containing Ti and Si is formed on the surface of the conductor.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: March 11, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takahiro Kouno, Shinichi Akiyama, Hirofumi Watatani, Tamotsu Owada
  • Patent number: 8659156
    Abstract: An electromigration and stress migration enhancement liner is provided for use in an interconnect structure. The liner includes a metal that has a thickness at a bottom of the at least one via opening and on an exposed portion of an underlying conductive feature that is greater than a remaining thickness that is located on exposed sidewalls of the interconnect dielectric material. The thinner portion of the electromigration and stress migration enhancement liner is located between the interconnect dielectric material and an overlying diffusion barrier. The thicker portion of the electromigration and stress migration enhancement liner is located between the underlying conductive feature and the diffusion barrier as well as between an adjacent dielectric capping layer and the diffusion barrier. The remainder of the at least one via opening is filled with an adhesion layer and a conductive material.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Baozhen Li
  • Patent number: 8653664
    Abstract: A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: February 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8642444
    Abstract: Disclosed herein is a method of manufacturing a bonded substrate, including the steps of: forming a first bonding layer on a surface on one side of a semiconductor substrate; forming a second bonding layer on a surface on one side of a support substrate; adhering the first bonding layer and the second bonding layer to each other; a heat treatment for bonding the first bonding layer and the second bonding layer to each other; and thinning the semiconductor substrate from a surface on the other side of the semiconductor substrate to form a semiconductor layer.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: February 4, 2014
    Assignee: Sony Corporation
    Inventor: Nobutoshi Fujii
  • Patent number: 8633101
    Abstract: A manufacturing method of a semiconductor device including an electrode having low contact resistivity to a nitride semiconductor is provided. The manufacturing method includes a carbon containing layer forming step of forming a carbon containing layer containing carbon on a nitride semiconductor layer, and a titanium containing layer forming step of forming a titanium containing layer containing titanium on the carbon containing layer. A complete solid solution Ti (C, N) layer of TiN and TiC is formed between the titanium containing layer and the nitride semiconductor layer. As a result, the titanium containing layer comes to be in ohmic contact with the nitride semiconductor layer throughout the border therebetween.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: January 21, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masahiro Sugimoto, Akinori Seki, Akira Kawahashi, Yasuo Takahashi, Masakatsu Maeda
  • Patent number: 8624395
    Abstract: An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Conal E. Murray, Ping-Chuan Wang, Chih-Chao Yang
  • Patent number: 8592107
    Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: November 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guo-Tsai Huang, Fu-Jye Liang, Li-Jui Chen, Chih-Ming Ke
  • Patent number: 8580687
    Abstract: One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a workpiece; forming a dielectric barrier layer over the workpiece; forming an opening through the dielectric barrier layer; forming a seed layer over the dielectric barrier layer and within the dielectric barrier layer opening; and electroplating a first fill layer on the seed layer.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 12, 2013
    Assignee: Infineon Technologies AG
    Inventors: Gerald Dallmann, Dirk Meinhold, Alfred Vater
  • Publication number: 20130140701
    Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.
    Type: Application
    Filed: January 30, 2013
    Publication date: June 6, 2013
    Applicant: International Rectifier Corporation
    Inventor: International Rectifier Corporation
  • Patent number: 8446012
    Abstract: A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: May 21, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I. Bao
  • Patent number: 8432037
    Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: April 30, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyoshi Maekawa, Kenichi Mori
  • Patent number: 8432031
    Abstract: A semiconductor die that includes a plurality of non-metallic slots that extend through a current routing line is disclosed. The semiconductor die comprises a semiconductor circuit that includes a plurality of semiconductor components and a current trace line that is coupled to a first semiconductor component. Further, the semiconductor die comprises a current routing line that is coupled with the current trace line. The current routing line includes a plurality of non-metallic slots that extend through the current routing line.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: April 30, 2013
    Assignee: Western Digital Technologies, Inc.
    Inventors: John R. Agness, Mingying Gu
  • Patent number: 8426307
    Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: April 23, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Cheng-Lin Huang
  • Patent number: 8378490
    Abstract: A method of integrated circuit fabrication is provided, and more particularly fabrication of a semiconductor apparatus with a metallic alloy. An exemplary structure for a semiconductor apparatus comprises a first silicon substrate having a first contact comprising a silicide layer between the substrate and a first metal layer; a second silicon substrate having a second contact comprising a second metal layer; and a metallic alloy between the first metal layer of the first contact and the second metal layer of the second contact.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: February 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chyi-Tsong Ni, I-Shi Wang, Hsin-Kuei Lee, Ching-Hou Su
  • Patent number: 8354751
    Abstract: An interconnect structure having enhanced electromigration resistance is provided in which a lower portion of a via opening includes a multi-layered liner. The multi-layered liner includes, from a patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a metal-containing hard mask. The multi-material layer includes a first material layer comprised of residue from an underlying dielectric capping layer, and a second material layer comprised of residue from an underlying metallic capping layer. The present invention also provides a method of fabricating such an interconnect structure which includes the multi-layered liner within a lower portion of a via opening formed within a dielectric material.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: David V. Horak, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8329360
    Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guo-Tsai Huang, Fu-Jye Liang, Li-Jui Chen, Chih-Ming Ke
  • Patent number: 8278759
    Abstract: A structure for measuring misalignment of patterns may include a first wiring and a second wiring. The first wiring may include a first lower pattern and a first upper pattern. The first upper pattern may extend in a y-direction, and a first end portion of the first upper pattern that is relatively further toward (proximal to) a negative y-direction may contact the first lower pattern. The second wiring may include a second lower pattern and a second upper pattern. The second upper pattern may extend in the y-direction, a second end portion of the second upper pattern that is relatively further toward (proximal to) a positive y-direction may contact the second lower pattern. The second wiring may be spaced apart from the first wiring along the negative y-direction.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: October 2, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Wan-Seob Kim
  • Patent number: 8247905
    Abstract: The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Qiang Huang, John P. Hummel, Lubomyr T. Romankiw, Mary B. Rothwell
  • Patent number: 8232643
    Abstract: Lead free solder interconnections for integrated circuits. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of material is formed on the input/output terminal of the integrated circuit. A lead free solder connector is formed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. An intermetallic compound is formed at the interface between the cap layer and the lead free solder connector. A solder connection is formed between the input/output terminal of the integrated circuit and the metal finish pad that is less than 0.5 weight percent copper, and the intermetallic compound is substantially free of copper.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: July 31, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chun Chuang, Ching-Wen Hsiao, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 8222086
    Abstract: A plurality of FPGA dice is disposed upon a semiconductor substrate. In order both to connect thousands of signal interconnect lines between the plurality of FPGA dice and to supply the immense power required, it is desired that the substrate construction include two different portions, each manufactured using incompatible processes. The first portion is a signal interconnect structure containing a thin conductor layers portion characterized as having a plurality of thin, fine-pitch conductors. The second portion is a power connection structure that includes thick conductors and vertical through-holes. The through-holes contain conductive material and supply power to the FPGA dice from power bus bars located at the other side of the semiconductor substrate. The portions are joined at the wafer level by polishing the wafer surfaces within a few atoms of flatness and subsequent cleaning. The portions are then fusion bonded together or combined using an adhesive material.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: July 17, 2012
    Assignee: Research Triangle Institute
    Inventor: Robert O. Conn
  • Patent number: 8188600
    Abstract: The present invention provides a semiconductor device which is capable of enhancing adhesion at an interface between a wire-protection film and copper, suppressing dispersion of copper at the interface to avoid electromigration and stress-inducing voids, and having a highly reliable wire. An interlayer insulating film, and a first etching-stopper film are formed on a semiconductor substrate on which a semiconductor device is fabricated. A first alloy-wire covered with a first barrier metal film is formed on the first etching-stopper film by a damascene process. The first alloy-wire is covered at an upper surface thereof with a first wire-protection film. The first wire-protection film covering an upper surface of the first alloy-wire contains at least one metal among metals contained in the first alloy-wire.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: May 29, 2012
    Assignee: NEC Corporation
    Inventors: Mari Amano, Munehiro Tada, Yoshihiro Hayashi
  • Patent number: 8159068
    Abstract: A semiconductor device includes: a semiconductor layer composed of one of GaAs based semiconductor, InP-based semiconductor, and GaN-based semiconductor; a first silicon nitride film that is provided on the semiconductor layer, and of which an end portion is in contact with a surface of the semiconductor layer; a protective film that is composed of one of polyimide and benzocyclobutene, and is provided on the semiconductor layer and the first silicon nitride film, the protective film covering the end portion of the first silicon nitride film; and a first metallic layer that is composed of one of titanium, tantalum and platinum, and is continuously provided from a first portion located between the semiconductor layer and the protective film to a second portion located between the end portion of the first silicon nitride film and the protective film, the first metallic layer being in contact with the surface of the semiconductor layer and a surface of the end portion of the first silicon nitride film.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: April 17, 2012
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventors: Takeshi Hishida, Tsutomu Igarashi
  • Patent number: 8138603
    Abstract: An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, a design structure of the IC interconnect and a method of manufacture of the IC interconnect is provided. The structure has electro-migration immunity and redundancy of design, which includes a plurality of wires laid out in parallel and each of which are coated with a liner material. Two adjacent of the wires are physically contacted to each other.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Conal E. Murray, Ping-Chuan Wang, Chih-Chao Yang