Abstract: The present invention relates to a semiconductor device having trench gates. The semiconductor device includes the following: a first semiconductor layer; a first semiconductor region selectively disposed in the upper layer of the first semiconductor layer; a second semiconductor region in contact with the first semiconductor region; a third semiconductor region on the bottom surfaces of the first and second semiconductor regions; gate trenches provided to penetrate the first and third semiconductor regions in the thickness direction of the first and third semiconductor regions to reach the inside of the first semiconductor layer; a field-reducing region on the bottom of each gate trench; and connection layers arranged in the first semiconductor layer at intervals so as to be each in contact with at least one of sidewalls of the gate trenches, the connection layers each electrically connecting the field-reducing region to the third semiconductor region.

Abstract: A semiconductor device is manufactured by implanting impurity ions in one surface of a semiconductor substrate made of silicon carbide; irradiating a region of the semiconductor substrate implanted with the impurity ions with laser light of a wavelength in the ultraviolet region; and forming, on a surface of a high-concentration impurity layer formed by irradiating with the laser light, an electrode made of metal in ohmic contact with the high-concentration impurity layer. When irradiating with the laser light, a first concentration peak of the impurity ions that exceeds a solubility limit concentration of the impurity ions in silicon carbide is formed in a surface region near the one surface of the semiconductor substrate within the high-concentration impurity layer.

Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

Abstract: A method of determining whether a silicon-carbide semiconductor device, which has a metal oxide semiconductor (MOS) gate structure and a built-in diode, is a conforming product. The method includes measuring an ON voltage of the silicon carbide semiconductor device, passing a forward current through the built-in diode of the silicon carbide semiconductor device, measuring another ON voltage of the silicon carbide semiconductor device, which is the ON voltage of the silicon carbide semiconductor device after passing the forward current, calculating a rate of change between the ON voltage and the another ON voltage, and determining that the silicon carbide semiconductor device is a conforming product unless the calculated rate of change is less than 3%.

Abstract: In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer, depositing a second epitaxial layer on the first epitaxial layer, implanting the second epitaxial layer to form a p-field termination region, depositing a third epitaxial layer on the p-field termination layer and forming trenches in the third epitaxial layer. The trenches include a trench gate of the transistor and a termination trench.

Abstract: A semiconductor device having a semiconductor substrate that includes first to third epitaxial layers provided sequentially on a starting substrate, the third epitaxial layer forming a pn junction with the second epitaxial layer, and including a plurality of first semiconductor regions formed on a second semiconductor region. The semiconductor device further includes a plurality of trenches penetrating the first and second semiconductor regions to reach the second epitaxial layer, a plurality of gate electrodes provided in the trenches respectively via a gate insulating film, a metal film in ohmic contact with the first semiconductor regions, a first electrode electrically connected to the first semiconductor regions via the metal film, and a second electrode provided at a back surface of the starting substrate. Each of the starting substrate and the first to third epitaxial layers contains silicon carbide.

Abstract: A semiconductor device includes an NMOS device formed on a first substrate bonded with a second substrate having a PMOS device formed thereon, with the bonding achieved by contacting a first wiring layer formed on the NMOS device with a second wiring layer formed on the PMOS device.

Abstract: A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.

Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.

Abstract: A GaN diode EMP arrestor exhibits breakdown in <10 ns at reverse-bias voltage >20 kV. Additionally, the arrestor exhibits avalanche ruggedness at 1 kA/cm2 in a 1 mm2 device (i.e. 10 A absolute current) over a period of 500 ns following the onset of breakdown. Finally, the specific on-resistance in the forward direction is <20 m? cm2.

Abstract: A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.

Abstract: A silicon carbide device includes a silicon carbide body with a trench gate structure that extends from a first surface into the silicon carbide body. A body region is in contact with an active sidewall of the trench gate structure. A source region is in contact with the active sidewall and located between the body region and the first surface. The body region includes a first body portion directly below the source region and distant from the active sidewall. In at least one horizontal plane parallel to the first surface, a dopant concentration in the first body portion is at least 150% of a reference dopant concentration in the body region at the active sidewall and a horizontal extension of the first body portion is at least 20% of a total horizontal extension of the body region.

Abstract: Provided are a memory structure and a method for manufacturing the same. The memory structure includes a capacitor and a transistor disposed thereon and electrically connected thereto. The transistor includes a first and a source/drain layers, a channel pillar, a gate, a gate dielectric layer, a doped layer, and a spacer layer. The first source/drain layer is electrically connected to the capacitor. The channel pillar is on the first source/drain layer. The gate is on a sidewall of the channel pillar. The gate dielectric layer is between the gate and the channel pillar. The doped layer is on the sidewall of the channel pillar and above the gate. The spacer layer is between the gate and the first source/drain layer and between the gate and the doped layer. The second source/drain layer is on or in the channel pillar.

Abstract: A semiconductor device according to an embodiment includes a gate electrode, a gate insulating layer, and a silicon carbide layer. The silicon carbide layer includes at least one first element selected from the group consisting of S, Se, Te, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, and W. The first distance between a first position and an interface between the gate insulating layer and the silicon carbide layer is equal to or less than 20 nm, and the first position is a position where a concentration of the first element is maximized. The second distance between a second position and the interface is equal to or less than 20 nm, second position is a position where a concentration of the first element is 1/10 of a concentration of the first element at the first position, and the second position is farther from the interface than the first position.

Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.

Abstract: A silicon carbide semiconductor device includes a drift layer having a first conductivity type and a surface in which an active region is defined; a plurality of first doped regions having a second conductivity and arranged within the active region; a plurality of second doped regions having a second conductivity and arranged within the active region; and a metal layer disposed on the surface of the drift layer and forming a Schottky contact with the drift layer. Each of the first doped regions has a first minimum width and a first area and are spaced from each other by a first minimum spacing Each of the second doped regions has a second minimum width greater than the first minimum width and a second area greater than the first area and are spaced from the first doped region by a second minimum spacing less than the first minimum spacing.

Abstract: A semiconductor device including a semiconductor substrate, a first semiconductor layer provided on a main surface of the semiconductor substrate, a second semiconductor layer selectively provided on a surface of the first semiconductor layer, a plurality of first and second semiconductor regions selectively provided in the second semiconductor layer at a surface thereof, and a plurality of trenches provided in a striped pattern that extends in a first direction.

Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce the breakdown voltage of the terminal part. In the SiC-MOSFET with the built-in Schottky diode, a source electrode forming non-ohmic connection such as Schottky connection with the second well region is provided on the second well region formed below a gate pad in the terminal part. By the absence of ohmic connection between the second well region and the source electrode, reduction in breakdown voltage is suppressed at the terminal part.

Abstract: In a guard ring section of a silicon carbide semiconductor device, an electric field relaxation layer for relaxing an electric field is formed in a surface layer portion of a drift layer, so that electric field is restricted from penetrating between guard rings. Thus, an electric field concentration is relaxed. Accordingly, a SiC semiconductor device having a required withstand voltage is obtained.

Abstract: Variations in device characteristics in a plane parallel to the principal surface of a semiconductor wafer are suppressed. A semiconductor epitaxial wafer includes a semiconductor wafer and a first conductivity type semiconductor epitaxial layer that is disposed on a principal surface of the semiconductor wafer and contains a first conductivity type impurity, and the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of the impurity in the semiconductor epitaxial layer have a positive correlation in a plane parallel to the principal surface of the semiconductor wafer.

Abstract: A silicon carbide semiconductor device includes a semiconductor element with a MOS structure having: a substrate; a drift layer on the substrate; a base region on the drift layer; a source region on the base region; a trench gate structure having a gate insulation film and a gate electrode in a gate trench disposed from a surface of the source region to be deeper than the base region; an interlayer insulation film covering the gate electrode and the gate insulation film; a source electrode on the interlayer insulation film, the source region and the base region; and a drain electrode. The semiconductor element flows a current when a gate voltage is applied to the gate electrode and a channel region is provided in a portion of the base region in contact with the trench gate structure.

Abstract: A vapor phase growth device includes a flow channel defining a space through which a source gas for forming an epi layer flows, a susceptor configured to hold a substrate in a state where the substrate faces the space, and a first member disposed vertically above and opposite to the susceptor, the first member having a thermal expansion coefficient not less than 0.7 times and not more than 1.3 times the thermal expansion coefficient of the substrate. The flow channel includes a holding portion configured to hold the first member.

Abstract: The long-missing polarization-induced two-dimensional hole gas is finally observed in undoped Group III nitride semiconductor structures and in undoped Group II or Group III oxide semiconductor structures. Experimental results providing unambiguous proof that a 2D hole gas in GaN grown on AlN does not need acceptor doping, and can be formed entirely by the difference in the internal polarization fields across the semiconductor heterojunction are presented.

Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.

Abstract: A feeder design is manufactured as a structure in a SiC semiconductor material comprising at least two p-type grids in an n-type SiC material, comprising at least one epitaxially grown p-type region, wherein an Ohmic contact is applied on the at least one epitaxially grown p-type region, wherein an epitaxially grown n-type layer is applied on at least a part of the at least two p-type grids and the n-type SiC material wherein the at least two p-type grids are applied in at least a first and a second regions at least close to the at least first and second corners respectively and that there is a region in the n-type SiC material between the first and a second regions without any grids.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include a first process of causing a stacking fault of a first semiconductor layer to expand. The first semiconductor layer includes silicon carbide and a first element and is provided on a base body including silicon carbide. The first element includes at least one selected from the group consisting of N, P, and As. The method can include a second process of forming a second semiconductor layer on the first semiconductor layer after the first process. The second semiconductor layer includes silicon carbide and the first element. The method can include a third process of forming a third semiconductor layer on the second semiconductor layer. The third semiconductor layer includes silicon carbide and a second element. The second element includes at least one selected from the group consisting of B, Al, and Ga.

Abstract: The nitride semiconductor device includes: a nitride semiconductor layer; a first conductivity type source region provided on a surface of the nitride semiconductor layer; a second conductivity type well region provided in the nitride semiconductor layer and adjacent to the source region in a first direction parallel to the surface and in a second direction intersecting with the first direction; a trench located on the opposite side of the source region with the well region sandwiched therebetween in the first direction; a first conductivity type impurity region located between the well region and the trench; an insulating film provided on a bottom surface of the trench; a gate insulating film provided on the well region; and a gate electrode provided from on the insulating film to on the gate insulating film. A thickness of the insulating film is larger than a thickness of the gate insulating film.

Abstract: A silicon carbide MOSFET includes a plurality of first and second trenches each of which extends a predetermined vertical distance from the top of a source down through a body region and into a current spreading layer (CSL). An insulated gate member is disposed in each first trench. The first trenches are each arranged in a wave-shaped pattern that extends in first and second lateral directions. Each of the second trenches is disposed between a pair of adjacent first trenches in the first lateral direction. A shielding region extends vertically from the bottom of each of the second trenches down into a drift region. A top metal layer fill each of the second trenches and electrically contacts the source region, the body region, the CSL, and the shielding region. A bottom metal layer electrically contacts the drain region.

Abstract: A trench gate MOSFET has at an n-type current spreading region between an n?-type drift region and a p-type base region, a first p+-type region facing a bottom of a trench, and a second p+-type region disposed between adjacent trenches. The first and the second p+-type regions extend parallel to a first direction in which the trench extends and are partially connected by a p+-type connecting portion and thus, disposed in a ladder shape when viewed from the front surface of a semiconductor substrate. The second p+-type region has at a portion of a surface on a drain side, a recessed portion that is recessed toward a source side. One or more recessed portions is provided between connection sites in the second p+-type region for connection with the p+-type connecting portions that are adjacent to each other in the first direction X.

Abstract: Several embodiments of the present technology are directed to semiconductor devices, and systems and associated methods for treating semiconductor devices based on warpage data. In some embodiments, a method can include heating a plurality of semiconductor devices from a first temperature to a second temperature, and determining warpage data at a plurality of points on the surfaces of the semiconductor devices as they are being heated. The method can further comprise applying a multivariate analysis to the surface warpage data to generate a multivariate statistic for each of the semiconductor devices at various sample temperatures. The multivariate statistics can be used to determine whether the semiconductor devices exceed or fall below a threshold limit.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a treatment process is utilized in order to introduce silicon into a p-metal work function layer. By introducing silicon into the p-metal work function layer, subsequently deposited layers which may comprise diffusable materials such as aluminum can be prevented from diffusing through the p-metal work function layer and affect the operation of the device.

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a first semiconductor layer and a first semiconductor region each of a first conductivity type, and a first base region, a second semiconductor layer and a second semiconductor region each of a second conductivity type. The first base region opposes the second semiconductor region in a depth direction. A distribution of point defects in a depth direction from a first surface of the second semiconductor region, opposite a second surface of the second semiconductor region facing toward a front surface of the silicon carbide semiconductor substrate has two peaks at positions deeper than an interface between the first semiconductor layer and the first base region, where a first peak at a deeper position of the two peaks has a greater quantity of the point defects than does a second peak at a shallower position of the two peaks.

Abstract: An epitaxial silicon carbide single crystal wafer having a small depth of shallow pits and having a high quality silicon carbide single crystal thin film and a method for producing the same are provided. The epitaxial silicon carbide single crystal wafer according to the present invention is produced by forming a buffer layer made of a silicon carbide epitaxial film having a thickness of 1 ?m or more and 10 ?m or less by adjusting the ratio of the number of carbon to that of silicon (C/Si ratio) contained in a silicon-based and carbon-based material gas to 0.5 or more and 1.0 or less, and then by forming a drift layer made of a silicon carbide epitaxial film at a growth rate of 15 ?m or more and 100 ?m or less per hour. According to the present invention, the depth of the shallow pits observed on the surface of the drift layer can be set at 30 nm or less.

Abstract: A method of forming a semiconductor device and a semiconductor device are provided. The method includes forming a graphene layer at a first side of a silicon carbide substrate having at least next to the first side a first defect density of at most 500/cm2. An acceptor layer is attached at the graphene layer to form a wafer-stack. The acceptor layer includes silicon carbide having a second defect density higher than first defect density. The wafer-stack is split along a split plane in the silicon carbide substrate to form a device wafer including the graphene layer and a silicon carbide split layer at the graphene layer. An epitaxial silicon carbide layer extending to an upper side of the device wafer is formed on the silicon carbide split layer. The device wafer is further processed at the upper side.

Abstract: The present application discloses a method for a terminal to transmit an uplink data signal configured with a plurality of code blocks in a wireless communication system. Particularly, the method comprises: a step of mapping, within one slot, a plurality of code blocks to resource elements by using a time-first method, for each time block; and a step of transmitting, to a base station, an uplink demodulation reference signal and an uplink data signal which is configured with a plurality of code blocks, wherein the size of the time block to which the time-first method is applied is determined based on a mapping pattern of the uplink demodulation reference signal.

Abstract: A SiC varied-growth-rate layer (2) is formed on a SiC bulk substrate (1) while increasing a growth speed from an initial growth speed of 2.0 ?m/h or less. A speed change rate of the SiC varied-growth-rate layer (2) is 720 ?m/h2 or less. A molar flow ratio of nitrogen to carbon when growth of the SiC varied-growth-rate layer (2) starts is 2.4 or less.

Abstract: A present invention includes the following: a third impurity region having a second conductivity type and disposed in an outer peripheral region that is the outer periphery of a cell arrangement region in which a unit cell is disposed; a field insulating film disposed in the outer peripheral region; an interlayer insulating film; a first main electrode disposed on the interlayer insulating film. The third impurity region includes a fourth impurity region having the second conductivity type, having a higher impurity concentration than the third impurity region. A gate wire and a gate pad are disposed in the outer peripheral region. The fourth impurity region is adjacent to the cell arrangement region, surrounds at least a region below the gate pad, and is electrically connected to the first main electrode.

Abstract: A semiconductor device, a drain electrode terminal supporting the semiconductor device and connected directly to a drain electrode pad, a source electrode terminal connected to a source electrode pad, and a gate electrode terminal are provided, wherein the source electrode terminal includes a wire post, a first lead extending from one end of the wire post, and a second lead extending from another end of the wire post, wherein the source electrode pad and the wire post of the source electrode terminal are connected to each other through a plurality of bonding wires, and wherein the semiconductor device, a surface, supporting the semiconductor device thereon, of the drain electrode terminal, the wire post of the source electrode terminal, the bonding wires, and part of the gate electrode terminal are covered with a mold resin.

Abstract: It is an object of the present invention to provide a silicon carbide substrate having a low defect density that does not contaminate a process device and a silicon carbide semiconductor device including the silicon carbide substrate. A silicon carbide substrate according to the present invention is a silicon carbide substrate including: a substrate inner portion; and a substrate outer portion surrounding the substrate inner portion, wherein non-dopant metal impurity concentration of the substrate inner portion is 1×1016 cm?3 or more, and a region of the substrate outer portion at least on a surface side thereof is a substrate surface region in which the non-dopant metal impurity concentration is less than 1×1016 cm?3.

Abstract: To enhance efficiency of a process of implanting impurities into a silicon carbide semiconductor layer. To provide a method of manufacturing a semiconductor device including a silicon carbide semiconductor layer, the method of manufacturing including: implanting impurities multiple times to an impurity implantation region in the silicon carbide semiconductor layer to different depths, with temperature of the silicon carbide semiconductor layer being set to be equal to or lower than 150° C. In the implanting, impurities may be implanted multiple times to the impurity implantation region to different depths, with temperature of the silicon carbide semiconductor layer being set to be equal to or higher than room temperature.

Abstract: A plurality of trench gate electrodes are formed from an upper surface to reach an intermediate depth of an n-type SiC epitaxial substrate including an n-type drain region on a lower surface and an n-type source region on an upper surface in contact with the source region to be arranged in a direction along the upper surface. Here, at least three side surfaces among four side surfaces of each of the trench gate electrodes having a rectangular planar shape are in contact with a p-type body layer below the source region. In addition, a JFET region in the SiC epitaxial substrate and a source electrode connected to the source region immediately above the JFET region extend along a direction in which the plurality of trench gate electrodes are arranged.

Abstract: In some examples, a semiconductor device includes a substrate, an interlayer insulating film, a gate pad provided on the interlayer insulating film, a source electrode that is provided on the interlayer insulating film, source wiring provided on the interlayer insulating film, and gate wiring that is provided on the interlayer insulating film and is electrically connected to the gate pad. The size of the source wiring is not increased, and a high impurity concentration region having a higher impurity concentration than a drift layer is formed on the surface of the substrate at a location directly below the gate pad.

Abstract: A method for fabricating a semiconductor device includes providing a semiconductor structure including a semiconductor substrate, a plurality of semiconductor fin structures, and a trench insulation layer formed on the semiconductor substrate and surrounding each semiconductor fin structure. The semiconductor fin structures include a plurality of first semiconductor fin structures and a plurality of second semiconductor fin structures. The top surface of the trench insulation layer is leveled with the top surface of the semiconductor fin structures.

Abstract: A semiconductor device includes a first electrode, a silicon carbide substrate having a first surface electrically connected with the first electrode and a second surface opposite to the first surface, an ohmic junction layer disposed on the second surface, and a second electrode disposed on the ohmic junction layer. The ohmic junction layer has a first layer that is directly disposed on the second surface and includes a first silicide of titanium and a first silicide of a metal element other than titanium, and a second layer that is directly disposed on the first layer, includes a second silicide of titanium and a second silicide of the metal element, and has a lower titanium concentration than the first layer.

Abstract: In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.

Abstract: An embodiment relates to a method comprising obtaining a SiC substrate comprising a N+ substrate and a N? drift layer; depositing a first hard mask layer on the SiC substrate and patterning the first hard mask layer; performing a p-type implant to form a p-well region; depositing a second hard mask layer on top of the first hard mask layer; performing an etch back of at least the second hard mask layer to form a sidewall spacer; implanting N type ions to form a N+ source region that is self-aligned; and forming a MOSFET.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of silicon carbide, a device structure provided on top of the first semiconductor layer, a second semiconductor layer of silicon carbide having a higher impurity concentration than the first semiconductor layer, provided under the first semiconductor layer, the second semiconductor layer implementing an ohmic-contact, and a metallic electrode film provided under the second semiconductor layer. A thickness of a carbon-containing region in which carbon-atoms are precipitated between the second semiconductor layer and the metallic electrode film is 10 nm or less.

Abstract: The present invention is a semiconductor module including: first and second drive circuits that perform drive control of at least one pair of first and second switching devices, in which the at least one pair of first and second switching devices and the first and second drive circuits are sealed in a package having a rectangular shape in plan view, and there are provided: a control terminal provided to protrude from a side surface of a first long side out of first and second long sides of the package, and to which a control signal of the first and second drive circuits is inputted; an output terminal provided to protrude from a side surface of the second long side; a first main terminal provided to protrude from a side surface of a first short side out of first and second short sides of the package; and a second main terminal provided to protrude from a side surface of the second short side.