Alloy Containing Aluminum Patents (Class 257/771)
  • Patent number: 10793427
    Abstract: A MEMS device formed in a first semiconductor substrate is sealed using a second semiconductor substrate. To achieve this, an Aluminum Germanium structure is formed above the first substrate, and a polysilicon layer is formed above the second substrate. The first substrate is covered with the second substrate so as to cause the polysilicon layer to contact the Aluminum Germanium structure. Thereafter, eutectic bonding is performed between the first and second substrates so as to cause the Aluminum Germanium structure to melt and form an AlGeSi sealant thereby to seal the MEMS device. Optionally, the Germanium Aluminum structure includes, in part, a layer of Germanium overlaying a layer of Aluminum.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: October 6, 2020
    Assignee: KIONIX, INC.
    Inventors: Martin Heller, Toma Fujita
  • Patent number: 10766767
    Abstract: A MEMS device formed in a first semiconductor substrate is sealed using a second semiconductor substrate. To achieve this, an Aluminum Germanium structure is formed above the first substrate, and a polysilicon layer is formed above the second substrate. The first substrate is covered with the second substrate so as to cause the polysilicon layer to contact the Aluminum Germanium structure. Thereafter, eutectic bonding is performed between the first and second substrates so as to cause the Aluminum Germanium structure to melt and form an AlGeSi sealant thereby to seal the MEMS device. Optionally, the Germanium Aluminum structure includes, in part, a layer of Germanium overlaying a layer of Aluminum.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: September 8, 2020
    Assignee: KIONIX, INC.
    Inventors: Martin Heller, Toma Fujita
  • Patent number: 10319672
    Abstract: A wiring board includes an insulating substrate that is rectangular in a plan view, a plurality of mount electrodes arranged to face each other on a first main surface of the insulating substrate along a pair of opposing sides of the insulating substrate in a plan view, a plurality of terminal electrodes arranged to face each other on a second main surface of the insulating substrate along the pair of opposing sides of the insulating substrate in a perspective plan view, and an inner metal layer arranged inside the insulating substrate and extending in a direction perpendicular to the pair of opposing sides of the insulating substrate in a perspective plan view.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: June 11, 2019
    Assignee: KYOCERA CORPORATION
    Inventors: Michio Imayoshi, Yousuke Moriyama
  • Patent number: 10128151
    Abstract: Devices and methods of fabricating integrated circuit devices via cobalt fill metallization are provided. A method includes, for instance, providing an intermediate semiconductor device having at least one trench, forming at least one layer of semiconductor material on the device, depositing a first cobalt (Co) layer on the second layer, and performing an anneal reflow process on the device. Also provided are intermediate semiconductor devices. An intermediate semiconductor device includes, for instance, at least one trench formed within the device, the trench having a bottom portion and sidewalls, at least one layer of semiconductor material disposed on the device, a first cobalt (Co) layer disposed on the at least one layer of semiconductor material, wherein the at least one layer of semiconductor material includes at least a first semiconductor material and a second semiconductor material.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: November 13, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vimal Kamineni, James Kelly, Praneet Adusumilli, Oscar Van Der Straten, Balasubramanian Pranatharthiharan
  • Patent number: 9013002
    Abstract: An iridium interfacial stack (“IrIS”) and a method for producing the same are provided. The IrIS may include ordered layers of TaSi2, platinum, iridium, and platinum, and may be placed on top of a titanium layer and a silicon carbide layer. The IrIS may prevent, reduce, or mitigate against diffusion of elements such as oxygen, platinum, and gold through at least some of its layers.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: April 21, 2015
    Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventor: David James Spry
  • Patent number: 8981570
    Abstract: A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: March 17, 2015
    Assignee: Unimicron Technology Corporation
    Inventors: Tzyy-Jang Tseng, Dyi-Chung Hu, Ying-Chih Chan
  • Patent number: 8975670
    Abstract: A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors, and where the second transistors include monocrystalline regions.
    Type: Grant
    Filed: July 22, 2012
    Date of Patent: March 10, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20150054163
    Abstract: A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The first layer includes a via opening and a tapered portion proximate to the via opening. The metal layer is formed over the via opening and the tapered portion of the first layer. The metal layer is substantially free from gaps and voids.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Patent number: 8963325
    Abstract: According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Baik-woo Lee, Young-hun Byun, Seong-woon Booh, Chang-mo Jeong
  • Publication number: 20140353833
    Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) stress compensation layers that reduce stress on one or more underlying semiconductor devices, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices. A stressed element is located within a back-end-of-the-line stack at a position overlying the one or more semiconductor devices. A stressing layer is located over the stressed element induces a stress upon the stressed element. A stress compensation layer, located over the stressed element, provides a counter-stress to reduce the stress induced on the stressed element by the stressing layer. By reducing the stress induced on the stressed element, stress on the semiconductor substrate is reduced, improving uniformity of performance of the one or more semiconductor devices.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 4, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Peng, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Publication number: 20140327062
    Abstract: An electronic device may include a substrate, an oxide dielectric layer on the substrate, an interface layer on the oxide dielectric layer, and an electrode on the interface layer. The oxide dielectric layer may include an aluminum oxide layer between first and second zirconium oxide layers. The interface layer may have a first formation enthalpy, and the oxide dielectric layer may be between the substrate and the interface layer. The electrode may have a second formation enthalpy higher than the first formation enthalpy, and the interface layer may be between the oxide dielectric layer and the electrode.
    Type: Application
    Filed: November 6, 2013
    Publication date: November 6, 2014
    Inventors: Ki-Yeon PARK, Hyun-Jun Kim, Se-Hyoung Ahn, Young-Geun Park, Ki-Vin Im
  • Patent number: 8872341
    Abstract: One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gerald Dallmann, Heike Rosslau, Norbert Urbansky, Scott Wallace
  • Patent number: 8872194
    Abstract: An illumination device is disclosed. The illumination device includes a light source a pre-dip material that at least partially encapsulates the light source. The pre-dip material may include one or both of thermally-conductive particles and a cyclo-aliphatic composition. The pre-dip material may further include a resin and a hardener for the resin. Methods of manufacturing an illumination device are also disclosed.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: October 28, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Kum Soon Wong, Yean Chon Yaw, Kit Lai Wong
  • Patent number: 8866298
    Abstract: A semiconductor component includes a semiconductor die and a copper-containing electrical conductor. The semiconductor die has a semiconductor device region, an aluminum-containing metal layer on the semiconductor device region, and at least one additional metal layer on the aluminum-containing metal layer which is harder than the aluminum-containing metal layer. The copper-containing electrical conductor is bonded to the at least one additional metal layer of the semiconductor die via an electrically conductive coating of the copper-containing electrical conductor which is softer than the copper of the copper-containing electrical conductor.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: 8860135
    Abstract: A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: October 14, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Min-Chuan Tsai, Chien-Hao Chen, Wei-Yu Chen, Chin-Fu Lin, Jing-Gang Li, Min-Hsien Chen, Jian-Hong Su
  • Patent number: 8860224
    Abstract: A device includes a top metal layer; a UTM line over the top metal layer and having a first thickness; and a passivation layer over the UTM line and having a second thickness. A ratio of the second thickness to the first thickness is less than about 0.33.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: October 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wen Chen, Chuang-Han Hsieh, Kun-Yu Lin, Kuan-Chi Tsai
  • Patent number: 8754529
    Abstract: A MEMS device comprises a substrate for manufacturing a moving MEMS component is divided into two electrically isolated conducting regions to allow the moving MEMS component and a circuit disposed on its surface to connect electrically with another substrate below respectively through their corresponding conducting regions, thereby the electrical conducting paths and manufacturing process can be simplified.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: June 17, 2014
    Assignee: Miradia, Inc.
    Inventors: Yu-Hao Chien, Hua-Shu Wu, Shih-Yung Chung, Li-Tien Tseng, Yu-Te Yeh
  • Publication number: 20140151889
    Abstract: Techniques are disclosed for enhancing the dielectric breakdown performance of integrated circuit (IC) interconnects. The disclosed techniques can be used to selectively etch the dielectric layer of an IC to form a recess, for example, between a given pair of adjacent/neighboring interconnects (e.g., metal lines). Thereafter, a layer of dielectric material of higher dielectric breakdown field (Ec) than the surrounding/underlying dielectric material (or other suitable insulator, as will be apparent in light of this disclosure) may be deposited/grown so as to substantially conform to the topology provided by the adjacent/neighboring interconnects and etched recess. In some cases, this dielectric layer may help to prevent or otherwise reduce: (1) dielectric breakdown between the adjacent/neighboring interconnects by locally increasing the dielectric breakdown voltage (VBD); and/or (2) diffusion of the interconnect fill metal into the surrounding/underlying dielectric material.
    Type: Application
    Filed: December 4, 2012
    Publication date: June 5, 2014
    Inventors: Pavel S. Plekhanov, Kevin J. Fischer, Qiang Fu, Hiroki Hiramatsu
  • Patent number: 8741738
    Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a semiconductor apparatus with a metallic alloy. An exemplary structure for an apparatus comprises a first silicon substrate; a second silicon substrate; and a contact connecting each of the first and second substrates, wherein the contact comprises a Ge layer adjacent to the first silicon substrate, a Cu layer adjacent to the second silicon substrate, and a metallic alloy between the Ge layer and Cu layer.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Hsun Chiu, Ting-Ying Chien, Ching-Hou Su, Chyi-Tsong Ni
  • Publication number: 20140145341
    Abstract: A semiconductor device includes: a semiconductor element that includes an electrode layer on a surface of the semiconductor element; a low-strength layer that is provided on a surface of the electrode layer; a bonding layer that is provided on a surface of the low-strength layer; and a conductive plate that is provided on a surface of the bonding layer. Strength of the bonding layer is higher than strength of the electrode layer, and strength of the low-strength layer is lower than the strength of the electrode layer.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 29, 2014
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Toru TANAKA
  • Patent number: 8735905
    Abstract: Provided is a method for producing inexpensive and high-quality aluminum nitride crystals. Gas containing N atoms is introduced into a melt of a Ga—Al alloy, whereby aluminum nitride crystals are made to epitaxially grow on a seed crystal substrate in the melt of the Ga—Al alloy. A growth temperature of aluminum nitride crystals is set at not less than 1000 degrees C. and not more than 1500 degrees C., thereby allowing GaN to be decomposed into Ga metal and nitrogen gas.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: May 27, 2014
    Assignees: Sumitomo Metal Mining Co., Ltd., Tohoku University
    Inventors: Hiroyuki Fukuyama, Masayoshi Adachi, Akikazu Tanaka, Kazuo Maeda
  • Patent number: 8716862
    Abstract: An integrated circuit includes a gate of a transistor disposed over a substrate. A connecting line is disposed over the substrate. The connecting line is coupled with an active area of the transistor. A level difference between a top surface of the connecting line and a top surface of the gate is about 400 ? or less. A via structure is coupled with the gate and the connecting line. A metallic line structure is coupled with the via structure.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chii-Ping Chen, Dian-Hau Chen
  • Patent number: 8669652
    Abstract: To provide an inexpensive lead component which can be easily connected to a semiconductor chip and which has satisfactory connectability. There is provided a lead component including a base material having a connection part for connecting to a semiconductor chip, comprising: a solder part having a Zn layer made of a Zn-bonding material rolled and clad-bonded on the base material, and an Al layer made of an Al-bonding material rolled and clad-bonded on the Zn layer, in a prescribed region including the connection part on the base material; and the solder part further comprising a metal thin film composed of one kind or two kinds or more of Au, Ag, Cu, Ni, Pd, and Pt covering a surface of the Al layer.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: March 11, 2014
    Assignee: Hitachi Cable, Ltd.
    Inventors: Shohei Hata, Yuichi Oda, Kazuma Kuroki, Hiromitsu Kuroda
  • Patent number: 8653668
    Abstract: A bonding structure and a copper bonding wire for semiconductor device include a ball-bonded portion formed by bonding to the aluminum electrode a ball formed on a front end of the copper bonding wire. After being heated at any temperature between 130° C. and 200° C., the ball-bonded portion exhibits a relative compound ratio R1 of 40-100%, the relative compound ratio R1 being a ratio of a thickness of a Cu—Al intermetallic compound to thicknesses of intermetallic compounds that are composed of Cu and Al and formed on a cross-sectional surface of the ball-bonded portion.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: February 18, 2014
    Assignees: Nippon Steel & Sumikin Materials Co., Ltd., Nippon Micrometal Corporation
    Inventors: Tomohiro Uno, Takashi Yamada, Atsuo Ikeda
  • Patent number: 8629559
    Abstract: A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
  • Patent number: 8525330
    Abstract: Provided is a connecting part for a semiconductor device including a semiconductor element, a frame, and a connecting part which connects the semiconductor element and the frame to each other, in which an interface between the connecting part and the semiconductor element and an interface between the connecting part and the frame respectively have the area of Al oxide film which is more than 0% and less than 5% of entire area of the respective interfaces. The connecting part has an Al-based layer and first and second Zn-based layers on main surfaces of the Al-based layer, a thickness ratio of the Al-based layer relative to the Zn-based layers being less than 0.59.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: September 3, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Masahide Okamoto, Osamu Ikeda, Yuki Murasato
  • Patent number: 8519539
    Abstract: A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: August 27, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Ha Jung, Baek Mann Kim, Soo Hyun Kim, Young Jin Lee, Sun Woo Hwang, Jeong Tae Kim
  • Publication number: 20130214418
    Abstract: A semiconductor device package structure includes a substrate with a via contact pad on top surface of the substrate, a terminal pad on bottom surface of the substrate and a conductive through hole through the substrate, wherein the conductive through hole electrically couples the via contact pad and the terminal pad on the substrate; a die having bonding pads thereon, wherein the die is formed on the top surface of the substrate; a slanting structure formed adjacent to at least one side of the die for carrying conductive traces; and a conductive trace formed on upper surface of the slanting structure to offer path between the bonding pads and the via contact pad.
    Type: Application
    Filed: March 21, 2013
    Publication date: August 22, 2013
    Applicant: King Dragon International Inc.
    Inventor: King Dragon International Inc.
  • Patent number: 8476645
    Abstract: Thermal management solutions for higher power LEDs. In accordance with embodiments, a heat sink, preferably copper, is connected directly to the thermal pad of an LED. Directly connecting the LED thermal pad to the copper heat sink reduces the thermal resistance between the LED package and the heat sink, and more efficiently conducts heat away from the LED through the copper heat sink. In embodiments, the copper heat sink is directly soldered to the LED thermal pad.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: July 2, 2013
    Assignee: Uni-Light LLC
    Inventors: Gary A. McDaniel, Chip Akins
  • Publication number: 20130161820
    Abstract: A method for bonding two silicon substrates and a corresponding system of two silicon substrates. The method includes: providing first and second silicon substrates; depositing a first bonding layer of pure aluminum or of aluminum-copper having a copper component between 0.1 and 5% on a first bonding surface of the first silicon substrate; depositing a second bonding layer of germanium above the first bonding surface or above a second bonding surface of the second silicon substrate; subsequently joining the first and second silicon substrates, so that the first and the second bonding surfaces lie opposite each other; and implementing a thermal treatment step to form an eutectic bonding layer of aluminum-germanium or containing aluminum-germanium as the main component, between the first silicon substrate and the second silicon substrate, spikes which contain aluminum as a minimum and extend into the first silicon substrate, forming at least on the first bonding surface.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 27, 2013
    Inventors: Julian GONSKA, Heribert Weber, Jens Frey, Timo Schary, Thomas Mayer
  • Patent number: 8466569
    Abstract: An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: June 18, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Stephen Arlon Meisner, Scott R. Summerfelt
  • Patent number: 8450209
    Abstract: A method of forming a non-volatile memory device includes providing a substrate having a surface and forming a first dielectric overlying the surface, forming a first wiring comprising aluminum material over the first dielectric, forming a silicon material over the aluminum material to form an intermix region consuming a portion of the silicon material and aluminum material, annealing to formation a first alloy from the intermix region, forming a p+ impurity polycrystalline silicon over the first alloy material, forming a first wiring structure from at least a portion of the first wiring, forming a resistive switching element comprising an amorphous silicon material formed over the p+ polycrystalline silicon, and forming a second wiring structure comprising at least a metal material over the resistive switching element.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: May 28, 2013
    Assignee: Crossbar, Inc.
    Inventor: Scott Brad Herner
  • Publication number: 20130127026
    Abstract: In a connecting material of the present invention, a Zn series alloy layer is formed on an outermost surface of an Al series alloy layer. In particular, in the connecting material, an Al content of the Al series alloy layer is 99 to 100 wt.% or a Zn content of the Zn series alloy layer is 90 to 100 wt.%. By using this connecting material, the formation of an Al oxide film on the surface of the connecting material at the time of the connection can be suppressed, and preferable wetness that cannot be obtained with the Zn—Al alloy can be obtained. Further, a high connection reliability can be achieved when an Al series alloy layer is left after the connection, since the soft Al thereof functions as a stress buffer material.
    Type: Application
    Filed: January 18, 2013
    Publication date: May 23, 2013
    Inventors: Osamu IKEDA, Masahide OKAMOTO
  • Patent number: 8446003
    Abstract: A semiconductor device includes a multilayer wiring substrate and a double-sided multi-electrode chip. The double-sided multi-electrode chip includes a semiconductor chip and has multiple electrodes on both sides of the semiconductor chip. The double-sided multi-electrode chip is embedded in the multilayer wiring substrate in such a manner that the double-sided multi-electrode chip is not exposed outside the multilayer wiring substrate. The electrodes of the double-sided multi-electrode chip are connected to wiring layers of the multilayer wiring substrate.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: May 21, 2013
    Assignee: DENSO CORPORATION
    Inventors: Atsushi Komura, Yasuhiro Kitamura, Nozomu Akagi, Yasutomi Asai
  • Patent number: 8426972
    Abstract: A semiconductor device has: a semiconductor substrate; and an upper surface electrode laminated on an upper surface of the semiconductor substrate, wherein at least one portion of the upper surface electrode includes a first layer formed on an upper surface side of the semiconductor substrate, a second layer formed on an upper surface side of the first layer, a third layer in contact with the upper surface of the second layer, and a fourth layer formed on an upper surface side of the third layer. The first layer is a barrier metal layer. The second layer is an Al (aluminum) layer. The third layer is one of an Al—Si (aluminum-silicon alloy) layer, an Al—Cu (aluminum-copper alloy) layer and an Al—Si—Cu (aluminum-silicon-copper alloy) layer. The fourth layer is a solder joint layer.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: April 23, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Keisuke Kimura
  • Publication number: 20130092948
    Abstract: The semiconductor device having flip chip structure includes: an insulating substrate; a signal wiring electrode disposed on the insulating substrate; a power wiring electrode disposed on the insulating substrate or disposed so as to pass through the insulating substrate; a semiconductor chip disposed in flip chip configuration on the insulating substrate and comprising a semiconductor substrate, a source pad electrode and a gate pad electrode disposed on a surface of the semiconductor substrate, and a drain pad electrode disposed on a back side surface of the semiconductor substrate; agate connector disposed on the gate pad electrode; and a source connector disposed on the source pad electrode. The gate connector, the gate pad electrode and the signal wiring electrode are bonded, and the source connector, the source pad electrode and the power wiring electrode are bonded, by using solid phase diffusion bonding.
    Type: Application
    Filed: October 18, 2011
    Publication date: April 18, 2013
    Applicant: ROHM CO., LTD.
    Inventor: Takukazu OTSUKA
  • Publication number: 20130087919
    Abstract: A through-silicon via stack package contains package units. Each package unit includes a semiconductor chip; a through-silicon via formed in the semiconductor chip; a first metal line formed on an upper surface and contacting a portion of a top surface of the through-silicon via; and a second metal line formed on a lower surface of the semiconductor chip and contacting a second portion of a lower surface of the through-silicon via. When package units are stacked, the second metal line formed on the lower surface of the top package unit and the first metal line formed on the upper surface of the bottom package unit are brought into contact with the upper surface of the through-silicon via of the bottom package unit and the lower surface of the through-silicon via of the top package unit, respectively. The stack package is lightweight and compact, and can form excellent electrical connections.
    Type: Application
    Filed: November 27, 2012
    Publication date: April 11, 2013
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Hynix Semiconductor Inc.
  • Publication number: 20130082387
    Abstract: In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.
    Type: Application
    Filed: September 29, 2011
    Publication date: April 4, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thilo Stolze, Guido Strotmann, Karsten Guth
  • Patent number: 8395261
    Abstract: A semiconductor device includes an electrode pad provided on a semiconductor chip, the electrode pad includes aluminum (Al) of between 50% wt. and 99.9% wt. and further includes copper (Cu), a coupling ball that primarily includes Cu, the coupling ball being coupled to the electrode pad so that a CuAl2 layer, a CuAl layer, a layer including one of Cu9Al4 and Cu3Al2, and the coupling ball are vertically stacked in this order on the electrode pad, and an encapsulating resin that includes a halogen of less than or equal to 1000 ppm, the encapsulating resin covering at least the electrode pad and a junction between the electrode pad and the coupling ball.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: March 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takekazu Tanaka, Kouhei Takahashi, Seiji Okabe
  • Patent number: 8390125
    Abstract: An integrated circuit structure includes a semiconductor substrate, a through-silicon via (TSV) extending into the semiconductor substrate, a pad formed over the semiconductor substrate and spaced apart from the TSV, and an interconnect structure formed over the semiconductor substrate and electrically connecting the TSV and the pad. The interconnect structure includes an upper portion formed on the pad and a lower portion adjacent to the pad, and the upper portion extends to electrically connect the TSV.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: March 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hong Tseng, Sheng Huang Jao
  • Patent number: 8378490
    Abstract: A method of integrated circuit fabrication is provided, and more particularly fabrication of a semiconductor apparatus with a metallic alloy. An exemplary structure for a semiconductor apparatus comprises a first silicon substrate having a first contact comprising a silicide layer between the substrate and a first metal layer; a second silicon substrate having a second contact comprising a second metal layer; and a metallic alloy between the first metal layer of the first contact and the second metal layer of the second contact.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: February 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chyi-Tsong Ni, I-Shi Wang, Hsin-Kuei Lee, Ching-Hou Su
  • Patent number: 8350303
    Abstract: A display device in which an Al alloy film and a conductive oxide film are directly connected without interposition of refractory metal and some or all of Al alloy components deposit or are concentrated at the interface of contact between the Al alloy film and the conductive oxide film. The Al alloy film contains 0.1 to 6 at % of at least one element selected from the group consisting of Ni, Ag, Zn, Cu and Ge, and further contains 1) 0.1 to 2 at % of at least one element selected from the group consisting of Mg, Cr, Mn, Ru, Rh, Pd, Ir, Pt, La, Ce, Pr, Gd, Tb, Sm, Eu, Ho, Er, Tm, Yb, Lu and Dy or 2) 0.1 to 1 at % of at least one element selected from the group consisting of Ti, V, Zr, Nb, Mo, Hf, Ta and W, as the alloy components.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: January 8, 2013
    Assignee: Kobe Steel, Ltd.
    Inventors: Hiroshi Gotoh, Toshihiro Kugimiya, Katsufumi Tomihisa
  • Patent number: 8338954
    Abstract: A semiconductor apparatus includes an aluminum electrode film formed on a semiconductor chip; and a nickel plated layer formed on the aluminum electrode film, wherein a concentration of sodium and potassium present in the nickel plated layer and at an interface between the nickel plated layer and the aluminum electrode film is 3.20×1014 atoms/cm2 or less.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: December 25, 2012
    Assignees: Fuji Electric Co., Ltd., C. Uyemura & Co., Ltd.
    Inventors: Hitoshi Fujiwara, Takayasu Horasawa, Kenichi Kazama
  • Publication number: 20120319283
    Abstract: A semiconductor device includes a semiconductor element including an anode electrode and a cathode electrode, an encapsulating material which covers the semiconductor element, a first external electrode which is electrically connected to the cathode electrode and is at least partially exposed outside of the encapsulating material, a second external electrode which is electrically connected to the anode electrode and is at least partially exposed outside of the encapsulating material, and a sacrificial metallic body which is arranged outside of the encapsulating material so as to be in direct contact with the first external electrode or to be electrically connected to the first external electrode through saltwater, and contains metal having larger ionization tendency than any metal contained in the first external electrode.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 20, 2012
    Applicant: Sanken Electric Co., Ltd.
    Inventor: Toru KANNO
  • Patent number: 8324731
    Abstract: An integrated circuit device having at least a bond pad for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: December 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Shwang-Ming Jeng, Yung-Cheng Lu, Huilin Chang, Ting-Yu Shen, Yichi Liao
  • Publication number: 20120248615
    Abstract: A manufacturing process of a MEMS device divides a substrate for fabricating a MEMS component into two electrically isolated regions, so that the MEMS component and the circuit disposed on its surface could connect electrically with another substrate below respectively through the corresponding conducing regions, whereby the configuration of the electrical conducting paths and the manufacturing process are simplified. A MEMS device manufactured by using the aforementioned process is also disclosed herein.
    Type: Application
    Filed: February 21, 2012
    Publication date: October 4, 2012
    Applicant: MIRADIA, INC.
    Inventors: YU-HAO CHIEN, HUA-SHU WU, SHIH-YUNG CHUNG, LI-TIEN TSENG, YU-TE YEH
  • Publication number: 20120223432
    Abstract: An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad.
    Type: Application
    Filed: March 1, 2011
    Publication date: September 6, 2012
    Applicant: LSI Corporation
    Inventors: JOHN M. DELUCCA, FRANK A. BAIOCCHI, RONALD J. WEACHOCK, JOHN W. OSENBACH, BARRY J. DUTT
  • Publication number: 20120217641
    Abstract: A device includes a top metal layer; a UTM line over the top metal layer and having a first thickness; and a passivation layer over the UTM line and having a second thickness. A ratio of the second thickness to the first thickness is less than about 0.33.
    Type: Application
    Filed: February 25, 2011
    Publication date: August 30, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wen Chen, Chuang-Han Hsieh, Kun-Yu Lin, Kuan-Chi Tsai
  • Patent number: 8242602
    Abstract: A method includes providing a mixture of molten indium and molten aluminum, and agitating the mixture while reducing its temperature until the aluminum changes from liquid phase to solid phase, forming particles distributed within the molten indium. Agitation of the mixture sufficiently to maintain the aluminum substantially suspended in the molten aluminum continues while further reducing the temperature of the mixture until the indium changes from a liquid phase to a solid phase. A metallic composition is formed, including indium and particles of aluminum suspended within the indium, the aluminum particles being substantially free from oxidation. The metallic (solder) composition can be used to form an assembly, including an integrated circuit (IC) device, at least a first thermal component disposed adjacent to the IC device, and a solder TIM interposed between and thermally coupled with each of the IC device and the first thermal component.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: August 14, 2012
    Assignee: Intel Corporation
    Inventors: Tom Fitzgerald, Carl Deppisch, Fay Hua
  • Patent number: 8217397
    Abstract: The present invention provides a thin film transistor substrate and a display device in which a decrease in the dry etching rate of a source electrode and drain electrode is not caused; no etching residues are generated; and a barrier metal can be eliminated between a semiconductor layer and metal wires such as the source and drain electrodes. The present invention is a thin film transistor substrate having a semiconductor layer 1, a source electrode 2, a drain electrode 3, and a transparent conductive film 4, in which the source electrode 2 and drain electrode 3 are formed by patterning by means of dry etching and comprises an Al alloy thin film comprising 0.1 to 1.5 atom % of Si and/or Ge, 0.1 to 3.0 atom % of Ni and/or Co, and 0.1 to 0.5 atom % of La and/or Nd, and the thin film transistor is directly connected with the semiconductor layer 1.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: July 10, 2012
    Assignee: Kobe Steel, Ltd.
    Inventors: Mototaka Ochi, Nobuyuki Kawakami, Katsufumi Tomihisa, Hiroshi Goto