Abstract: This invention relates to a method of forming a bottomless liner structure. The method involves the steps of first obtaining a material having a via. Next, a first layer is deposited on the material, the first layer covering the sidewalls and bottom of the via. Finally, a second layer is sputter deposited on the first material, the material Rf biased during at least a portion of the time that the second layer is sputter deposited, such that the first layer deposited on the bottom of the via is substantially removed and substantially all of the first layer deposited on the sidewalls of the via is unaffected.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device comprises: a semiconductor substrate; an uppermost metal interconnect formed on the semiconductor substrate; an oxide layer formed on the substrate and the uppermost metal interconnect; an aluminum layer formed on the oxide layer; and a stress-relief layer formed on the aluminum layer to thereby prevent cracking of the passivation layer during a subsequent packaging process, to increase reliability of the passivation layer, and to prevent degradation of properties of the semiconductor device.

Abstract: Isolated metal structures (110), (140) are formed adjacent to terminated metal lines (100), (130) that are connect by a via (120). The isolated structures (110), (140) act to suppress the stress created in the terminated metal lines (100), (130) during thermal cycling.

Abstract: A sputtering target consists essentially of 0.1 to 50% by weight of at least one kind of element that forms an intermetallic compound with Al, and the balance of Al. The element that forms an intermetallic compound with Al is uniformly dispersed in the target texture, and in a mapping of EPMA analysis, a portion of which count number of detection sensitivity of the element is 22 or more is less than 60% by area ratio in a measurement area of 20×20 &mgr;m. According to such a sputtering target, even when a sputtering method such as long throw sputtering or reflow sputtering is applied, giant dusts or large concavities can be suppressed in occurrence.

Abstract: A typical air bridge is an aluminum conductor suspended across an air-filled cavity to connect two components of an integrated circuit, two transistors for example. The air-filled cavity has a low dielectric constant which reduces cross-talk between neighboring conductors and improves speed and efficiency of the integrated circuit. However, current air bridges must be kept short because typical aluminum conductors sag too much. Accordingly, one embodiment of the invention forms air-bridge conductors from an aluminum-beryllium alloy, which enhances stiffness and ultimately provides a 40-percent improvement in air-bridge lengths.

Abstract: Titanium aluminum nitrogen (“Ti—Al—N”) is deposited onto a semiconductor substrate area to serve as an antireflective coating. For wiring line fabrication processes, the Ti—Al—N layer serves as a cap layer which prevents unwanted reflection of photolithography light (i.e., photons) during fabrication. For field emission display devices (FEDs), the Ti—Al—N layer prevents light originating at the display screen anode from penetrating transistor junctions that would hinder device operation. For the wiring line embodiment an aluminum conductive layer and a titanium-aluminum underlayer are formed beneath the antireflective cap layer. The Ti—Al underlayer reduces the shrinkage which occurs in the aluminum conductive layer during heat treatment.

Abstract: In order to solve the aforementioned problems, the present invention provides a semiconductor device having a multilayer interconnection structure, wherein an upper interconnection comprises a first metal layer composed of an aluminum alloy, which is formed over a lower interconnection, and a second metal layer formed over the first metal layer and composed of an aluminum alloy formed as a film at a temperature higher than that for the first metal layer. Another invention provides a semiconductor device having a multilayer interconnection structure, wherein a metal region composed of a metal different from an aluminum alloy is formed in a portion spaced by a predetermined distance in an extending direction of an upper interconnection from an end of a via hole defined in the upper interconnection composed of the aluminum alloy, which is electrically connected to a lower interconnection through the via hole.

Abstract: A thin film transistor and a method of manufacturing the same includes forming a copper alloy line on substrate, an oxidation film formed on the upper surface of the copper alloy line. The copper alloy line includes a concentration y of magnesium, and the copper alloy line has a thickness t. the concentration y of magnesium in copper alloy line is related to the thickness is as follows: y ≤ 94 t .

Abstract: A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate an Al alloy layer containing therein copper (Cu), and forming on the Al alloy layer a titanium nitride (TiN) film with enhanced chemical reactivity by using sputtering techniques while applying thereto a DC power of 5.5 W/cm2 or less. Fabrication of such reactivity-rich TiN film on the Al alloy layer results in a reaction layer of Al and Ti being subdivided into several spaced-apart segments. In this case, the reaction layer hardly serves as any diffusion path; thus, it becomes possible to prevent Cu as contained in the Al alloy layer from attempting to outdiffuse with the reaction layer being as its diffusion path.

Abstract: An integrated circuit metallization structure using a titanium/aluminum alloy, and a method to generate such a structure, provide reduced leakage current by allowing mobile impurities such as water, oxygen, and hydrogen to passivate structural defects in the silicon layer of the IC. The titanium layer of the structure is at least partially alloyed with the aluminum layer, thereby restricting the ability of the titanium to getter the mobile impurities within the various layers of the IC. Despite the alloying of the titanium and aluminum, the metallization structure exhibits the superior contact resistance and electromigration properties associated with titanium.

Abstract: A bridge structure, such as an air bridge, includes a bridge element formed of an alloy including aluminum, copper, and lithium. The alloy may also further include silicon and the amount of lithium of the alloy is generally greater than about 1.0% by weight up to the maximum solubility limit of lithium in aluminum. Methods for forming bridge structures utilizing such an alloy are also described.

Abstract: A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300° C. to 550° C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100° C.

Abstract: A TRIAC which is one species of chip-type semiconductors includes an element body made of silicon, electrodes provided on one face of the element body, a molybdenum plate provided on one of the electrodes by an alloy plate made of aluminum and silicon, a molybdenum plate provided on the other face of the element body by a similar alloy plate, and nickel layers provided on connection faces of the molybdenum plates to outer electrode plates, so that the electrode and molybdenum plate are firmly connected without conventional high-temperature solder which includes a great amount of lead, and that the alloy plate never melt even when newly developed low-temperature institute is employed, and that the operation of the molybdenum plates is sufficiently realized.

Abstract: A semiconductor device includes a first metal interconnection layer on a semiconductor substrate, an intermetal dielectric layer on the first metal interconnection layer and a second metal interconnection layer formed on the intermetal dielectric layer. A contact stud electrically connects the first and second metal interconnection layers through the intermetal dielectric layer, and includes a titanium/aluminum (TiAlx) core extending from the first metal interconnection layer toward the second metal interconnection layer. In method embodiments, a portion of an insulating layer of a semiconductor substrate is removed to form a hole that exposes an underlying conductive layer. A glue layer, e.g., a titanium (Ti) layer, is formed on bottom and sidewalls of the hole. A Ti seed layer is formed on the glue layer in the hole. An aluminum-containing layer is formed on the Ti seed layer. The substrate is thermally treated to form a contact stud including a TiAlx core.

Abstract: Methods of forming a metal interconnects include forming an electrically insulating layer having a contact hole therein, on a substrate. A step is also performed to form an electrically conductive seed layer. The seed layer extends on a sidewall of the contact hole and on a portion of an upper surface of the electrically insulating layer extending adjacent the contact hole. The seed layer is sufficiently thick along an upper portion of the sidewall and sufficiently thin along a lower portion of the sidewall that an upper portion of the contact hole is partially constricted by the seed layer and a constricted contact hole is thereby defined. An anti-nucleation layer is deposited on a portion of the seed layer that extends outside the constricted contact hole. The constricted contact hole is used as a mask to inhibit deposition of the anti-nucleation layer adjacent a bottom of the constricted contact hole.

Abstract: A corrosion-resistant conductive layer (TiW layer) formed of a corrosion-resistant material is formed to extend from a bonding pad portion to an interconnection portion of a light receiving element. A semiconductor laser device according to the present invention includes the light receiving element.

Abstract: A fine particle of metal is disposed on a semiconductor substrate. With the exception of a position of disposition of the fine particle of metal, a covering layer is formed on a surface of the semiconductor substrate. Thereafter, heat treatment is implemented at a temperature higher than that where constituent atoms of the semiconductor substrate and constituent atoms of the fine particle of metal dissolve at an interface thereof due to interdiffusion in a vacuum atmosphere. Thus, a fine projection structure that comprises a semiconductor substrate and a fine projection consisting of a solid solution of the semiconductor substrate and the metal is obtained. The fine projection is formed with part thereof precipitating in the semiconductor substrate. The fine projection structure as this largely contributes in realizing high integration semiconductor devices and quantum size devices.

Abstract: In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type A—X—Y, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.

Abstract: In a method for forming a connection structure in an integrated circuit, a first conducting material is deposited over a substrate and patterned to form a conducting stud in electrical contact with a conducting element of the substrate. A dielectric is formed over the substrate and the conducting stud. A trench is formed in the dielectric to expose a top portion of the conducting stud, and a second conducting material is inlaid in the trench to form wiring in electrical contact with the conducting stud. The electrically conducting element of the substrate may be an element of a semiconductor device or a wiring, contact or via. The first conducting material may be aluminum, and the second conducting material may be copper. The dielectric may be formed as a single layer and may be an organic low-k dielectric. Related connection structures are also disclosed.

Abstract: There is provided an electronic device comprising at least one electronic part and a substrate on which said electronic part is mounted, said electronic part and said substrate being bonded by a joint comprising a phase of Al particles and another phase of a Al—Mg—Ge—Zn alloy, said Al particles being connected to each other by said Al—Mg—Ge—Zn alloy phase.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. A seedless barrier layer lines the opening, and a conductor core fills the opening over the seedless barrier layer. The barrier layer is deposited in the opening and contains atomic layers of barrier material which bonds to the dielectric layer, an intermediate material which bonds to the barrier material layer and to the conductor core, and a conductor core material which bonds to the intermediate material. The conductor core bonds to the conductor core material.

Abstract: A system and method of selectively etching copper surfaces free of copper oxides in preparation for the deposition of an interconnecting metallic material is provided The method removes metal oxides with &bgr;-diketones, such as Hhfac. The Hhfac is delivered into the system in vapor form, and reacts almost exclusively to copper oxides. The by-products of the cleaning process are likewise volatile for removal from the system with a vacuum pressure. Since the process is easily adaptable to most IC process systems, it can be conducted in an oxygen-free environment, without the removal of the IC from the process chamber. The in-situ cleaning process permits a minimum amount of copper oxide to reform before the deposition of the overlying interconnection metal. In this manner, a highly conductive electrical interconnection between the copper surface and the interconnecting metal material is formed.

Abstract: A semiconductor device having a contact layer and a diffusion barrier layer is fabricated by preparing a semiconductor substrate, forming a layer of titanium/aluminum alloy on the surface of the substrate, and then heating the resultant structure in a nitrogen ambient to form a contact layer of titanium silicide interposed between the substrate and a diffusion barrier layer consisting of titanium/aluminum/nitride.

Abstract: There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.

Abstract: A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms first, which subsequently volumetrically contracts, thereby forming a titanium aluminide compound, with the contraction being absorbed by the aluminum. Because the alloy is reacted to form the metal compound prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced.

Abstract: Disclosed is a thin film aluminum alloy which is limited in the generation of hillocks while maintaining a low specific resistance and hardness irrespective of annealing temperature. In order to obtain the thin film aluminum alloy having a Vickers hardness of 30 Hv or less and a film stress (absolute value indication) of 30 kg/mm2 or less when performing annealing treatment at a temperature ranging from 25° C. to 500° C., wherein said hardness and said film stress are distributed in a predetermined hardness range and in a predetermined film stress range respectively within the temperature range of the above-mentioned annealing treatment and are respectively almost constant against annealing temperature, the thin film aluminum alloy being formed as a film on a substrate by a sputtering method using a sputtering target having a composition comprising 0.5 to 15 atom % of one or more types selected from Ag, Cu, Mg and Zn and 0.

Abstract: In one aspect the invention includes a method of protecting aluminum within an aluminum-comprising layer from electrochemical degradation during semiconductor processing comprising, providing a material within the layer having a lower reduction potential than aluminum. In another aspect, the invention includes a semiconductor processing method of forming and processing an aluminum-comprising mass, comprising: a) forming the aluminum-comprising layer mass to comprise a material having a lower reduction potential than aluminum; and b) exposing the aluminum-comprising mass to an electrolytic substance, the material protecting aluminum within the aluminum-comprising layer from electrochemical degradation during the exposing. In yet another aspect, the invention includes an aluminum-comprising layer over or within a semiconductor wafer substrate and comprising a material having a lower reduction potential than aluminum.

Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bump formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film formed in at least a peripheral portion of the bump to cover an interface of the bump and the intermediate layer which is exposed to a side surface of the bump.

Abstract: A typical air bridge is an aluminum conductor suspended across an air-filled cavity to connect two components of an integrated circuit, two transistors for example. The air-filled cavity has a low dielectric constant which reduces cross-talk between neighboring conductors and improves speed and efficiency of the integrated circuit. However, current air bridges must be kept short because typical aluminum conductors sag too much. Accordingly, one embodiment of the invention forms air-bridge conductors from an aluminum-beryllium alloy, which enhances stiffness and ultimately provides a 40-percent improvement in air-bridge lengths.

Abstract: The electronic device (1) has a layer (11) of a material comprising a first and a second element. This material has an amorphous and a crystalline state. A transition from the amorphous to the crystalline state can be effected by heating of the material to above a crystallization temperature, for example with a laser. As a result, the layer (11) has a first electrically conducting areas (21), comprising the material in the crystalline state, which are insulated from each other by the first electrically insulating area (23), comprising the material in the amorphous state. The layer (11) may be present as an interconnect layer, but also as a covering layer. Preferably, the material is aluminum-germanium. In the method of patterning a layer (11), electrically conductive areas of the layer can be strengthened by electroplating.

Abstract: An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.

Abstract: An aluminum-containing film having an oxygen content within the film. The aluminum-containing film is formed by introducing hydrogen gas and oxygen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.

Abstract: A semiconductor process and structure is provided for use in single or dual damascene metallization processes. A thin metal layer which serves as an etch stop and masking layer is deposited upon a first dielectric layer. Then, a second dielectric layer is deposited upon the thin metallization masking layer. The thin metallization masking layer provides an etch stop to form the bottom of the in-laid conductor grooves. In a dual damascene process, the thin metallization masking layer leaves open the via regions. Thus, the conductor grooves above the metallization masking layer and the via regions may be etched in the first and second dielectric in one step. In a single damascene process, the thin metallization etch masking layer may cover the via regions. The etch stop and masking layer can be formed from any conductive or non-conductive materials whose chemical, mechanical, thermal and electrical properties are compatible with the process and circuit performance.

Abstract: A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation. The enhanced vias are useful in a wide variety of semiconductor devices, including SRAMS and DRAMs.

Abstract: A method for forming an aluminum contact through an insulating layer includes the formation of an opening. A barrier layer is formed, if necessary, over the insulating layer and in the opening. A thin refractory metal layer is then formed over the barrier layer, and aluminum deposited over the refractory metal layer. Proper selection of the refractory metal layer and aluminum deposition conditions allows the aluminum to flow into the contact and completely fill it. Preferably, the aluminum is deposited over the refractory metal layer without breaking vacuum.

Abstract: In a method for manufacturing a semiconductor device, probe pads are formed simultaneously with formation of an intermediate conductive layer, and a test operation is performed upon the semiconductor device by placing probes on the probe pads. Then, post-stage processes are performed upon the semiconductor device in accordance with characteristics of the semiconductor device obtained by the test operation.

Abstract: In a semiconductor device, an active region is formed on a semiconductor substrate. An electrode layer is directly formed on the active region and serves as a bonding pad. The electrode layer is mainly formed by an Al alloy layer containing Cu.

Abstract: The present invention is concerned with an interconnect structure for providing electrical communication between an interconnect and a contact in a semiconductor device which includes a contact formed of aluminum or aluminum-copper, an aluminum-copper alloy film which is capable of substantially preventing the contact from being etched by an etchant and which covers substantially the contact, and an interconnect line formed of aluminum or aluminum-copper which at least partially covers the aluminum-copper film sufficient to provide electrical communication between the interconnect line and the contact. The present invention also provides a method for fabricating such interconnect structure.

Abstract: Anodic oxidation is conducted without forming a voltage supplying line for anodic oxidation. A second wiring layer comprising aluminum is formed as separated for each wiring, and electrically forms a short circuit by a metallic film comprising tantalum. The second wiring layer is subjected to anodic oxidation by applying a voltage to the first metallic film, and an anodic oxide film (alumina film) is formed on the surface thereof. A first wiring layer is formed by etching an anodic oxide with the anodic oxide as a mask, to complete wiring comprising wiring layers and laminated to each other.

Abstract: A microstructure comprises a conductive layer of aluminum, copper or alloys thereof on a substrate wherein the layer comprises metal grains at least about 0.1 microns and barrier material deposited in the grainboundaries of the surface of the metal is provided along with a method for its fabrication.

Abstract: A semiconductor barrier layer and manufacturing method therefor for copper interconnects which is a tantalum-titanium, tantalum-titanium nitride, tantalum-titanium sandwich. The tantalum in the tantalum-titanium alloy bonds strongly with the semiconductor dielectric, the tantalum-titanium nitride acts as the barrier to prevent diffusion of copper, and the titanium bonds strongly with the copper.

Abstract: An interconnect structure having refractory sidewalls 240 for enhanced yield, performance and reliability. The primary purpose of the refractory metal 240 is to getter sidewall impurities, residual polymers, and corrosive species by-products from the plasma etch and cleanup processes used to pattern interconnects. In a preferred embodiment, the refractory metal 240 reacts with the conducting layer 210 to form an intermetallic 245 which further enhances the endurance of the metallization against stress-induced rupturing and via-induced electromigration. The disclosed structures and methods are particularly advantageous in “zero-overlap” designs, and aggressive pitch patterns where linewidth and corrosion control are critical, but are also advantageous in “Damascene” pattern definition applications.

Abstract: The present invention provides a bonding structure between a bonding pad and a bonding portion of a bonding wire made of an Au-base material, wherein said bonding pad further comprises: a base layer; at least a barrier layer overlying said base layer; and a bonding layer overlying said at least barrier layer, said bonding layer including an Al-base material, and wherein said bonding portion of said bonding wire is buried in said bonding layer, and an Au—Al alloy layer extends on an interface between said bonding portion and said bonding layer, and a bottom of said Au—Al alloy layer is in contact with or adjacent to an upper surface of said barrier layer.

Abstract: The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interlayer insulator film 11, a titanium layer 12, a titanium nitride layer 13 that serves as the barrier layer, an aluminum alloy wiring layer 15 and a protective film 18 are formed on top of the silicon substrate 10 to compose the electrode structure. In this case, a distortion relaxation layer 14, with a film thickness of approximately over 10 nm and which is an intermetallic compound that includes aluminum and titanium in its composition, is formed in between the titanium nitride layer 13 and the aluminum alloy wiring layer 15. Because of this distortion relaxation layer, for every wiring width of 1 &mgr;m, the number of Al voids with widths of over 0.3 &mgr;m is practically reduced to 0.

Abstract: Described in the present invention is a semiconductor device in which a plurality of interconnect lines are disposed, through an insulating layer, on the same layer above a semiconductor substrate having a semiconductor element; a first interlevel insulator is formed selectively in a narrowly-spaced region between adjacent interconnect lines; a second interlevel insulator is formed in a widely-spaced region between said adjacent interconnect lines, and the first interlevel insulator has a smaller dielectric constant than the second interlevel insulator. According to such a constitution, strength and reliability can be heightened and performance can be improved easily even in a miniaturized interconnect structure.

Abstract: A new liner structure and method to incorporate this liner into process flows in order to lower the processing temperature of aluminum extrusion or reflow cavity filling. The structures produced by this innovative method are particularly useful for advanced sub-quarter micron multi-level interconnect applications.

Abstract: A semiconductor device is constituted by embedding an Al wiring layer in a second object formed on an interlayer-insulating film on one principal plane of a semiconductor substrate and connecting with an Al wiring formed on the substrate and at least, an Nb liner film and NbAl alloy film are formed between the second object and the Al wiring layer.

Abstract: A process for producing a semiconductor device comprises a step of polishing of a region of an electroconductive material serving as an electrode or a wiring line in an insulating layer formed on a semiconductor region, the region of the electroconductive material being electrically connected to the semiconductor region, wherein a region of another material is formed within the region of the electroconductive material to be polished. Also a semiconductor device having the region is provided. A process for producing an active matrix substrate comprises a step of polishing of picture element electrodes made of a metal provided on crossing portions of plural signal lines and plural scanning lines and a means for applying voltage to the picture elements, wherein a region of another material is formed within the region of the picture element electrode to be polished. An active matrix substrate has such picture element electrodes as mentioned above.

Abstract: A method and apparatus are provided for reducing and eliminating the First Wafer Effect. Specifically, in a method, or system that employs a separate hot chamber for hot deposition of material that may result in the First Wafer Effect (FWE material), a cold layer of the FWE material is deposited within the hot deposition chamber prior to deposition of the hot FWE material layer.

Abstract: A modular semiconductor power device has a conductive member consisting of an alumina plate to which copper layers are soldered on opposite sides. A chip is soldered to one of these layers and the other of these layers is soldered in turn to a metal heat sink. The chip is connected to respective copper strips which, in turn, are soldered to thermal strips originally forming part of a frame so that, after the device is encapsulated in a synthetic resin, the connecting members of the frame can be cut away to leave free ends of the latter strips exposed.