Abstract: A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring.

Abstract: An improved reliability of a junction region between a bonding wire and an electrode pad in an operation at higher temperature is presented. A semiconductor device includes a semiconductor chip provided on a lead frame, which are encapsulated with an encapsulating resin. Lead frames are provided in both sides of the lead frame. A portion of the lead frame is encapsulated with the encapsulating resin to function as an inner lead. The encapsulating resin is composed of a resin composition that contains substantially no halogen. Further, an exposed portion of the Al pad provided in the semiconductor chip is electrically connected to the inner lead via the AuPd wire.

Abstract: The present invention provides Al-based wiring material that allows, in a display device including thin film transistors and transparent electrode layers, direct bonding to the transparent electrode layer made of ITO, IZO or the like as well as direct bonding to the semiconductor layer, such as n+-Si. The Al—Ni—B alloy wiring material according to the present invention is configured such that the nickel content X at %, the nickel atomic percent, and the boron content Y at %, the boron atomic percent, satisfy the following equations: 0.5?X?10.0, 0.05?Y?11.0, Y+0.25X?1.0 and Y+1.15X?11.5, and the remainder is aluminum.

Abstract: A method of making chip assemblies includes providing an in-process assembly including a semiconductor wafer, a wafer compliant structure overlying a front surface of the wafer and cavities, and terminals carried on the compliant structure adjacent the cavities and electrically connected to the wafer, the cavities being substantially sealed. The method includes subdividing the in-process assembly to form individual chip assemblies, each including one or more chip regions of the wafer, a portion of the compliant structure and the terminals carried on the portion, and opening vents communicating with said cavities after said providing step.

Abstract: An electronic device that has an integrated circuit die with a plurality of contacts pads, a printed circuit board with a plurality of conductors corresponding to each of the contact pads respectively, wire bonds electrically connecting each of the contact pads to the corresponding conductors and, an adhesive surface positioned between the contacts pads and the corresponding conductors. The wire bonds are secured to the adhesive surface to hold them in a low profile configuration.

Abstract: Semiconductor devices to reduce stress on a metal interconnect are disclosed. A disclosed semiconductor device comprises: a semiconductor substrate; an uppermost metal interconnect formed on the semiconductor substrate; an oxide layer formed on the substrate and the uppermost metal interconnect; an aluminum layer formed on the oxide layer; and a stress-relief layer formed on the aluminum layer to thereby prevent cracking of the passivation layer during a subsequent packaging process, to increase reliability of the passivation layer, and to prevent degradation of properties of the semiconductor device.

Abstract: The present invention is directed to a thick film conductive composition comprising: (a) electrically conductive silver powder; (b) Mn-containing additive; (c) glass frit wherein said glass frit has a softening point in the range of 300 to 600° C.; dispersed in (d) organic medium. The present invention is further directed to a semiconductor device and a method of manufacturing a semiconductor device from a structural element composed of a semiconductor having a p-n junction and an insulating film formed on a main surface of the semiconductor comprising the steps of (a) applying onto said insulating film the thick film composition as describe above; and (b) firing said semiconductor, insulating film and thick film composition to form an electrode.

Abstract: Intermetallic conductive materials are used to form interconnects in an integrated circuit. In some cases, the intermetallic conductive material may be an intermetallic alloy of aluminum.

Abstract: The present invention provides a sputtering target comprising aluminum and one or more alloying elements including Ni, Co, Ti, V, Cr, Mn, Mo, Nb, Ta, W, and rare earth metals (REM). The addition of very small amounts of alloying element to pure aluminum and aluminum alloy target improves the uniformity of the deposited wiring films through affecting the target's recrystallization process. The range of alloying element content is 0.01 to 100 ppm and preferably in the range of 0.1 to 50 ppm and more preferably from 0.1 to 10 ppm weight which is sufficient to prevent dynamic recrystallization of pure aluminum and aluminum alloys, such as 30 ppm Si alloy. The addition of small amount of alloying elements increases the thermal stability and electromigration resistance of pure aluminum and aluminum alloys thin films while sustaining their low electrical resistivity and good etchability. This invention also provides a method of manufacturing microalloyed aluminum and aluminum alloy sputtering target.

Abstract: A semiconductor device includes: a plurality of power MOS cells on a semiconductor substrate; a plurality of lead wires connecting to a source and a drain of each power MOS cell through a contact hole; a plurality of collecting electrodes connecting in parallel with the lead wires through a via hole; an interlayer protection film on the collecting electrode; a thick film electrode connecting to the collecting electrode through the opening; and a terminal protection film having an opening for bonding connection.

Abstract: A high melting point solder alloy superior in oxidation resistance, in particular a solder alloy provided with both a high oxidation resistance and high melting point suitable for filling fine through holes of tens of microns in diameter and high aspect ratios and forming through hole filling materials, comprising a zinc-aluminum solder alloy containing 0.001 wt % to 1 wt % of aluminum and the balance of zinc and unavoidable impurities.

Abstract: A semiconductor device can comprise a contact material in substantially continuous contact with a contact region. In an embodiment the contact region may comprise an alloy comprising a wide band-gap material and a low melting point contact material. A wide band-gap material may comprise silicon carbide and a low melting point contact material may comprise aluminum. In another embodiment a substantially uniform ohmic contact may be formed between a contact material and a semiconductor material by annealing the contact at a temperature less than the melting point of the contact material. In an embodiment, the contact may be annealed for more than five hours.

Abstract: An exemplary damascene interconnect structure includes a substrate (20), a first dielectric layer (21) on the substrate, a plurality of trenches (27) formed in the first dielectric layer, and a plurality of metal lines (24) filled in the trenches. The first dielectric layer includes multi sub-dielectric layers (211, 212, 213). Wherein a plurality of air gaps (28) are maintained between the metal lines and at least one of the sub-dielectric layers. A method for fabricating the damascene interconnect structure is also provided.

Abstract: A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.

Abstract: A method for treating a dielectric material using hydrocarbon plasma is described, which allows for thinner films of barrier material to be used to form a robust barrier.

Abstract: A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper electrodes is secured, and also the time-lapse degradation under high temperature which causes diffusion of copper and corrosion of copper is suppressed. Still furthermore, direct bonding connection can be established to current collecting electrodes in the power device portion, and also established to a bonding pad formed on the control circuit portion in the control circuit portion. A pad area at the device peripheral portion which has been hitherto needed is reduced, so that the area of the device is saved, and the manufacturing cost is reduced.

Abstract: A hillock-free conductive layer comprising at least two aluminum (Al) layers formed on a substrate, wherein said at least two Al layers comprise a barrier Al layer formed on the substrate, and a pure Al layer formed on the barrier Al layer. The barrier Al layer could be an aluminum nitride (AlNx) layer, an aluminum oxide (AlOx) layer, an aluminum oxide-nitride (AlOxNy) layer, or an Al—Nd alloy layer. Also, the pure Al layer is physically thicker than the barrier Al layer, for effectively inhibiting the occurrence of hillocks and the like.

Abstract: An improved method of forming a semiconductor device structure is disclosed, comprising insertion of a semiconductor wafer into a high-pressure heated chamber and the deposition of a low melting-point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The wafer is heated up to the melting point of the aluminum material and the chamber is pressurized to force the aluminum material into the contact holes or vias and eliminate voids present therein. A second layer of material, comprising a different metal or alloy, which is used as a dopant source, is deposited over an outer surface of the deposited aluminum material layer and allowed to diffuse into the aluminum material layer in order to form a homogenous aluminum alloy within the contact hole or via. A semiconductor device structure made according to the method is also disclosed.

Abstract: In order to solve the aforementioned problems, the present-invention provides a semiconductor device having a multilayer interconnection structure, wherein an upper interconnection comprises a first metal layer composed of an aluminum alloy, which is formed over a lower interconnection, and a second metal layer formed over the first metal layer and composed of an aluminum alloy formed as a film at a temperature higher than that for the first metal layer. Another invention provides a semiconductor device having a multilayer interconnection structure, wherein a metal region composed of a metal different from an aluminum alloy is formed in a portion spaced by a predetermined distance in an extending direction of an upper interconnection from an end of a via hole defined in the upper interconnection composed of the aluminum alloy, which is electrically connected to a lower interconnection through the via hole.

Abstract: A mold type semiconductor device includes a semiconductor chip including a semiconductor part; a metallic layer; a solder layer; and a metallic member connecting to the semiconductor chip through the metallic layer and the solder layer. The solder layer is made of solder having yield stress smaller than that of the metallic layer. Even when the semiconductor chip is sealed with a resin mold, the metallic layer is prevented from cracking.

Abstract: Disclosed is an Al alloy film for wiring, which consists of, by atom, 0.2 to 1.5% Ge and 0.2 to 2.5% Ni and the balance being essentially Al, wherein a total amount of Ge and Ni is not more than 3.0%. The invention is also directed to a sputter target material having the same chemical composition as that of the Al alloy film.

Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.

Abstract: A problem in related art according to which an increase in leak current cannot be avoided in order to obtain a low forward voltage VF as forward voltage VF and reverse leak current IR characteristics of a Schottky barrier diode are in a trade-off relationship is hereby solved by forming a Schottky barrier diode using a metal layer comprising a Schottky metal layer of Ti including a small amount of Al. Consequently, a low reverse leak current IR can be obtained without causing a large increase in the forward voltage VF of pure Ti such that power consumption can be reduced by suppressing forward power loss and decreasing reverse power loss.

Abstract: A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.

Abstract: Supercritical fluid-assisted deposition of materials on substrates, such as semiconductor substrates for integrated circuit device manufacture. The deposition is effected using a supercritical fluid-based composition containing the precursor(s) of the material to be deposited on the substrate surface. Such approach permits use of precursors that otherwise would be wholly unsuitable for deposition applications, as lacking requisite volatility and transport characteristics for vapor phase deposition processes.

Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.

Abstract: A layered structure of wire(s) comprising a wiring layer made of a low resistance metal containing aluminum, copper or silver; and an alloy layer made of an intermediate phase containing the low resistance metal and a refractory metal. The refractory metal is molybdenum. There is also formed a layered structure of wire(s) made of an aluminum alloy containing a lanthanoid, wherein a number average crystal grain size is 16.9 nm or more. Crystal grain size may be larger than a mean free path of electrons to provide a layered structure of wire(s) with a reduced resistance.

Abstract: An interconnect structure of a semiconductor device includes a tungsten plug (14) deposited in a via or contact window (11). A barrier layer (15) separates the tungsten plug (14) from the surface of a dielectric material (16) within which the contact window or via (11) is formed. The barrier layer (15) is a composite of at least two films. The first film formed on the surface of the dielectric material (16) within the via (11) is a tungsten silicide film (12). The second film is a tungsten film (13) formed on the tungsten silicide film (12). A tungsten plug (14) is formed on the tungsten film (13) to complete interconnect structure. The barrier layer (15) is deposited using a sputtering technique performed in a deposition chamber. The chamber includes tungsten silicide target (19) from which the tungsten silicide film (12) is deposited, and a tungsten coil (20) from which the tungsten film (20) is deposited.

Abstract: A semiconductor device of the present invention comprises a semiconductor chip, metal layers formed on a first main surface of the semiconductor chip, a first conductive layer layered on a second main surface of the semiconductor chip, consisting of a plurality of conductive films, a second conductive layer layered on the metal layer, having a layered structure consisting of a plurality of conductive films formed in the same order as in the first conductive layer as viewed from the semiconductor chip and a third conductive layer layered on the metal layer, having a layered structure consisting of a plurality of conductive films formed in the same order as in the first conductive layer as viewed from the semiconductor chip. The plurality of conductive films comprise a nickel film and a low contact resistance conductive film having contact resistance with the semiconductor chip which is lower than that of the nickel film.

Abstract: An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×1018 atoms·cm?3 or less, carbon atoms at a concentration of 5×1018 atoms·cm?3 or less, and nitrogen atoms at a concentration of 7×1017 atoms·cm?3 or less; furthermore, a silicon nitride film is formed on the aluminum gate, and an anodic oxide film is formed on the side planes thereof.

Abstract: A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.

Abstract: A sputtering target consists essentially of 0.1 to 50% by weight of at least one kind of element that forms an intermetallic compound with Al, and the balance of Al. The element that forms an intermetallic compound with Al is uniformly dispersed in the target texture, and in a mapping of EPMA analysis, a portion of which count number of detection sensitivity of the element is 22 or more is less than 60% by area ratio in a measurement area of 20×20 ?m. According to such a sputtering target, even when a sputtering method such as long throw sputtering or reflow sputtering is applied, giant dusts or large concavities can be suppressed in occurrence.

Abstract: A semiconductor device comprising a semiconductor substrate having first and second surfaces opposing each other, the substrate including a plurality of cells sharing a common drain region, each of the cells having source and gate regions, a surface source electrode connected to the source region of each of the cells and provided on the first surface, a strap member coupled with the surface source electrode by ultrasonic waves, a gate polysilicon wiring layer connecting the gate region of each of the cells and having a silicide layer in at least a portion of a surface thereof, a surface gate electrode connected to the gate polysilicon wiring layer and provided on the first surface, and a drain electrode provided on the second surface and shared by the cells.

Abstract: Alignment marks of a semiconductor device, formed prior to a step of applying heat treatment in an oxygen atmosphere, include an insulating film, a groove formed in the insulating film during a step of defining a contactor hole in a device part, a metal film formed at least on sidewalls of the groove during a step of burying the contactor hole in the device part, and a cover film formed on the insulating film to cover the metal film formed in the groove for prevention of oxidation of the metal film during heat treatment applied in an oxygen atmosphere.

Abstract: First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and a thermal treatment process using annealing step is executed. At this time, all or part of aluminum oxide (AlOx) layer having a high resistivity, which is formed on the gate wire and/or the data wire during manufacturing process, may be removed. Then, the passivation layer is patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively.

Abstract: The present invention describes a method including providing a component, the component having a bond pad; forming a passivation layer over the component; forming a via in the passivation layer to uncover the bond pad; and forming an under bump metallurgy (UBM) over the passivation layer, in the via, and over the bond pad, in which the UBM includes an alloy of Aluminum and Magnesium. The present invention also describes an under bump metallurgy (UBM) that includes a lower layer, the lower layer including an alloy of Aluminum and Magnesium; and an upper layer located over the lower layer.

Abstract: A semiconductor device including a substrate (10). An interconnect pattern (12) is formed over the substrate (10), and the substrate (10) has a first portion (14) and a second portion (16) to be superposed on the first portion (14). The first portion (14) has edges (22), (24), (26) and (28) as positioning references. The second portion (16) has a shape to be superposed over the first portion (14) except the edges (22), (24), (26) and (28).

Abstract: A carrier has a metal area that is essentially composed of copper. A chip has a rear side metallization layer. A buffer layer, essentially composed of nickel and having a thickness of between 5 ?m and 10 ?m, is arranged on the metal area. The chip does not have a chip housing and is arranged on the metal area, which has been provided with the buffer layer, such that only one connecting medium is arranged between the rear side metallization layer of the chip and the buffer layer.

Abstract: A semiconductor apparatus includes an under layer, a first insulating layer and a first conductive portion. The under layer is formed above a substrate. The first insulating layer is formed on the under layer. The first conductive portion is formed in a first concave portion which passes through the first insulating layer to the under layer. The first conductive portion includes a first barrier metal layer and a first metal portion. The first barrier metal layer is formed on a side wall and a bottom surface of the first concave portion. The first metal portion is formed on the first barrier metal layer such that the rest of the first concave portion is filled with the first metal portion. The first metal portion includes a first alloy including copper and aluminium.

Abstract: In a semiconductor integrated circuit device, upon connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layers, the uppermost one is made of a wiring material such as aluminum or aluminum alloy, while the lower, one is made of Cu or Cu alloy. The lowest interconnection is made of a conductive material other than Cu or Cu alloy. For example, the conductive material which permits minute processing and has both low resistance and high EM resistance such as tungsten is employed.

Abstract: A memory device with multi-bit memory cells and method of making the same uses self-assembly to provide polymer memory cells on the contacts to a transistor array. Employing self-assembly produces polymer memory cells at the precise locations of the contacts of the transistor array. The polymer memory cells change resistance values in response to electric current above a specified threshold value. The memory cells retain the resistivity values over time.

Abstract: In order to form an aluminum system wiring that does not peel off on an insulating film containing fluorine and to improve the reliability thereof, a semiconductor device according to the present invention includes an insulating film (14) containing fluorine formed on a substrate (11), a titanium aluminum alloy film (17a) formed on the insulating film (14) containing fluorine, and a metallic film (17b) comprising aluminum or an aluminum alloy formed on the titanium aluminum alloy film (17a).

Abstract: A semiconductor device includes a semiconductor element having a plurality of element electrodes and a ball electrode electrically connected to at least one element electrode out of the plurality of element electrodes. The ball electrode is made of a Sn—Zn-based lead-free solder including 7 through 9.5 wt % of zinc and the remaining of tin.

Abstract: An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×1018 atoms·cm?3 or less, carbon atoms at a concentration of 5×1018 atoms·cm?3 or less, and nitrogen atoms at a concentration of 7×1017 atoms·cm?3 or less; furthermore, a silicon nitride film is formed on the aluminum gate, and an anodic oxide film is formed on the side planes thereof.

Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. Plugs that extend from one surface of the wafer into the wafer are used to provide vertical connections and to bond the wafers together. A stacked integrated circuit is constructed by bonding the front side of a new wafer to a wafer in the stack and then thinning the backside of the new wafer to a thickness that leaves a portion of the plugs extending above the surface of the backside of the thinned wafer. The elevated plug ends can then be used to bond another wafer by bonding to pads on the front side of that wafer. The mating bonding pads can include depressed regions that mate to the elevated plug ends.

Abstract: A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation. The enhanced vias are useful in a wide variety of semiconductor devices, including SRAMS and DRAMs.

Abstract: An object of the present invention is to provide a technique for forming an ohmic connection between a semiconductor and a metal efficiently in a short period of time. The present invention provides a method of forming at least one electrode on a surface of a semiconductor, wherein a metal or alloy for the electrode is rubbed against a predetermined region of the semiconductor surface so as to be adhered by frictional force and frictional heat to the predetermined region of the semiconductor as an electrode and part of the adhered metal or a metal of the alloy is diffused into an inside of the semiconductor by the frictional heat thereby to be formed into an ohmic electrode substantially simultaneously when the metal or alloy is adhered by the frictional force and frictional heat to the predetermined region of the semiconductor.

Abstract: A method for making a radio frequency (RF) component includes forming a dielectric layer on a semiconductor substrate and forming and patterning a conductive layer on the dielectric layer to define the RF component. The dielectric layer may include SiN, the conductive layer may include aluminum, and the semiconductor substrate may include silicon, for example. At least one opening may be formed through the RF component at least to the semiconductor substrate. Moreover, the at least one opening may either extend into the semiconductor substrate or substantially terminate at a surface of the semiconductor substrate. The RF component may then be released from the semiconductor substrate by exposing the semiconductor substrate to an etchant passing through the at least one opening to the semiconductor substrate. Releasing the RF component may include exposing the semiconductor substrate to a dry etchant, such as XeF2, for example.

Abstract: Disclosed is a thin film aluminum alloy which is limited in the generation of hillocks while maintaining a low specific resistance and hardness irrespective of annealing temperature. In order to obtain the thin film aluminum alloy having a Vickers hardness of 30 Hv or less and a film stress (absolute value indication) of 30 kg/mm2 or less when performing annealing treatment at a temperature ranging from 25° C. to 500° C., wherein said hardness and said film stress are distributed in a predetermined hardness range and in a predetermined film stress range respectively within the temperature range of the above-mentioned annealing treatment and are respectively almost constant against annealing temperature, the thin film aluminum alloy being formed as a film on a substrate by a sputtering method using a sputtering target having a composition comprising 0.5 to 15 atom % of one or more types selected from Ag, Cu, Mg and Zn and 0.

Abstract: An interconnection of an aluminum-copper-titanium alloy containing about 0.1 atomic percent titanium.