Abstract: A thin film transistor of this invention includes: a source and drain regions formed on an insulating base region; and a conductive layer connected to the source and drain regions. The conductive layer has a layered structure of an Al-containing metal film and an N-containing Mo film.

Abstract: A liquid crystal display device comprising a substrate; a first metal layer including an aluminum alloy having a first refractory metal with a first melting temperature over the substrate; and a second metal layer including a pure aluminum or an aluminum alloy having a second refractory metal with a second melting temperature lower than the first melting temperature over the first metal layer. The above liquid crystal display device of the present invention prevents the occurrence of hillocks on the aluminum gate metal. A method of manufacturing a liquid crystal display device is disclosed including the steps of forming a first metal layer of an aluminum alloy including a refractory metal having a first melting temperature on a substrate; and forming a second metal layer of a pure aluminum or an aluminum alloy including a refractory metal having a second melting temperature lower than the first melting temperature on the first metal layer.

Abstract: An aluminum interconnection of the invention contains scandium as an impurity, so that the hardness of the interconnection in improved. Moreover, after a thin Al-Sc alloy film is formed, an annealing is performed 80 as to make the crystal grain larger than the width of the interconnection. The resulting Al interconnection has a high resistance against a stressmigration or electromigration, when a current stress in applied at a practical temperature in an LSI. This greatly contributes to the fabrication of a semiconductor device having a fine structure.

Abstract: A semiconductor device has an electrode interposed between an interlayer insulation film and a wire which is bonded thereto. A main component of the electrode is aluminum and the electrode contains fine-grained silicon in a concentration of 0.1 to 0.6 weight %. As a result, even if large ultrasonic power, a large load or the like is applied to the electrode when the wire is wire-bonded, damage such as the formation of a crack hardly generates at the interlayer insulation film. Therefore, the occurrence of defects due to the wire-bonding can be reduced.

Abstract: A method for fabricating a semiconductor device includes: successively laminating a pair or more pairs of Ti and Al thin films on an n type GaAs substrate thereby to form Ti/Al laminated films; and performing thermal processing to the n type GaAs substrate and the Ti/Al laminated films at a temperature lower than the temperature at which Al of the Ti/Al laminated films and GaAs of the n type GaAs layer react with each other, to make the Ti/Al laminated films have ohmic junction with the n type GaAs layer thereby to form an ohmic electrode. Therefore, the Ti/Al laminated layer film comprising materials which are not likely to intrude into the n type GaAs layer is alloyed to Al.sub.3 Ti alloy by the annealing, and during the annealing, Ga atoms are out-migrated from the n type GaAs layer, and the Si atoms as dopants in the n type GaAs layer are present in the junction interface of the n type GaAs layer with the Ti/Al laminated layer film, thereby to form an ohmic contact.

Abstract: A capacitor having a pair of conductive electrodes separated by a dielectric layer and wherein at least one of the electrodes comprise Ti.sub.x Al.sub.1-x N, and wherein the variable "x" lies in a range of about 0.4 to about 0.8. The invention also contemplates a method for forming an electrically conductive diffusion barrier on a silicon substrate and which comprises providing a chemical vapor deposition reactor having a chamber; positioning the silicon substrate in the chemical vapor deposition reactor chamber; providing a source of gaseous titanium aluminum and nitrogen to the chemical vapor deposition reactor chamber; and providing temperature and pressure conditions in the chemical vapor deposition reactor chamber effective to deposit an electrically conductive diffusion barrier layer on the silicon substrate comprising Ti.sub.x Al.sub.1-x N, and wherein the variable "x" is in a range of about 0.4 to about 0.8.

Abstract: The invention relates to a semiconductor device of the type sealed in glass, comprising a silicon semiconductor body having a pn-junction between opposing faces which are connected to slugs of a transition metal by means of a bonding layer, the bonding layer comprising a quantity of aluminum in the range between 7 and 15 wt. % and a quantity of silver in the range between 85 and 93 wt. %.

Abstract: An improvement in a metal stack used for interconnecting structures in an integrated circuit. The improvement comprises the entrapping in a titanium layer of nitrogen at the interface where the titanium layer contacts a bulk conductor layer such as an aluminum-copper alloy layer. The entrapped nitrogen prevents the formation of any substantial amount of titanium aluminide thereby reducing current densities and also improving the electromigration properties of the stack. As currently preferred, the nitrogen is entrapped in approximately the first 30.ANG. of the titanium layer.

Abstract: A method and structure for reducing short circuits in semiconductor devices is disclosed. A three layer interlevel dielectric structure is formed over a semiconductor substrate, which typically comprises a first metallization level, M1. The three layer dielectric includes a first insulator layer, a middle spin-on glass (SOG) layer, and a top second insulator layer. The spin-on glass fills defects in the surface of the first insulator layer created during planarization using chemical-mechanical-polishing (CMP). Prior to deposition of the second insulator, a first via is etched through the SOG film and the first insulator layer to expose a portion of the semiconductor substrate, typically a conductive metal. A conductive metal is deposited into the first via and planarized to form a metal interconnection stud. Because the surface defects are filled and covered with the SOG film, none of the deposited metal enters the defects, and short circuits with the stud are greatly reduced.

Abstract: A semiconductor device includes at least one hole formed on a semiconductor substrate. A barrier metal is formed on at least one portion in contact with the semiconductor substrate in the hole. A metal interconnection is constituted by two layers including a first Al-containing metal film formed on the barrier metal, and a second Al-containing metal film formed on the first Al-containing metal film and having a melting point lower than the melting point of the first Al-containing metal film.

Abstract: This is a highly purified metal comprising one metal selected from the group consisted of titanium, zirconium and hafnium. The highly purified metal has an Al content of not more than 10 ppm. It also has an oxygen content of more than 250 ppm, each of Fe, Ni and Cr contents not more than 10 ppm and each of Na and K contents not more than 0.1 ppm. The highly purified metal is obtained by either purifying crude metal by the iodide process or surface treating crude metal to remove a contaminated layer existing on the surface thereof and then melting The surface treated material with electron bean in a high vacuum.

Abstract: The method of producing a semiconductor device includes the steps of forming a groove having a predetermined pattern shape on the surface of a substrate; forming a metal film on the substrate while reaction with the surface of the substrate is suppressed; and agglomerating the metal film by in-situ annealing, wherein agglomeration of the metal film is started before the metal film reacts with the surface of the substrate due to annealing, while formation of a native oxide on the metal film is suppressed, and whereby the metal film is filled into the groove by annealing at a predetermined temperature for a predetermined period of time. The structure of the semiconductor device includes an insulator in which there is formed a groove portion having a predetermined pattern shape and an electrode interconnection made of a single-crystal metal which is filled in the groove portion.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: A multilayer interconnect structure for a semiconductor integrated circuit comprising a base layer of titanium, a second layer of titanium nitride, a third layer of an aluminum alloy and a top layer of titanium nitride. All of the layers contained within the multilayer interconnect structure are deposited by in-situ deposition in an ultra-high vacuum deposition system. The different layers deposited in the deposition system are conducted consecutively without a disruption to the vacuum. Although each layer in the multilayer interconnect structure are deposited within the integrated ultra-high vacuum deposition system, with multiple deposition chambers, the deposition of the different layers is conducted at different temperatures. The time to the electromigration failure of the multilayer interconnect structure, caused by the electromigration of the aluminum alloy, is greatly increased by depositing the aluminum alloy layer at a temperature in excess of 300.degree. C. and preferably between 350.degree. C.

Abstract: A Si IC includes an Al-based layer which is deposited as a composite of sublayers of different composition Al-based materials. In one embodiment a first sublayer comprises an Al-Si-based alloy disposed so as to prevent substantial Si migration into the first sublayer, and a second sublayer, above the first, comprises an Al-based alloy with substantially no Si to alleviate precipitation-induced problems.

Abstract: A method for forming an alignment mark during semiconductor device manufacturing. A first area and a second area are provided on the semiconductor substrate wherein the second area is adjacent to the first area. An alignment mark is formed in the first area. A first layer is formed over the first area and the second area wherein the alignment mark is replicated in the first layer. The first layer is then removed from the second area and left over the first area. A globally planarized second layer, is formed over the first area and the second area. The second layer is then removed from the first area and is left over the second area.

Abstract: The use of a bi-layer thin film structure consisting of aluminum or aluminide on a refractory metal layer as a diffusion barrier to oxygen penetration at high temperatures for preventing the electrical and mechanical degradation of the refractory metal for use in applications such as a capacitor electrode for high dielectric constant materials.

Abstract: An aluminum-nickel-chromium (Al-Ni-Cr) layer used as an interconnect within a semiconductor device is disclosed. The Al-Ni-Cr layer has about 0.1-0.5 weight percent nickel and about 0.02-0.1 weight percent chromium. Usually, the nickel or chromium concentrations are no greater than 0.5 weight percent. The layer is resistant to electromigration and corrosion. The low nickel and chromium concentrations allow the layer to be deposited and patterned similar to most aluminum-based layers.

Abstract: A semiconductor device that includes a wiring line formed from an electrode wiring layer which uses, as an electrode material, an Al alloy containing Cu, wherein wiring line having a size smaller than a crystal grain diameter has a Cu concentration of 0.05 to 0.3 wt %, and a wiring line having a size larger than a crystal grain diameter has a Cu concentration of 0.5 to 10 wt %.

Abstract: A semiconductor circuit device wiring is provided in which the wiring connected to a semiconductor element is composed of a crystalline material. The crystal axis direction along which nearest neighboring atoms in a single crystal constituting the crystalline material are arranged and the electric current direction through the wiring are crossed with each other at an angle of 22.5.degree. or less.

Abstract: In an electronic device, an interconnect utilizes a flat substrate and a layer bonded to the substrate. The layer may have a through hole formed therein or be formed from parallel spaced layers. An aluminum or aluminum alloy film having single crystallinity is deposited within the through hole or void step created between parallel spaced layers.

Abstract: A semiconductor integrated circuit device includes a substrate formed with semiconductor elements and a metal wiring having a laminated structure and provided on the substrate. The metal wiring includes a first layer including aluminum as a main component, and a second layer formed on the first layer. The second layer includes titanium and nitrogen as main components. The second layer includes more titanium than nitrogen in number of atoms. A third layer may be formed between the first and second layers. The third layer includes a compound of aluminum and titanium as a main component. A fourth layer may further be formed between the second and third layers. The fourth layer includes titanium as a main component and is free of aluminum.

Abstract: A method for making a schottky diode structure (10) simultaneously with a polysilicon contact structure (31,33) to a transistor is provided. In a single process step, a polysilicon layer is patterned to expose a single crystal semiconductor region (22a) over one portion of a substrate, while leaving portions the polysilicon layer (31, 33, 29) intact over other portions of the substrate (22b). Multi-layer metal electrodes are deposited and patterned to form a rectifying schottky contact to the exposed single crystal region (22a), and to form an ohmic contact to the exposed polysilicon (31, 33, 29).

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: A metallization alloy for semiconductor devices comprising aluminum, copper, and tungsten is provided. In a method for applying the metallization, the metal is sputtered onto a semiconductor substrate having devices formed therein. After deposition, the metallization is patterned and etched using conventional semiconductor photoresist and etch techniques.

Abstract: A heat sink is attached to a semiconductor element functioning as an exothermic element, which is mounted on a circuit board and has a predetermined allowable power consumption, thereby cooling the semiconductor element. A semiconductor element having a lower allowable power consumption than the semiconductor element having the predetermined power consumption, which is hardly exposed to a cooling air flow cooled via the heat sink, is connected to a heat conductive auxiliary member connected at one end to the heat sink. Thus, the heat radiation efficiency of the semiconductor element having the lower allowable power consumption is enhanced.

Abstract: A first power semiconductor device with a semiconductor base to which an emitter wire electrode is connected through an emitter bonding pad and a gate wire electrode is connected through a gate bonding pad, wherein the gate bonding pad comprises a silicon oxide film, a silicon crystal layer and a gate wiring electrode made of aluminum containing silicon which are successively formed on the semiconductor base, and the gate wire electrode is connected to the gate wiring electrode. A second power semiconductor device wherein the emitter bonding pad is an emitter wiring electrode made of aluminum containing silicon which is directly formed on the semiconductor base, and the emitter wire electrode is bonded to the emitter wiring electrode.

Abstract: A leadframe for use in mounting and interconnecting an integrated circuit. A first or base metal layer of the leadframe comprises at least one of brass or other copper alloy. A second, conducting layer atop the base layer comprises at least one of aluminum or an aluminum alloy. A third, upper layer on the second layer comprises at least one of copper or a copper alloy. The first, second and third layers are formed into a multilayer clad strip, a portion of at least the third layer being selectively removed to expose a selected pattern of the second layer.

Abstract: A lower wiring layer is formed on an insulating film 12 covering a semiconductor substrate 10. The wiring layer 14 has a laminated structure of a barrier metal layer such as WSi2, an Al or Al alloy layer, and a cap metal layer such as WSi.sub.2 formed in this order from the bottom. The cap metal layer is caused to contain conductive material such as Al by using an ion injection method or the like. After forming an insulating film covering the wiring layer, a contact hole is formed in the insulating film by a dry etching process using a resist layer as a mask. The dry etching process uses a fluorine based gas such as CHF.sub.3 as the etching gas. With this etching gas, fluoride such as Al fluoride (AlF.sub.3) is generated to suppress the etching of the cap metal layer.

Abstract: Disclosed is an electrode for semiconductor devices capable of suppressing the generation of hillocks and reducing the resistivity, which is suitable for an active matrixed liquid crystal display and the like in which a thin film transistor is used; its fabrication method; and a sputtering target for forming the electrode film for semiconductor devices. The electrode for semiconductor devices is made of an Al alloy containing the one or more alloying elements selected from Fe, Co, Ni, Ru, Rh and Ir, in a total amount from 0.1 to 10 At %, or one or more alloying elements selected from rare earth elements, in a total amount from 0.05 to 15 at %.

Abstract: The close-packed plane of a single crystal forming an electrode line such as electrodes or lines of a semiconductor device whose active regions are reduced in size, i.e., highly integrated, is arranged parallel to the longitudinal direction of the line; or in the case of a polycrystalline electrode line, the angle formed between the normal line direction of the close-packed plane of its crystal grains and that of the electrode line is arranged to be 80.degree. or less.

Abstract: In a semiconductor device, an impurity diffused layer serving as an active region is formed in a predetermined region of the surface of a semiconductor substrate of silicon, an underlayer insulating film is formed on the semiconductor substrate for the purpose of protecting and stabilizing the surface of the semiconductor substrate, and an interconnection electrically connected to the impurity diffused layer through a contact hole and formed on an Al-Si-Sn alloy, an Al-Si-Sb alloy or alloys having Ti added to the respective alloys, so that occurrence of an alloy pit and a silicon nodule is prevented. In addition, a completed protective film is formed on the interconnection and the underlayer insulating film and an aperture in a bonding pad region is formed in a predetermined region of the completed protective film, so that the interconnection and the bonding pad are electrically connected to each other.

Abstract: A micro metal-wiring construction comprises a substrate having a first insulating layer thereon, a metal wiring formed on the first insulating layer of the substrate, and a second insulating layer covering the metal wiring. The coefficient of thermal expansion of the metal wiring is greater than those of the first and the second insulating layers. Intersection lines formed between grain boundaries of the metal wiring and a surface of the first insulating layer is nearly perpendicular to an extending direction of the metal wiring and an angle between grain boundary planes and a line that is perpendicular to a surface of the first insulating layer is greater than 20 degrees. Metal-wiring having a good resistance against stress-induced-migration is obtained by providing when this angle is greater than 20.degree..

Abstract: Interconnect or metallization structures for integrated circuits on semiconductor chips contain blocked conductor segments to limit atomic transport from one segment to another thus minimizing stress migration and electromigration damage. Since the blocked conductor segments prevent atomic transport between two neighboring segments, the total amount of atoms and vacancies available for hillock and void growth in a segment can be controlled by the length of the segment. The conductor segments are made of high electrical conductance metals, such as aluminum, copper or gold based alloys, and are separated by very short segments of a high melting temperature refractory metal or alloy. Because of their high melting temperatures, refractory metals or alloys suppress atomic transport. The interconnect structures can be fabricated by conventional lithographic and deposition techniques.

Abstract: Disclosed herein is a semiconductor device having a substrate, an insulating layer covering the substrate, a plurality of wiring layer formed on the insulating layer, each wiring layer having a top surface and a side surface, and a sidewall insulating film formed on and along the side surface of each of the wiring layers. The sidewall insulating film suppresses a hillock projecting from the side surface of each wiring layer.

Abstract: A thin-film transistor comprises a gate electrode formed on an insulating substrate, a gate insulating film covering the gate electrode and the insulating substrate, an i-type semiconductor layer formed on the gate insulating film, and a source electrode and a drain electrode electrically connected to two ends of the i-type semiconductor layer, respectively. The gate electrode is made of aluminum alloy containing high-melting-point metal such as Ti and Ta and oxygen or nitrogen or both.

Abstract: A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an insulating layer having an opening (contact hole or via) and a first conductive layer formed on the insulating layer which completely fills the opening. The first conductive layer does not produce any Si precipitates in a subsequent heat-treating step for filling the opening with the first conductive layer material. The semiconductor device may further include a second conductive layer having a planarized surface on the first conductive layer. This improves subsequent photolithography. An anti-reflective layer may be formed on the second conductive layer for preventing an unwanted reflection during a photo lithography process.

Abstract: A ferroelectric thin film element constructed by forming a first electrode composed of an alloy thin film of a Ni-Cr-Al system or Ni-Al system on a substrate and forming a ferroelectric thin film composed of a ferroelectric material having a composition having a spontaneous axis in the direction (111) and having a crystal orientation in the direction (111) on the first electrode composed of a thin film.

Abstract: A semiconductor integrated circuit device has an interconnection structure in which multilayer aluminum interconnection layers are connected through a connection hole. A first aluminum interconnection layer is formed on a main surface of said semiconductor substrate. An insulating layer is formed on the first aluminum interconnection layer and has a through hole extending to a surface of the first aluminum interconnection layer. A second aluminum interconnection layer is formed on the insulating layer and is electrically connected to the first aluminum interconnection layer through the through hole. The second aluminum interconnection layer includes a titanium layer, a titanium nitride layer and an aluminum alloy layer. The titanium layer is formed on the insulating layer to be in contact with the surface of the first aluminum interconnection layer through the through hole. The titanium nitride layer is formed on the titanium layer. The aluminum alloy layer is formed on the titanium nitride layer.

Abstract: A semiconductor device and a manufacture method for the semiconductor device, the method comprising the steps of forming an insulating film on the surface of a semiconductor substrate, forming contact holes in the insulating layer to expose the surface of the semiconductor substrate, selectively depositing a metal film, which contains aluminum as a main ingredient, on the exposed surface to form an electrodes in each the contact hole, and forming a wiring made of a second metal, which contains as a principal ingredient an element other than aluminum, on both the insulating layer and the electrode. Preferably, the upper surface of each electrode is substantially flat in a connecting portion between the electrode and the wiring, and a relationship of A.gtoreq.C is established where A is a length of one side of the electrode's upper surface and C is a width of the wiring in the connecting portion therebetween.

Abstract: There is disclosed a semiconductor device having an electrode for wire bonding, comprising a first aluminum layer, a nickel-aluminum alloy layer, and a second aluminum layer. The electrode is suitable for bonding with copper wire, since the electrode withstands a wide range of bonding conditions--mechanical pressure, ultrasonic wave power and such, and permits a reliable electrical connection to be maintained.

Abstract: An improved antifuse uses metal penetration of either a P-N diode junction or a Schottky diode. The P-N junction, or Schottky diode, is contacted by a diffusion barrier such as TiN, W, Ti-W alloy, or layers of Ti and Cr, with a metal such as Al. Al-CU alloy, Cu, Au, or Ag on top of the diffusion barrier. When this junction is stressed with voltage pulse producing a high current density, severe joule heating occurs resulting in metal penetration of the diffusion barrier and the junction. The voltage drop across the junction decreases by about a factor of ten after the current stress and is stable thereafter. Alternatively, a shallow P-N junction in a silicon substrate is contacted by a layer of metal that forms a silicide, such as Ti, Cr, W, Mo, or Ta. Stressing the junction with a voltage pulse to produce a high current density results in the metal penetrating the junction and reacting with the substrate to form a silicide.

Abstract: In this semiconductor device, contact holes extending from a lower interconnection layer containing diffusion layers at the surface of a Si substrate to an Al-involved interconnection layer formed above the Sis substrate through the intermediation of an interlayer dielectric film are filled with Al alloy having a eutectic point lower than that of Al-Si alloy. Then, for example, an Al-Ge alloy is sputtered, reflowed and allowed to react with the Si film to convert into an Al-Ge-Si alloy. At the stage of forming the Al-Ge-Si alloy, the reflow ceases. This brings the reduction of junction leakage current from the diffusion layers. Similarly in the case of a high aspect ratio of contact hole, this technique enables the contact hole to be fully filled with the above-mentioned Al alloy.

Abstract: A polar semiconductor quantum wire for use in electronic and opto-electronic devices. The polar semiconductor quantum wire is either completely or partially encapsulated in metal to reduce the strength of the scattering potential associated with interface optical phonons normally established at the lateral boundaries of polar semiconductor quantum wires. Metal alone or metal employed in conjunction with modulation doping enhances the transport of charge carriers within the polar semiconductor quantum wire.

Abstract: In a semiconductor device, an impurity diffused layer serving as an active region is formed in a predetermined region of the surface of a semiconductor substrate of silicon, an underlayer insulating film is formed on the semiconductor substrate for the purpose of protecting and stabilizing the surface of the semiconductor substrate, and an interconnection electrically connected to the impurity diffused layer through a contact hole and formed on an Al-Si-Sn alloy, an Al-Si-Sb alloy or alloys having Ti added to the respective alloys, so that occurrence of an alloy pit and a silicon nodule is prevented. In addition, a completed protective film is formed on the interconnection and the underlayer insulating film and an aperture in a bonding pad region is formed in a predetermined region of the completed protective film, so that the interconnection and the bonding pad are electrically connected to each other.

Abstract: A thin-film transistor comprises a gate electrode formed on a glass substrate, a gate insulating film formed essentially over an entire surface of the substrate to cover the gate electrode, a non-single-crystal silicon semiconductor film placed on the gate insulating film to cover the gate electrode; and a drain electrode and a source electrode spaced a specified distance apart on the semiconductor film and electrically connected to the semiconductor film so as to form the channel region of the transistor. The gate electrode is made of titanium-containing aluminum.

Abstract: A barrier material for use in preventing interdiffusion of silicon and aluminum at silicon/aluminum interfaces comprises a layer of titanium, aluminum, and nitrogen between about 100.ANG. and 1000.ANG. thick. The barrier material comprises between 1% and 20% aluminum, between 30% and 60% titanium, and between 30% and 60% nitrogen. The TiAlN material is more resistant to diffusion than TiN and can be etched and sputtered like TiN. It has better thermal budget than TiN and better stability on silicon, and thus can replace TiN in many of its uses in semiconductor devices.

Abstract: A semiconductor device formed by a semiconductor chip bonded to a lead frame die pad. The bonding material, such as a silicone resin, has an elasticity modulus ranging from 1 Kg/cm.sup.2 to 100 Kg/cm.sup.2 from room temperature to 400.degree. C. The lead frame electrodes are connected to the semiconductor chip electrodes by copper alloy wires.

Abstract: The close-packed plane of a single crystal forming an electrode line such as electrodes or lines of a semiconductor device whose active regions are reduced in size, i.e., highly integrated, is arranged parallel to the longitudinal direction of the line; or in the case of a polycrystalline electrode line, the angle formed between the normal line direction of the close-packed plane of its crystal grains and that of the electrode line is arranged to be 80.degree. or less.