Abstract: A compound semiconductor device includes: a substrate; a first barrier layer of a nitride semiconductor formed over the substrate; a well layer of a nitride semiconductor formed over the first barrier layer; and a second barrier layer of a nitride semiconductor formed over the well layer, wherein the first barrier layer, the well layer, and the second barrier layer each include a first region having, as an upper surface, a (0001) plane in terms of crystal orientation and a second region having, as an upper surface, a (000-1) plane in terms of crystal orientation, the first region of the first barrier layer, the first region of the well layer, and the first region of the second barrier layer are stacked, the second region of the first barrier layer, the second region of the well layer, and the second region of the second barrier layer are stacked.

Abstract: In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating characteristic from varying. A p-type channel layer having an impurity concentration distribution homogeneous in the depth direction at the sidewall part of a trench is formed by applying angled ion implantation of p-type impurities to a p?type body layer formed by implanting ions having implantation energies different from each other two or more times after the trench is formed. Further, although the p-type impurities are introduced also into an n?-type drift layer at the bottom part of the trench when the p-type channel layer is formed by the angled ion implantation, a channel length is stipulated by forming an n-type layer having an impurity concentration higher than those of the p-type channel layer, the p?-type body layer, and the n?-type drift layer between the p?-type body layer and the n?-type drift layer.

Abstract: In the silicon carbide semiconductor element, a second silicon carbide semiconductor layer that is in contact with the surface of a first silicon carbide semiconductor layer has at least an upper layer including a dopant of a first conductivity type at a high concentration. Above a junction field effect transistor (JFET) region interposed between body regions that are disposed in the first silicon carbide semiconductor layer so as to be spaced from each other, the silicon carbide semiconductor element has a channel removed region, which is a cutout formed by removing a high concentration layer from the front surface side of the second silicon carbide semiconductor layer, the high concentration layer having a higher dopant concentration than at least the dopant concentration of the JFET region. The width of the channel removed region is smaller than that of the JFET region.

Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.

Abstract: A vertical semiconductor device includes a semiconductor body having a front side, a backside arranged opposite to the front side and a lateral edge delimiting the semiconductor body in a horizontal direction perpendicular to the front side, a gate metallization arranged on the front side and extending at least close to the lateral edge; a contact metallization arranged on the front side and between the lateral edge and the gate metallization, and a backside metallization arranged on the backside and in electric contact with the contact metallization. The gate metallization is arranged around at least two sides of the contact metallization when viewed from above.

Abstract: A diode includes a second semiconductor layer over a first semiconductor layer. The diode further includes a third semiconductor layer over the second semiconductor layer, where the third semiconductor layer includes a first semiconductor element over the second semiconductor layer. The third semiconductor layer additionally includes a second semiconductor element over the second semiconductor layer, wherein the second semiconductor element surrounds the first semiconductor element. Further, the third semiconductor layer includes a third semiconductor element over the second semiconductor element. Furthermore, a hole concentration of the second semiconductor element is less than a hole concentration of the first semiconductor element.

Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.

Abstract: A thin diamond film bonded to a diamond substrate made by the process of heating a diamond substrate inside a vacuum chamber to about 500° C., cooling the diamond substrate, coating a first surface of the diamond substrate with chromium, depositing an initial layer of palladium, heating the diamond substrate, allowing the chromium and the diamond substrate to form a chemical bond, inter-diffusing the adhesion layer of chromium and the initial layer of palladium, cooling, depositing palladium, placing a shadow mask, degassing the vacuum, depositing a tin layer, assembling the tin layer, heating the tin layer, melting the tin layer, and bonding the thin diamond film to the diamond substrate. A thin diamond film bonded to a diamond substrate comprising a thin diamond film, a layer of chromium, palladium, tin, and a diamond substrate.

Abstract: A switching circuit is disclosed. The switching circuit includes a normally-on switching element, a normally-off switching element, a switching unit and a power source. The drain of the normally-off switching element is electrically connected to the source of the normally-on switching element. The source of the normally-off switching element is electrically connected to the gate of the normally-on switching element. The power source and the switching unit are configured to form a serial-connected branch. A first terminal of the serial-connected branch is electrically connected to the drain of the normally-off switching element. A second terminal of the serial-connected branch is electrically connected to the source of the normally-off switching element.

Abstract: The invention provides a low resistivity silicon carbide single crystal wafer for fabricating semiconductor devices having excellent characteristics. The low resistivity silicon carbide single crystal wafer has a specific volume resistance of 0.001 ?cm to 0.012 ?cm and 90% or greater of the entire wafer surface area is covered by an SiC single crystal surface of a roughness (Ra) of 1.0 nm or less.

Abstract: A device includes an n-doped InP layer and an ohmic contact, in contact with the n-doped InP layer. The ohmic contact includes an annealed stack of at least three, or preferably four alternating layers of Si and Ni, such that: (i) the n-doped InP layer and one of the layers of the stack in contact with the n-doped InP layer are at least partly intermixed; and (ii) any two adjacent layers of the stack are at least partly intermixed. Related fabrication methods are also disclosed.

Abstract: A method for manufacturing a silicon carbide semiconductor device comprises: a step for forming a front-surface electrode (30) on a front surface side of a silicon carbide wafer (10); a step for thinning the silicon carbide wafer (10) by reducing a thickness of the silicon carbide wafer (10) from a back surface side thereof; a step for providing a metal layer (21) on the back surface of the thinned silicon carbide wafer (10); a step for irradiating the metal layer (21) with laser light, while applying an external force such that the silicon carbide wafer and the metal layer are planarized, to form the carbide layer (20) obtained by a reaction with carbon in the silicon carbide wafer (10), on a back surface side of the metal layer (21); and a step for forming a back-surface electrode (40) on a back surface side of the carbide layer (20).

Abstract: A method includes depositing an ESL on a substrate; patterning the ESL such that a first region of the substrate is covered thereby and a second region of the substrate is exposed within an opening of the etch stop layer; depositing a first dielectric layer on the ESL in the first region and on the substrate in the second region; patterning the first dielectric layer to form a first trench through the first dielectric layer in the first region; forming a metal feature in the first trench; depositing a second dielectric layer over the metal feature in the first region and over the first dielectric layer in the second region; and performing a patterning process to form a second trench through the second dielectric layer in the first region, and to form a third trench through the second and first dielectric layers in the second region.

Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

Abstract: A reactor and method for seeded growth of nano-products such as carbon nanotubes, wires and filaments in which selected precursors are introduced into the reactor which is heated to a temperature sufficient to induce nano-product formation from interaction between the precursor gases and a nanopore templated catalyst. The selected precursors are segregated in the reactor through a plate defining two chambers which are sealed off from each other except for a void space provided in the plate. The void space is closed off by a membrane having nanopores and a catalyst formed as a layer. Atomic transfer of material from the selected precursors to form the nano-products on the catalyst layer in the other of the chambers occurs by diffusion through the catalyst layer to form the nano-product on the other of the chambers absent a pressure drop between the two chambers.

Abstract: A data storage device may include a package substrate, and an upper semiconductor chip disposed above a top surface of the package substrate. At least one lower bump is disposed on a bottom surface of the package substrate. A lower semiconductor chip is disposed on the bottom surface of the package substrate and spaced apart from the at least one lower bump. The lower semiconductor chip is thinner than the at least one lower bump.

Abstract: A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.

Abstract: A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.

Abstract: A silicon carbide semiconductor device includes an n+-type SiC substrate, a gate oxide film formed on a portion of the surface of the n+-type SiC substrate, a gate electrode formed on the gate oxide film, an interlayer insulating film formed so as to cover the gate electrode, a TiN film formed so as to cover the interlayer insulating film, and a Ni silicide layer formed on a surface of the n+-type SiC substrate not covered by the interlayer insulating film. The TiN film has two or more layers.

Abstract: A semiconductor device manufacturing method includes forming a first resist and a second resist on a stacked body that includes a plurality of first films and a plurality of second films, the second resist facing one or more side surfaces of the first resist; forming a third film in a slit between the first resist and the second resist, the third film covering the side surfaces of the first resist and defining exposed surfaces of the first resist not covered by the third film; performing a first etch of the stacked body from an upper surface using the first resist, the second resist, and the third film as a mask; selectively etching the one or more exposed surfaces of the first resist and the second resist; and performing a second etch of the stacked body from the upper surface using the first resist and the third film as a mask.

Abstract: Methods for forming an epilayer on a surface of a substrate are generally provided. For example, a substrate can be positioned within a hot wall CVD chamber (e.g., onto a susceptor within the CVD chamber). At least two source gases can then be introduced into the hot wall CVD chamber such that, upon decomposition, fluorine atoms, carbon atoms, and silicon atoms are present within the CVD chamber. The epilayer comprising SiC can then be grown on the surface of the substrate in the presence of the fluorine atoms.

Abstract: A light emitting element has: first and second conductivity type semiconductor layers, first and second electrodes disposed on the same face side of the first and second conductivity type semiconductor layers, respectively. In plan view, the first electrode has a first connecting portion, a first extending portion, and two second extending portions, and the second electrode has a second connecting portion and two third extending portions. The first extending portion of the first electrode extends linearly from the first connecting portion toward the second connecting portion, and the two second extending portions extend parallel to the first extending portion on two sides of the first extending portion. The second extending portions each has two bent portions. The third extending portions extend parallel to the first extending portion between the first extending portion and the two second extending portions.

Abstract: This semiconductor device includes: a semiconductor layer that is formed of first conductivity-type SiC; a plurality of trenches that are formed in the semiconductor layer; second conductivity-type column regions that are formed along the inner surfaces of the trenches; a first conductivity-type column region that is disposed between the adjacent second conductivity-type column regions; and insulating films that are embedded in the trenches. The semiconductor device is capable of improving a withstand voltage by means of a super junction structure. The semiconductor device may also include an electric field attenuation section for attenuating electric field intensity of a surface section of the first conductivity-type column region.

Abstract: A programmable cell includes a semiconductor-on-insulator substrate, a program gate, and a word line gate. The semiconductor-on-insulator substrate includes a semiconductor layer. The semiconductor layer includes a first doped source/drain region, a second doped source/drain region and a region comprising germanium. The program gate is disposed above the region comprising germanium and includes a first gate dielectric layer disposed below a gate conductor. The word line gate is disposed between the first doped source/drain region and the second doped source/drain region.

Abstract: A Schottky barrier diode includes: an n+ type of silicon carbide substrate; an n? type of epitaxial layer formed on a first surface of the n+ type of silicon carbide substrate; a plurality of p+ regions formed inside the n? type of epitaxial layer; a Schottky electrode formed in an upper portion of the n? type of epitaxial layer of an electrode region; and an ohmic electrode formed on a second surface of the n+ type of silicon carbide substrate, wherein the plurality of p+ regions are formed to be spaced apart from each other at a predetermined interval within the n? type of epitaxial layer.

Abstract: A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer. Thus, breakdown of the insulating film in the gate region can be prevented without causing deterioration in quality of the gate insulating film, upon switching and avalanche breakdown.

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first fin-shaped pattern including an upper part and a lower part on a substrate, forming a second fin-shaped pattern by removing a part of the upper part of the first fin-shaped pattern, forming a dummy gate electrode intersecting with the second fin-shaped pattern on the second fin-shaped pattern, and forming a third fin-shaped pattern by removing a part of an upper part of the second fin-shaped pattern after forming the dummy gate electrode, wherein a width of the upper part of the second fin-shaped pattern is smaller than a width of the upper part of the first fin-shaped pattern and is greater than a width of an upper portion of the third fin-shaped pattern.

Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

Abstract: An object of the present invention is to provide a semiconductor device capable of eliminating unevenness of current distribution in a plane. A semiconductor device according to the present invention is a semiconductor device including a transistor cell region where a plurality of transistor cells is arranged on a semiconductor substrate, the semiconductor device including an electrode pad which is arranged avoiding the transistor cell region on the semiconductor substrate and is electrically connected to a one-side current electrode of each of the cells, in which the transistor cell region contains a plurality of regions each of which has a different current drive capability from each other depending on a distance from the electrode pad.

Abstract: What is provided is a field effect component including a semiconductor body, which extends in an edge zone from a rear side as far as a top side and which includes a semiconductor mesa, which extends in a vertical direction, which is perpendicular to the rear side and/or the top side. The semiconductor body in a vertical cross section further includes a drift region, which extends at least in the edge region as far as the top side and which is arranged partly in the semiconductor mesa, and a body region, which is arranged at least partly in the semiconductor mesa and which forms a pn junction with the drift region. The pn junction extends between two sidewalls of the semiconductor mesa.

Abstract: A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further includes a source, a drain, and a gate between the source and the drain, the gate being over the III-N layer structure. The p-type III-N layer includes a first portion that is at least partially in a device access region between the gate and the drain, and the first portion of the p-type III-N layer is electrically connected to the source and electrically isolated from the drain. When the transistor is biased in the off state, the p-type layer can cause channel charge in the device access region to deplete as the drain voltage increases, thereby leading to higher breakdown voltages.

Abstract: A method for manufacturing a plurality of fingerprint identification modules simultaneously is provided. A first thin film and a second thin film are formed on a first transfer base and a second transfer base respectively. The first thin film and the second thin film are cut respectively to form a plurality of first thin film units and a plurality of second thin film units. The first transfer base and the second transfer base are adhered on opposite surfaces of a substrate. The first thin film units and the second thin film units are cut respectively to form a plurality of the first piezoelectric layers and a plurality of the second piezoelectric layers. A plurality of first slits and a plurality of second slits are formed on opposite surfaces of the substrate for breaking the mother base into the fingerprint identification modules.

Abstract: A layered semiconductor includes a base layer including a substrate and a buffer layer, and a drift layer which is disposed on the base layer and is made of GaN and whose conductivity type is an n-type. The drift layer has an average n-type impurity concentration of 1.5×1016 cm?3 or less in a radial direction of the substrate, and the difference between the maximum n-type impurity concentration and the minimum n-type impurity concentration is 1.5×1015 cm?3 or less.

Abstract: A hybrid organic-inorganic micromirror device includes a micromirror comprising an inorganic material positioned above an elastomeric substrate. The micromirror is supported on an underside thereof by a conductive elastomeric support protruding from the elastomeric substrate. The conductive elastomeric support may function as a universal joint and is rendered electrically conductive by an electrically conductive coating thereon. A plurality of electrodes are disposed on the elastomeric substrate under the micromirror. The electrodes are spaced apart from each other and from the micromirror and are arranged around the conductive elastomeric support. Each electrode comprises an inorganic material and is in electrical contact with an elastomeric contact region protruding from the elastomeric substrate. When a voltage bias is applied between the micromirror and one or more of the electrodes, the micromirror is electrostatically actuated to move in a predetermined direction.

Abstract: Disclosed herein is a technique for realizing a high-performance and high-reliability silicon carbide semiconductor device. A trenched MISFET with a trench formed into the drift through a p-type body layer 105 includes an n-type resistance relaxation layer 109 covering the bottom portion of the trench, and a p-type field relaxation layer 108. The p-type field relaxation layer 108 is separated from the trench bottom portion via the resistance relaxation layer 109, and is wider than the resistance relaxation layer 109. This achieves a low ON resistance, high reliability, and high voltage resistance at the same time. By forming the field relaxation layer beneath the trench, feedback capacitance can be controlled to achieve a high switching rate and high reliability.

Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.

Abstract: A silicon-doped n-type aluminum nitride monocrystalline substrate wherein, at a photoluminescence measurement at 23° C., a ratio (I1/I2) between the emission spectrum intensity (I1) having a peak within 370 to 390 nm and the emission peak intensity (I2) of the band edge of aluminum nitride is 0.5 or less; a thickness is from 25 to 500 ?m; and a ratio (electron concentration/silicon concentration) between the electron concentration and the silicon concentration at 23° C. is from 0.0005 to 0.001.

Abstract: A SiC Schottky-barrier diode and a SiPiN diode are connected in parallel. Due to a difference in their thermal properties, a relatively large current flows in the SiPiN diode at a high temperature in which electro migration progresses easily in a solder layer, and the progression of the electro migration is suppressed. At a low temperature in which the electro migration does not progress so much, only a relatively small current flows in the SiPiN diode, and a loss suppression by the SiC Schottky-barrier diode is achieved.

Abstract: A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer having a first main surface and a second main surface opposite to the first main surface. In the second main surface of the silicon carbide layer, a trench having a depth in a direction from the second main surface toward the first main surface is provided, and the trench has a sidewall portion where a second layer and a third layer are exposed and a bottom portion, where a first layer is exposed. A position of the bottom portion of the trench in a direction of depth of the trench is located on a side of the second main surface relative to a site located closest to the first main surface in a region where the second layer and the first layer are in contact with each other, or located as deep as the site in the direction of depth.

Abstract: A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm. A method for manufacturing a semiconductor device according to the present invention includes: a step of forming a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, on the surface of a first conductive-type SiC semiconductor layer; and a step for heat treating the Schottky metal while the surface thereof is exposed, and structuring the junction of the SiC semiconductor layer to the Schottky metal to be planar, or to have recesses and protrusions of equal to or less than 5 nm.

Abstract: A Schottky metal 9 is in Schottky-contact with a center portion of a surface of an epitaxial layer 4. A peripheral trench 13 is formed by digging from the surface of the epitaxial layer 4 on a boundary portion between an active region 21 where the Schottky metal 9 is in Schottky-contact with the surface of the epitaxial layer 4 and a peripheral region 22 outside of the active region in a surface layer portion of the epitaxial layer 4. An insulating film 14 is formed on an entire area of inner wall surfaces of the peripheral trench 13. There is provided with a conductor 15 which is connected to the Schottky metal 9 and is opposed to the entire area of the inner wall surfaces of the peripheral trench 13 via the insulating film 14 in the peripheral trench 13.

Abstract: Certain embodiments of the present invention may be directed to a transistor structure. The transistor structure may include a semiconductor substrate. The semiconductor substrate may include a drift region, a collector region, an emitter region, and a lightly-doped/undoped region. The lightly-doped/undoped region may be lightly-doped and/or undoped. The transistor structure may also include a heterostructure. The heterostructure forms a heterojunction with the lightly-doped/undoped region. The transistor structure may also include a collector terminal. The collector terminal is in contact with the collector region. The transistor structure may also include a gate terminal. The gate terminal is in contact with the heterostructure. The transistor structure may also include an emitter terminal. The emitter terminal is in contact with the lightly-doped/undoped region and the emitter region.

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer and a gate insulating layer. The silicon carbide layer has a main surface. The gate insulating layer is arranged as being in contact with the main surface of the silicon carbide layer. The silicon carbide layer includes a drift region having a first conductivity type, a body region having a second conductivity type different from the first conductivity type and being in contact with the drift region, a source region having the first conductivity type and arranged as being spaced apart from the drift region by the body region, and a protruding region arranged to protrude from at least one side of the source region and the drift region into the body region, being in contact with the gate insulating layer, and having the first conductivity type.

Abstract: The present disclosure provides a semiconductor device and formation method thereof. A shallow trench isolation structure is formed in a semiconductor substrate. A first dielectric layer is formed on the semiconductor substrate. First and second dummy gate structures are formed on the shallow trench isolation structure and through the first dielectric layer. A resistive material layer is formed on the first and second dummy gate structures and on the first dielectric layer between the first and second dummy gate structures. A second dielectric layer is formed on the first dielectric layer and the resistive material layer. A first plug is formed in the second dielectric layer and the resistive material layer and on the first dummy gate structure. A second plug is formed in the second dielectric layer and the resistive material layer and on the second dummy gate structure.

Abstract: A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface, barrier regions having a second conductivity type and disposed within the silicon carbide semiconductor layer, an edge termination region having the second conductivity type and disposed within the silicon carbide semiconductor layer, the edge termination region enclosing the barrier regions, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the back surface, wherein each of the barrier regions has a polygonal boundary with the silicon carbide semiconductor layer, and each of sides of the polygonal boundary has an angle of 0° to 5° inclusive relative to <11-20> direction of crystal orientations of the semiconductor substrate.

Abstract: A detection device having: a terahertz wave generation element; a terahertz wave detection element; a first transmission path arranged upon the terahertz wave generation element; a second transmission path arranged upon the terahertz wave detection element; and a sealed section arranged between the terahertz wave generation element and the terahertz wave detection element and separated from the first transmission path and the second transmission path, so as to surround the first transmission path and the second transmission path. A space between an emission surface in the first transmission path and an incident surface in the second transmission path is connected to a space between the first transmission path and the sealed section and to a space between the second transmission path and the sealed section.

Abstract: An electrode comprises an acid treated, cathodically cycled carbon-comprising film or body. The carbon consists of single walled nanotubes (SWNTs), pyrolytic graphite, microcrystalline graphitic, any carbon that consists of more than 99% sp2 hybridized carbons, or any combination thereof. The electrode can be used in an electrochemical device functioning as an electrolyzer for evolution of hydrogen or as a fuel cell for oxidation of hydrogen. The electrochemical device can be coupled as a secondary energy generator into a system with a primary energy generator that naturally undergoes generation fluctuations. During periods of high energy output, the primary source can power the electrochemical device to store energy as hydrogen, which can be consumed to generate electricity as the secondary source during low energy output by the primary source. Solar cells, wind turbines and water turbines can act as the primary energy source.

Abstract: Process (A) of preparing a silicon carbide substrate of a first conductivity type; process (B) of forming an epitaxial layer of the first conductivity type on one principal surface of the silicon carbide substrate; process (C) of forming on another principal surface of the silicon carbide substrate, a first metal layer; process (D) of heat treating the silicon carbide substrate after the process (C) to form an ohmic junction between the first metal layer and the other principal surface of the silicon carbide substrate, and a layer of a substance (10) highly cohesive with another metal on the first metal layer; and a process (E) of removing impurities and cleaning a surface of the first metal layer (8) on the other principal surface of the silicon carbide substrate (D), are performed. The heat treatment at process (D) is executed at a temperature of 1,100 degrees C. or more.

Abstract: An SiC trench transistor having a first terminal and an epitaxial layer positioned vertically between a gate trench and a second terminal; a compensation layer extending horizontally being provided in the epitaxial layer, the compensation layer having an effective doping of a type opposite to the doping of the epitaxial layer. A method for manufacturing an SiC trench transistor is also provided, an epitaxial layer being provided on a second terminal of the SiC trench transistor; a compensation layer extending horizontally being implanted in the epitaxial layer, the compensation layer having an effective doping of a type opposite to the doping of the epitaxial layer; and a first terminal and a gate trench being provided above the compensation layer.