Abstract: A method for fabricating a semiconductor device comprises: Firstly, a semiconductor fin comprising a first sub-fin and a second sub-fin protruding from a surface of a substrate is provided. An isolation structure having an opening extending therein is then provided in the semiconductor fin to electrically isolate the first sub-fin and the second sub-fin. Subsequently, a first dummy structure disposed on the first isolation structure and having at least one metal layer entirely overlapping on the first isolation structure along a long axis of the semiconductor fin is formed, wherein the metal layer laterally conformally extends downwards into the opening and extends upwards beyond the first isolation structure along the long axis of the semiconductor fin, so as to form a stepped structure overlapping on sidewalls and a bottom of the opening, a portion of the first sub-fin and a portion of the second sub-fin.

Abstract: A light emitting element having; a first and a second conductivity type semiconductor layers, a first and a second electrodes formed on the first and second conductivity type semiconductor layer, the first and the second electrodes being disposed on the same face side of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, in plan view, the first electrode having a first connecting portion, a first extending portion, and two second extending portions, the second electrode having a second connecting portion and two third extending portions, the first extending portion of the first electrode extending linearly from the first connecting portion toward the second connecting portion, and the two second extending portions extending parallel to the first extending portion on two sides of the first extending portion, the two third extending portions of the second electrode extending parallel to the first extending portion between the first extending portion and the two

Abstract: A Schottky barrier diode element includes an n-type or p-type silicon (Si) substrate, an oxide semiconductor layer, and a Schottky electrode layer, the oxide semiconductor layer including either or both of a polycrystalline oxide that includes gallium (Ga) as the main component and an amorphous oxide that includes gallium (Ga) as the main component.

Abstract: A semiconductor substrate has an element portion and a termination portion located on an outer side of the element portion. A first electrode layer is provided on a first surface of the semiconductor substrate. A second electrode layer is provided on a second surface of the semiconductor substrate in an upper portion of the element portion. An interlayer insulation film is provided on the second surface of the semiconductor substrate. The interlayer insulation film has: an element insulation portion that provides insulation between a part of the element portion of the semiconductor substrate and the second electrode layer; and a termination insulation portion covering a termination portion of the semiconductor substrate. The termination insulation portion includes a high dielectric constant film that is higher in dielectric constant than the element insulation portion.

Abstract: A method for fabricating an epi wafer according to the embodiment comprises depositing an epi layer on a wafer in a first chamber; transferring the wafer to a second chamber connected to the first chamber; forming a protective layer on the wafer in the second chamber; and cooling the wafer in the second chamber. Further, an apparatus for fabricating an epi wafer according to the embodiment comprises a first chamber comprising an epi deposition part; a second chamber comprising a protective layer forming part and a cooling part; and a wafer transfer apparatus connected to lower portions of the first chamber and the second chamber.

Abstract: A semiconductor device includes: a buffer layer formed over a substrate; a first semiconductor layer formed over the buffer layer by using a compound semiconductor; a second semiconductor layer formed over the first semiconductor layer by using a compound semiconductor; and a gate electrode, a source electrode, and a drain electrode formed over the second semiconductor layer, wherein the first semiconductor layer contains an impurity element serving as an acceptor and an impurity element serving as a donor; and in the first semiconductor layer, an acceptor concentration of the impurity element serving as the acceptor is greater than a donor concentration of the impurity element serving as the donor; and the donor concentration is greater-than over equal to 5×1016 cm?3.

Abstract: A semiconductor device includes a junction field effect transistor cell with a top gate region, a lateral channel region and a buried gate region. The lateral channel region is arranged between the top gate region and the buried gate region along a vertical direction with respect to a first surface of a semiconductor body. The lateral channel region comprises at least two first zones of a first conductivity type and at least one second zone of a second conductivity type, wherein the first and second zones alternate along the vertical direction. The embodiments provide well-defined channel widths and facilitate the adjustment of pinch-off voltages as well as the manufacture of normally-off junction field effect transistor cells.

Abstract: A semiconductor device of the present invention includes a semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode being in contact with a surface of the semiconductor layer. The semiconductor layer includes a drift layer that forms the surface of the semiconductor layer and a high-resistance layer that is formed on a surface layer portion of the drift layer and that has higher resistance than the drift layer. The high-resistance layer is formed by implanting impurity ions from the surface of the semiconductor layer and then undergoing annealing treatment at less than 1500° C.

Abstract: A method of forming a transistor device include forming a drift layer of a first conductivity type, forming a well of a second conductivity type in the drift layer, forming a JFET region with first conductivity type dopant ions in the drift layer, forming a channel adjustment layer of the first conductivity type on the JFET region and the well, implanting first conductivity type dopant ions to form an emitter region of the first conductivity type extending through the channel adjustment layer and into the well, wherein the emitter region is spaced apart from the JFET region by the well, implanting second conductivity type dopant ions to form a connector region of the second conductivity type adjacent the emitter region, forming a gate oxide layer on the channel region, and forming a gate on the gate oxide layer.

Abstract: A method for manufacturing a semiconductor device including a cell region and a peripheral region formed outside the cell region, comprising the steps of (a) providing a semiconductor substrate including a first epitaxial layer of a first conductivity type formed over a main surface thereof, (b) doping a lower band gap impurity for making the band gap smaller than the band gap of the first epitaxial layer before doping into the first epitaxial layer in the cell region, and thereby forming a lower band gap region, (c) after the step (b), forming a plurality of first column regions of a second conductivity type which is the opposite conductivity type to the first conductivity type in such a manner as to be separated from one another in the first epitaxial layer extending from the cell region to the peripheral region, and (d) after the step (c), forming a second epitaxial layer.

Abstract: A method for manufacturing an n-type SiC single crystal, enables the suppression of the variation in nitrogen concentration among a plurality of n-type SiC single crystal ingots manufactured. A method includes the steps of: providing a manufacturing apparatus (100) including a chamber (1) having an area in which a crucible (7) is to be disposed; heating the area in which the crucible (7) is to be disposed and evacuating the gas in the chamber (1); filling, after the evacuation, the chamber (1) with a mixed gas containing a noble gas and nitrogen gas; heating and melting a starting material housed in the crucible (7) disposed in the area to produce a SiC solution (8) containing silicon and carbon; and immersing a SiC seed crystal into the SiC solution under the mixed gas atmosphere to grow an n-type SiC single crystal on the SiC seed crystal.

Abstract: A method for preparing a power diode, including: providing a substrate (10), growing a N type layer (20) on the front surface of the substrate (10); forming a terminal protecting ring; forming an oxide layer (30), knot-pushing to the terminal protecting ring; forming a gate oxide layer (60), depositing a poly-silicon layer (70) on the gate oxide layer (60); depositing a SiO2 layer (80) on the surface of the poly-silicon layer (70) and a oxide layer (50); forming a N type heavy doped region (92); forming a P+ region; removing a photoresist, implanting P type ions using the SiO2 layer (80) as a mask layer, and forming a P type body region; heat annealing; forming a side wall structure in the opening of the poly-silicon layer (70), the gate oxide layer (60) being etched, and removing the SiO2 layer (80); and processing a front surface metallization and a back surface metallization treatment.

Abstract: In a semiconductor device, a first active region has a first ?-shape, and the second active region has a second ?-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

Abstract: There is provided a silicon carbide semiconductor device having an improved switching characteristic. A MOSFET includes a silicon carbide layer, a gate insulating film, a gate electrode, and a source electrode. The silicon carbide layer includes a drift region, a body region, and a contact region. The source electrode is in contact with the contact region in a main surface. The MOSFET is configured such that contact resistance of the source electrode with respect to the contact region is not less than 1×10?4 ?cm2 and not more than 1×10?1 ?cm2. Moreover, when viewed in a plan view of the main surface, an area of the contact region is not less than 10% of an area of the body region.

Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.

Abstract: The present invention provides a semiconductor device that can achieve both low on-resistance and high withstand voltage, while reducing the device size, improving the manufacturing yield, and reducing the cost. The semiconductor device 1 includes a substrate 5, an epitaxial layer 6 formed on the substrate 5 and formed with a gate trench 11, a gate insulating film 17 formed on the side surface 14 and the bottom surface 15 of the gate trench 11, a gate electrode 20 embedded in the gate trench 11 and opposed to the epitaxial layer 6 with the gate insulating film 17 therebetween, and a source layer 25, a channel layer 26, and a drift layer 27 formed in this order from a first surface to a second surface of the epitaxial layer 6, in which the on-resistance Ron represented by a variable “y” and the withstand voltage Vb represented by a variable “x” functionally satisfy the following relational expression (1): y?9×10?7x2?0.0004x+0.7001??(1).

Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate; an n-type SiC layer provided on one side of the semiconductor substrate; a p-type first SiC region provided in the n-type SiC layer; a metallic second SiC region provided in the p-type first SiC region, the second SiC region containing at least one element selected from the group of Mg, Ca, Sr, Ba, Sc, Y, La, and lanthanoid; a gate electrode; a gate insulating film provided between the gate electrode and the n-type SiC layer, the gate insulating film provided between the gate electrode and the first SiC region; a first electrode provided on the second SiC region; and a second electrode provided on a side of the semiconductor substrate opposite to the n-type SiC layer.

Abstract: A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation ? of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation ? of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.

Abstract: In order to provide a high-performance and reliable silicon carbide semiconductor device, in a silicon carbide semiconductor device including an n-type SiC epitaxial substrate, a p-type body layer, a p-type body layer potential fixing region and a nitrogen-introduced n-type first source region formed in the p-type body layer, an n-type second source region to which phosphorus which has a solid-solubility limit higher than that of nitrogen and is easily diffused is introduced is formed inside the nitrogen-introduced n-type first source region so as to be separated from both of the p-type body layer and the p-type body layer potential fixing region.

Abstract: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The first semiconductor region includes silicon carbide. A conductivity type of the first semiconductor region is a first conductivity type. The second semiconductor region includes silicon carbide. A conductivity type of the second semiconductor region is a second conductivity type. The third semiconductor region includes silicon carbide. A conductivity type of the third semiconductor is the second conductivity type. The third semiconductor region is provided between the first semiconductor region and the second semiconductor region. As viewed in a direction connecting the first semiconductor region and the second semiconductor region, an area of an overlapping region of the second semiconductor region and the third semiconductor region is smaller than an area of an overlapping region of the first semiconductor region and the second semiconductor region.

Abstract: A method of manufacturing a semiconductor element includes a first step of epitaxially growing an AlN layer on a substrate, a second step of forming a buffer layer on the AlN layer by epitaxially growing AlxGayInzN where x, y, and z satisfy x+y+z=1 and y is not zero without adding Fe, a third step of forming a resistance layer on the buffer layer by epitaxially growing AlxGayInzN where x, y, and z satisfy x+y+z=1 and y is not zero while adding Fe, a step of epitaxially growing a channel layer on the resistance layer, a step of epitaxially growing an electron supply layer above the channel layer, and a step of forming an electrode above the electron supply layer.

Abstract: The present invention provides a diamond semiconductor device which includes: a diamond substrate; a diamond step section disposed over substrate surface of the diamond substrate having a {001} crystal face to rise substantially perpendicularly to substrate surface; an n-type phosphorus-doped diamond region; and a diamond insulation region. In the diamond step section, a first step section having a {110} crystal face over a side surface is integrated with a second step section having a {100} crystal face over a side surface. The phosphorus-doped diamond region is formed by crystal growth started from base angle of the step shape of the first step section over the side surface of the first step section and substrate surface of the diamond substrate as growth base planes. The diamond insulation region is formed by crystal growth over the side surface of the second step section and substrate surface of the diamond substrate as growth base planes.

Abstract: The object cutting method comprises a step of locating a converging point of laser light within a monocrystal sapphire substrate, while using a rear face of the monocrystal sapphire substrate as an entrance surface of the laser light, and relatively moving the converging point along each of a plurality of lines to cut set parallel to the m-plane and rear face of the substrate, so as to form first and second modified regions within the substrate along each line and cause a fracture to reach a front face. In this step, in each line, with respect to a tilted surface passing the first region while being parallel to the r-plane of the substrate, the second region is positioned on the side where the tilted surface and rear face form an acute angle.

Abstract: A strain sensor provided with a substrate that has flexibility; a carbon nanotube (CNT) film that is provided on the surface of the substrate and that has a plurality of CNT fibers oriented in one direction; and a pair of electrodes that are arranged at both ends in the orientation direction of the CNT fibers in the CNT film; in which the CNT film has a plurality of CNT fiber bundles that consist of the plurality of CNT fibers, and a resin layer that covers the peripheral surface of the plurality of the CNT fiber bundles and joins with the surface of the substrate.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a main electrode, a first barrier layer, and an interconnection layer. The main electrode is directly provided on the silicon carbide substrate. The first barrier layer is provided on the main electrode, and is made of a conductive material containing no aluminum. The interconnection layer is provided on the first barrier layer, is separated from the main electrode by the first barrier layer, and is made of a material containing aluminum.

Abstract: A method of manufacturing a semiconductor device includes performing a cycle a predetermined number of times, the cycle including supplying a first precursor containing a specific element and a halogen group to form a first layer and supplying a second precursor containing the specific element and an amino group to modify the first layer into a second layer. A temperature of the substrate is set such that a ligand containing the amino group is separated from the specific element in the second precursor, the separated ligand reacts with the halogen group in the first layer to remove the halogen group from the first layer, the separated ligand is prevented from being bonded to the specific element in the first layer, and the specific element from which the ligand is separated in the second precursor is bonded to the specific element in the first layer.

Abstract: The present disclosure provides a semiconductor device including a substrate, a gate structure, a channel layer, a first active region and a second active region. The gate structure is disposed in the substrate. The channel layer is sandwiched between the gate structure and the substrate. A material of the channel layer is selected from the group consisting of silicon-germanium epitaxial material, silicon-carbon epitaxial material, and a combination thereof. The first active region and the second active region are disposed in the substrate and respectively disposed at opposite sides of the gate structure. A method for manufacturing a semiconductor device is provided herein.

Abstract: An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a Schottky junction with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact.

Abstract: A semiconductor device according to one embodiment includes an n-type first GaN-based semiconductor layer, a p-type second GaN-based semiconductor layer on the first GaN-based semiconductor layer. The second GaN-based semiconductor layer includes a low impurity concentration region and a high impurity concentration region. An n-type third GaN-based semiconductor layer is provided on the second GaN-based semiconductor layer. The device includes a gate electrode being located adjacent to the third GaN-based semiconductor layer, the low impurity concentration region, and the first GaN-based semiconductor layer intervening a gate insulating film. The device includes a first electrode on the third GaN-based semiconductor layer, a second electrode on the high impurity concentration region, and a third electrode on the opposite side of the first GaN-based semiconductor layer from the second GaN-based semiconductor layer.

Abstract: In a general aspect, an apparatus can include a semiconductor substrate, a drift region disposed in the semiconductor substrate; a body region disposed in the drift region and a source region disposed in the body region. The apparatus can also include a gate trench disposed in the semiconductor substrate. The apparatus can further include a gate dielectric disposed on a sidewall and a bottom surface of the gate trench, the gate dielectric on the sidewall defining a first interface with the body region and the gate dielectric on the bottom surface defining a second interface with the body region. The apparatus can still further include a gate electrode disposed on the gate dielectric and a lateral channel region disposed in the body region, the lateral channel region being defined along the second interface.

Abstract: A semiconductor device includes a first chip including a PN junction diode, and a second chip including a Schottky barrier diode, connected in parallel to the first chip. A first inductive metal member has a first end connected to a cathode of the PN junction diode, and a second end connected to a cathode of the Schottky barrier diode. A second inductive metal member has a third end connected to the cathode of the Schottky barrier diode. An output line is connected to a fourth end of the second connection member, and electrically connected to the cathode of the PN junction diode via a first path formed by the first and second metal members, and to the cathode of the Schottky barrier diode via a second path formed by the second metal member and exclusive of the first metal member, so that the first path has greater inductance than the second.

Abstract: A semiconductor device is provided with a base member having a front surface and a plurality of semiconductor chips provided on the front surface and each having a long side and a short side, the plurality of semiconductor chips being aligned so that the long sides are faced with each other. The plurality of semiconductor chips are provided diagonally, respectively, so that the adjacent semiconductor chips are inclined to the same side in a planar view of the front surface.

Abstract: Provided are methods of forming field effect transistors. The method includes preparing a substrate with a first region and a second region, forming fin portions on the first and second regions, each of the fin portions protruding from the substrate and having a first width, forming a first mask pattern to expose the fin portions on the first region and cover the fin portions on the second region, and changing widths of the fin portions provided on the first region.

Abstract: A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The second electrode layer is connected with at least a part of a surface of the first electrode layer which is opposite to a surface of the first electrode layer that is in contact with the n-type semiconductor layer.

Abstract: A UNCD nanowire comprises a first end electrically coupled to a first contact pad which is disposed on a substrate. A second end is electrically coupled to a second contact pad also disposed on the substrate. The UNCD nanowire is doped with a dopant and disposed over the substrate. The UNCD nanowire is movable between a first configuration in which no force is exerted on the UNCD nanowire and a second configuration in which the UNCD nanowire bends about the first end and the second end in response to a force. The UNCD nanowire has a first resistance in the first configuration and a second resistance in the second configuration which is different from the first resistance. The UNCD nanowire is structured to have a gauge factor of at least about 70, for example, in the range of about 70 to about 1,800.

Abstract: A semiconductor device according to an embodiment includes a SiC layer including a first region provided at a surface. The first region satisfies NA?ND<5×1015 cm?3 when a concentration of a p-type impurity is denoted by NA, whereas a concentration of an n-type impurity is denoted by ND. The surface is inclined at 0 degrees or more and 10 degrees or less to a {000-1} face, or the surface having a normal direction inclined at 80 degrees or more and 90 degrees or less to a <000-1> direction. The device includes a gate electrode, a gate insulating film provided between the SiC layer and the gate electrode, and a second region provided between the first region and the gate insulating film. The second region has a nitrogen concentration higher than 1×1022 cm?3.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor part and a conductive electrode. The first semiconductor part is made of SiC. The SiC contains a first element as an n-type or p-type impurity. The first semiconductor part has a first interface part. The first interface part is configured to have maximum area density of the first element. The c conductive electrode is electrically connected to the first interface part.

Abstract: A junction field effect transistor cell of a semiconductor device includes a top gate region, a lateral channel region and a buried gate region arranged along a vertical direction. The lateral channel region includes first zones of a first conductivity type and second zones of a second conductivity type which alternate along a lateral direction perpendicular to the vertical direction. A pinch-off voltage of the junction field effect transistor cell does not depend, or only to a low degree depends, on a vertical extension of the lateral channel region.

Abstract: In one general aspect, an apparatus can include a silicon carbide (SiC) crystal having a top surface aligned along a plane and the SiC crystal having an off-orientation direction. The apparatus including a semiconductor device defined within the SiC crystal. The semiconductor device having an outer perimeter where the outer perimeter has a first side aligned along the off-orientation direction and a second side aligned along a direction non-parallel to the off-orientation direction. The first side of the outer perimeter of the semiconductor device having a length longer than the second side of the outer perimeter of the semiconductor device.

Abstract: An integrated circuit on a substrate including at least one peripheral portion that surrounds an active area and is realized close to at least one scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in its peripheral portion on different planes starting from the substrate and realizes an integrated antenna for the circuit.

Abstract: The novel photoelectrochemical nano-hybrid film fabricated by blending regioregular polyhexylthiophene (RRPHTh) with titanium oxide (TiO2), Zinc oxide (ZnO) and nanodiamond (ND) nanoparticles on ITO coated glass plate, n-type silicon, and gold coated glass surfaces. The photoelectrochemical study reveals photoinduced electron transfer in nano-hybrid RRPHTh with donor and ND as acceptor providing a molecular approach to high-efficiency photoelectrochemical conversion properties. The ND-RRPHTh has shown promising morphological and photoelectrochemical properties than RRPHTh as well as TiO2-RRPHTh and ZnO-RRPHTh nano-hybrid films.

Abstract: A method of forming spacers and the resulting fin-shaped field effect transistors are provided. Embodiments include forming a silicon (Si) fin over a substrate; forming a polysilicon gate over the Si fin; and forming a spacer on top and side surfaces of the polysilicon gate, and on exposed upper and side surfaces of the Si fin, the spacer including: a first layer and second layer having a first dielectric constant, and a third layer formed between the first and second layers and having a second dielectric constant, wherein the second dielectric constant is lower than the first dielectric constant.

Abstract: A semiconductor device includes a substrate, a first nitride semiconductor layer formed on the substrate, a p-type nitride semiconductor layer formed on the first nitride semiconductor layer, a recess having a bottom portion which reaches the first nitride semiconductor layer through a part of the p-type nitride semiconductor layer, a third nitride semiconductor layer formed to cover the bottom portion of the recess, a side portion of the recess, and a part of an upper surface of the p-type nitride semiconductor layer. The semiconductor device further includes a fourth nitride semiconductor layer formed on the third nitride semiconductor layer, a first electrode formed on another side of the substrate, a gate electrode formed on the upper surface of the p-type nitride semiconductor layer, and a second electrode that is in contact with the third nitride semiconductor layer or the fourth nitride semiconductor layer.

Abstract: A semiconductor-device manufacturing method of the present invention includes a step of selectively implanting impurity ions into a surface of an SiC semiconductor layer and forming impurity regions and a step of activating the impurity ions by annealing the SiC semiconductor layer at a temperature of 1400° C. or more when the surface of the SiC semiconductor layer is covered with an insulating film.

Abstract: The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film.

Abstract: A memory device comprises plural of silicon-containing layers, string select lines (SSLs), strings, bit lines, metal strapped word lines and plural sets of multi-plugs structure. The silicon-containing layers stacked at a substrate. The SSLs are disposed on the silicon-containing layers and extend along a first direction. The strings are perpendicular to the silicon-containing layers and the SSLs and electrically connected to the SSLs. The bit lines are disposed on the SSLs extending along a second direction and electrically connected to the strings. The plural sets of multi-plugs structure are arranged along the first direction, so as to make the strings disposed between two adjacent sets of multi-plugs structure, wherein each set of multi-plugs structure has plural plugs each corresponding to and connected with one of the silicon-containing layers. Each of the metal strapped word lines is connected to the plugs that are connected to the identical silicon-containing layer.

Abstract: In some aspects of the invention, a layer containing titanium and nickel is formed on an SiC substrate. A nickel silicide layer containing titanium carbide can be formed by heating. A carbon layer precipitated is removed by reverse sputtering. Thus, separation of an electrode of a metal layer formed on nickel silicide in a subsequent step is suppressed. The effect of preventing the separation can be further improved when the relation between the amount of precipitated carbon and the amount of carbon in titanium carbide in the surface of nickel silicide from which the carbon layer has not yet been removed satisfies a predetermined condition.

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

Abstract: According to one embodiment, a semiconductor device, includes an element unit including a vertical-type MOSFET, the vertical-type MOSFET in including a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer sequentially stacked in order, an impurity concentration of the second semiconductor layer being lower than the first semiconductor layer, an insulator covering inner surfaces of a plurality of trenches, the adjacent trenches being provided with a first interval in between, and a diode unit including basically with the units of the element unit, the adjacent trenches being provided with a second interval in between, the second interval being larger than the first interval.