Abstract: A wide bandgap semiconductor device with an adjustable voltage level includes a wide bandgap semiconductor power unit and a level adjusting unit. The wide bandgap semiconductor power unit includes a source terminal, to which the level adjusting unit is electrically connected. The level adjusting unit provides a level shift voltage via the source terminal to adjust a driving voltage level of the wide bandgap semiconductor power unit. By adjusting the driving voltage level of the wide bandgap semiconductor power unit using the level adjusting unit, the wide bandgap semiconductor device may serve as a high-voltage enhancement-mode transistor to achieve reduced costs and an increased switching speed.

Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×1017 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.

Abstract: A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.

Abstract: Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer.

Abstract: A semiconductor device includes trench gate structures in a semiconductor body with hexagonal crystal lattice. A mean surface plane of a first surface is tilted to a <1-100> crystal direction by an off-axis angle, wherein an absolute value of the off-axis angle is in a range from 2 degree to 12 degree. The trench gate structures extend oriented along the <1-100> crystal direction. Portions of the semiconductor body between neighboring trench gate structures form transistor mesas. Sidewalls of the transistor mesas deviate from a normal to the mean surface plane by not more than 5 degree.

Abstract: An insulated gate silicon carbide semiconductor device includes: a drift layer of a first conductivity type on a silicon carbide substrate of 4H type with a {0001} plane having an off-angle of more than 0° as a main surface; a first base region; a source region; a trench; a gate insulating film; a protective diffusion layer; and a second base region. The trench sidewall surface in contact with the second base region is a surface having a trench off-angle of more than 0° in a <0001> direction with respect to a plane parallel to the <0001> direction. The insulated gate silicon carbide semiconductor device can relieve an electric field of a gate insulating film and suppress an increase in on-resistance and provide a method for manufacturing the same.

Abstract: Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.

Abstract: A semiconductor device according to embodiments described herein includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, a first region, and a second region. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the first layer. The first region is provided across the first layer and the second layer, includes a first element from F, D, and H, and has a first concentration peak of the first element. The second region is provided in the first layer, includes a second element from Ge, B, Al, Ga, In, Be, Mg, Ca, Sr, Ba, Sc, Y, La, and lanthanoid, and has a second concentration peak of the second element and a third concentration peak of C.

Abstract: Exemplary embodiments of the present invention provide a method of growing a nitride semiconductor layer including growing a gallium nitride-based defect dispersion suppressing layer on a gallium nitride substrate including non-defect regions and a defect region disposed between the non-defect regions, and growing a gallium nitride semiconductor layer on the defect dispersion suppressing layer.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate electrode. The silicon carbide substrate includes a first source region and a second source region, a first body region, a second body region, a first drift region, a second drift region, a third drift region, and a first connection region. The first connection region is provided to include a first intersection and a second intersection, the first intersection being an intersection of a straight line along a first straight-line portion and a straight line along a second straight-line portion, the second intersection being an intersection of a straight line along a third straight-line portion and a straight line along a fourth straight-line portion, and the first connection region has a second conductivity type.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.

Abstract: A semiconductor device manufacturing method according to an embodiment includes: forming an n-type SiC layer on a SiC substrate; forming a p-type impurity region at one side of the SiC layer; exposing other side of the SiC layer by removing at least part of the SiC substrate; implanting carbon (C) ions into exposed part of the SiC layer; performing a heat treatment; forming a first electrode on the p-type impurity region; and forming a second electrode on the exposed part of the SiC layer.

Abstract: A method for manufacturing a semiconductor device, includes: (a) providing a SiC epitaxial substrate in which on a SiC support substrate, a SiC epitaxial growth layer having an impurity concentration equal to or less than 1/10,000 of that of the SiC support substrate and having a thickness of 50 ?m or more is disposed; (b) forming an impurity region, which forms a semiconductor element, on a first main surface of the SiC epitaxial substrate by selectively injecting impurity ions; (c) forming an ion implantation region, which controls warpage of the SiC epitaxial substrate, on a second main surface of the SiC epitaxial substrate by injecting predetermined ions; and (d) heating the SiC epitaxial substrate after (b) and (c).

Abstract: A semiconductor device includes a MISFET having: a diamond substrate; a drift layer having a first layer with a first density for providing a hopping conduction and a second layer with a second density lower than the first density, and having a ? dope structure; a body layer on the drift layer; a source region in an upper portion of the body layer; a gate insulation film on a surface of the body layer; a gate electrode on a surface of the gate insulation film; a first electrode electrically connected to the source region and a channel region; and a second electrode electrically connected to the diamond substrate. The MISFET flows current in the drift layer in a vertical direction, and the current flows between the first electrode and the second electrode.

Abstract: The silicon carbide semiconductor layer includes a first impurity region, a second impurity region, and a third impurity region. Turning to a first position at which an impurity concentration 1/10 as high as a highest impurity concentration is exhibited in a concentration profile of an impurity having the first conductivity type in a direction perpendicular to the main surface in the third impurity region and a second position at which an impurity concentration 1/10 as high as a highest impurity concentration is exhibited in a concentration profile of an impurity having the second conductivity type in the direction perpendicular to the main surface in the second impurity region, a first depth from the main surface to the first position is shallower than a second depth from the main surface to the second position. The electrode is electrically connected to the second impurity region and the third impurity region.

Abstract: Thin film transistors (TFTs), including radiofrequency TFTs, with submicron-scale channel lengths and methods for making the TFTs are provided. The transistors include a trench cut into the layer of semiconductor that makes up the body of the transistors. Trench separates the source and drain regions and determines the channel length of the transistor.

Abstract: A MOSFET includes: a SiC layer including one main surface and provided with a plurality of contact regions; and a plurality of source electrodes formed in contact with the contact regions. In the MOSFET, in a plan view of the one main surface, a plurality of cells including the contact regions and the source electrodes are formed adjacent to one another, each of the plurality of cells having an outer circumferential shape that is a shape of hexagon including a long axis. According to the MOSFET, a contact resistance between each contact region and each source electrode can be further reduced, thereby attaining a more improved electrical property.

Abstract: There is provided a method of manufacturing a semiconductor device, including pre-treating a surface of an insulating film formed on a substrate by supplying a precursor containing a first element and a halogen element to the substrate; and forming a film containing the first element and a second element on the pre-treated surface of the insulating film by performing a cycle a predetermined number of times, the cycle including supplying the precursor to the substrate; and supplying a reactant containing the second element to the substrate, wherein the act of supplying the precursor and the act of supplying the reactant are performed non-simultaneously.

Abstract: An epitaxial wafer comprises a silicon substrate wafer having first and second sides, and a silicon epitaxial layer deposited on the first side, and optionally one or more additional epitaxial layers on top of the silicon epitaxial layer, at least one of the silicon epitaxial layer or at least one of the one or more additional epitaxial layers being doped with nitrogen at a concentration of 1×1016 atoms/cm3 or more and 1×1020 atoms/cm3 or less. The epitaxial wafer is produced by depositing the silicon epitaxial layer and/or at least one of the one or more additional epitaxial layers, at a deposition temperature of 940° C. or less through chemical vapor deposition in the presence of a deposition gas atmosphere containing one or more silicon precursor compounds and one or more nitrogen precursor compounds.

Abstract: There is provided a silicon carbide semiconductor device allowing for integration of a transistor element and a Schottky barrier diode while avoiding reduction of an active region and decrease of a breakdown voltage. A silicon carbide semiconductor device includes a silicon carbide layer. The silicon carbide layer includes: a first region defining an outer circumference portion of an element region in which a transistor element is provided; and a JTE region provided external to the first region in a drift layer and electrically connected to the first region. The first region is provided with at least one opening through which the drift layer is exposed. The silicon carbide semiconductor device further includes a Schottky electrode provided in the opening and forming a Schottky junction with the drift layer.

Abstract: Semiconductor devices that include a semiconductor structure integrated with one or more diamond material layers. A first diamond material layer is formed on a bottom surface and optionally, the side surfaces of the semiconductor structure. In some embodiments, at least a portion of the semiconductor structure is embedded in the diamond. An electrical device can be formed on a top surface of the semiconductor structure. A second diamond material layer can be formed on the top surface of the semiconductor structure. The semiconductor structure can include a III-nitride material such as GaN, which can be embedded within a the first diamond material layer or encased by the first and/or second diamond material layer.

Abstract: A silicon carbide field effect transistor includes a silicon carbide substrate, an n-type drift layer, a p-type epitaxy layer, a source region, a trench gate, at least one p-type doped region, a source, a dielectric layer and a drain. The p-type doped region is disposed at the n-type drift layer to be adjacent to one lateral side of the trench gate, and includes a first doped block and a plurality of second doped blocks arranged at an interval from the first doped block towards the silicon carbide substrate. Further, a thickness of the second doped blocks does not exceed 2 um. Accordingly, not only the issue of limitations posed by the energy of ion implantation is solved, but also an electric field at a bottom and a corner of the trench gate is effectively reduced, thereby enhancing the reliability of the silicon carbide field effect transistor.

Abstract: A semiconductor device according to embodiments includes a p-type SiC layer having a first plane, a gate electrode, and a gate insulating layer provided between the first plane of the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, and a first region. The second layer has a higher oxygen density than the first layer. The first region is provided between the first layer and the second layer and includes a first element, the first element being at least one element in the group of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth).

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer having a first main surface and a second main surface opposite to the first main surface. In the second main surface of the silicon carbide layer, a trench having a depth in a direction from the second main surface toward the first main surface is provided, and the trench has a sidewall portion where a second layer and a third layer are exposed and a bottom portion, where a first layer is exposed. A position of the bottom portion of the trench in a direction of depth of the trench is located on a side of the second main surface relative to a site located closest to the first main surface in a region where the second layer and the first layer are in contact with each other, or located as deep as the site in the direction of depth.

Abstract: A semiconductor device according to the embodiments includes a SiC layer having a first plane, an insulating layer, and a region between the first plane and the insulating layer, the region including at least one element in the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium), a full width at half maximum of a concentration peak of the element being equal to or less than 1 nm, and when a first area density being an area density of Si (silicon) and C (carbon) including a bond which does not bond with any of Si and C in the SiC layer at the first plane and a second area density being an area density of the element, the second area density being equal to or less than ½ of the first area density.

Abstract: A silicon-carbide substrate that includes a doped contact region and a dielectric layer is provided. A protective layer is formed on the dielectric layer. A structured mask is formed on the protective layer. Sections of the protective layer and the dielectric layer that are exposed by openings in the mask are removed. The structured mask is removed. A metal layer is deposited such that a first portion of the metal layer directly contacts the doped contact region and a second portion of the metal layer lines the remaining sections of the protective layer and the dielectric layer. A first rapid thermal anneal process is performed. After performing the first rapid thermal anneal process, the second portion of the metal layer and the remaining section of the protective layer are removed without removing the first portion of the metal layer.

Abstract: A semiconductor device includes a body zone in a semiconductor mesa, which is formed between neighboring control structures that extend from a first surface into a semiconductor body. A drift zone forms a first pn junction with the body zone. In the semiconductor mesa, the drift zone includes a first drift zone section that includes a constricted section of the semiconductor mesa. A minimum horizontal width of the constricted section parallel to the first surface is smaller than a maximum horizontal width of the body zone. An emitter layer between the drift zone and the second surface parallel to the first surface includes at least one first zone of a conductivity type of the drift zone.

Abstract: Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure.

Abstract: A semiconductor substrate of an embodiment includes a SiC layer having a surface inclined in a <11-20> direction plus or minus 5° from a {0001} face at an off angle of 0° to 10°. Area density of threading edge dislocation clusters in the SiC layer is 18.8 cm?2 or less, each of the threading edge dislocation clusters includes a plurality of threading edge dislocations on the surface, the threading edge dislocations included in each of the threading edge dislocation clusters exist in a region that extends in a [1-100] direction plus or minus 5° and has a width of 30 ?m or less, each of the threading edge dislocation clusters includes at least three threading edge dislocations adjacent at an interval of 30 ?m or less, and an interval of adjacent threading edge dislocations in each of the threading edge dislocation clusters is 70 ?m or less.

Abstract: In a front surface of a semiconductor base body, a gate trench is disposed penetrating an n+-type source region and a p-type base region to a second n-type drift region. In the second n-type drift region, a p-type semiconductor region is selectively disposed. Between adjacent gate trenches, a contact trench is disposed penetrating the n+-type source region and the p-type base region, and going through the second n-type drift region to the p-type semiconductor region. A source electrode embedded in the contact trench contacts the p-type semiconductor region at a bottom portion and corner portion of the contact trench, and forms a Schottky junction with the second n-type drift region at a side wall of the contact trench.

Abstract: By using a surface-modified metal oxide particle material obtained by performing surface modification on a metal oxide particle having an average primary particle diameter of 3 nm or more and 10 nm or less with a surface-modifying material having at least a phenyl group and a group capable of undergoing a crosslinking reaction with a functional group in a silicone resin-forming component, the surface-modified metal oxide particle material which has high heat resistance and may further exhibit high transparency and gas barrier properties when used for a sealing material for optical semiconductor light emitting device, or the like is provided and a dispersion liquid, a silicone resin composition and a silicone resin composite each containing the surface-modified metal oxide particle material, as well as an optical semiconductor light emitting device, a light fitting, and a liquid crystal imaging device each using the silicone resin composite, are also provided.

Abstract: A field effect transistor includes a substrate; a first semiconductor layer, disposed over the substrate; a second semiconductor layer, disposed over the first semiconductor layer, wherein an interface between the first semiconductor layer and the second semiconductor layer has a two-dimensional electron gas; a p+ III-V semiconductor layer, disposed over the second semiconductor layer; and a depolarization layer, disposed between the second semiconductor layer and the p+ III-V semiconductor layer, wherein the depolarization layer includes a metal oxide layer.

Abstract: A silicon carbide semiconductor device has a silicon carbide substrate, a gate insulating film, and a gate electrode. Silicon carbide substrate includes a first impurity region having a first conductivity type, a well region being in contact with the first impurity region and having a second conductivity type which is different from the first conductivity type, and a second impurity region separated from the first impurity region by the well region and having the first conductivity type. The gate insulating film is in contact with the first impurity region and the well region. The gate electrode is in contact with the gate insulating film and is arranged opposite to the well region with respect to the gate insulating film. A specific on-resistance at a voltage which is half a gate driving voltage applied to the gate electrode is smaller than twice the specific on-resistance at the gate driving voltage.

Abstract: A silicon carbide semiconductor device includes: a substrate; a drift layer; a current dispersion layer; a base region; a source region; trenches; a gate insulation film; a gate electrode; a source electrode; a drain electrode; and a bottom layer. The current dispersion layer is arranged on the drift layer, and has a first conductive type with an impurity concentration higher than the drift layer. The bottom layer has a second conductive type, is arranged under the base region, covers a bottom of each trench including a corner portion of the bottom of the trench, and has a depth equal to or deeper than the current dispersion layer.

Abstract: A semiconductor device may include a semiconductor layer having a first conductivity type, a well region of a second conductivity type in the semiconductor layer wherein the first and second conductivity types are different, and a terminal region of the first conductivity type in the well region. An epitaxial semiconductor layer may be on the surface of the semiconductor layer including the well region and the terminal region with the epitaxial semiconductor layer having the first conductivity type across the well and terminal regions. A gate electrode may be on the epitaxial semiconductor layer so that the epitaxial semiconductor layer is between the gate electrode and portions of the well region surrounding the terminal region at the surface of the semiconductor layer.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.

Abstract: A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.

Abstract: Methods, systems, and devices are disclosed for implementing high power circuits and semiconductor devices. In one aspect, a method for fabricating a silicon carbide semiconductor device includes forming a thin epitaxial layer of a nitrogen doped SiC material on a SiC epitaxial layer formed on a SiC substrate, and thermally growing an oxide layer to form an insulator material on the nitrogen doped SiC epitaxial layer, in which the thermally grown oxide layer results in at least partially consuming the nitrogen doped SiC epitaxial layer in the oxide layer to produce an interface including nitrogen between the SiC epitaxial layer and the oxide layer.

Abstract: A semiconductor device includes a SiC layer that has a first surface and a second surface, a first electrode in contact with the first surface, a first SiC region of a first conductivity type in the SiC layer, a second SiC region of a second conductivity type in the SiC layer and surrounding a portion of the first SiC region, a third SiC region of the second conductivity type in the SiC layer and surrounding the second SiC region, the third SiC region having an impurity concentration of the second conductivity type lower than that of the second SiC region, and a fourth SiC region of the second conductivity type in the SiC layer between the second SiC region and the third Sic region, the fourth SiC region having an impurity concentration of the second conductivity type higher than that of the second SiC region.

Abstract: A manufacturing method of a semiconductor device includes: forming an electric metal layer by depositing metal as art electrode material on an inside of an opening of an insulating layer on a surface of an SiC semiconductor substrate; widening a gap between an inner wall surface in an opening formed in the insulating layer and the electrode metal layer by etching the insulating layer after the electrode metal layer is formed; and forming an ohmic contact between the electrode metal layer and the SiC semiconductor substrate by heating the SiC semiconductor substrate and the metal electrode layer after the insulating layer is etched.

Abstract: A silicon carbide semiconductor device includes: a vertical MOSFET having: a semiconductor substrate including a high-concentration impurity layer and a drift layer; a base region; a source region; a trench gate structure; a source electrode; and a drain electrode. The base region has a high-concentration base region and a low-concentration base region having a second conductivity type with an impurity concentration lower than the high-concentration base region, which are stacked each other. Each of the high-concentration base region and the low-concentration base region contacts a side surface of the trench.

Abstract: A semiconductor device of an embodiment includes a p-type SiC layer; a SiC region provided on the p-type SiC layer and containing H (hydrogen) or D (deuterium) in an amount of 1×1018 cm?3 or more and 1×1022 cm?3 or less; and a metal layer provided on the SiC region.

Abstract: A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.

Abstract: A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.

Abstract: A semiconductor device is produced by: creating an opening in a mask formed on a semiconductor body; creating, underneath the opening, a trench in the semiconductor body which has a side wall and a trench bottom; creating, while the mask is on the semiconductor body, an insulating layer covering the trench bottom and the side wall; depositing a spacer layer including a first electrode material on the insulating layer; removing the spacer layer from at least a portion of the insulating layer that covers the trench bottom; filling at least a portion of the trench with an insulating material; removing the part of the insulating material laterally confined by the spacer layer so as to leave an insulating block in the trench; and filling at least a portion of the trench with a second electrode material so as to form an electrode within the trench.

Abstract: Methods, systems, and devices are disclosed for implementing high power circuits and semiconductor devices. In one aspect, a method for fabricating a silicon carbide semiconductor device includes forming a thin epitaxial layer of a nitrogen doped SiC material on a SiC epitaxial layer formed on a SiC substrate, and thermally growing an oxide layer to form an insulator material on the nitrogen doped SiC epitaxial layer, in which the thermally grown oxide layer results in at least partially consuming the nitrogen doped SiC epitaxial layer in the oxide layer to produce an interface including nitrogen between the SiC epitaxial layer and the oxide layer.

Abstract: A white LED includes a P-type layer, a tunneling structure, an N-type layer, an N-type electrode, and a P-type electrode. The tunneling structure is in contact with the P-type layer. The tunneling structure is a stack structure comprising a first barrier layer, a first active layer and a second barrier layer. At least one of the first barrier layer, the first active layer and the second barrier layer is a first metal nitride oxide layer. The N-type layer is in contact with the tunneling structure. The N-type electrode is in contact with the N-type layer. The P-type electrode is in contact with the P-type layer.

Abstract: Methods are provided to fabricate semiconductor devices, e.g., FinFET devices, having fin channel structures formed of silicon-germanium alloy layers with uniform thickness. For example, a method includes forming a semiconductor fin structure having sidewalls that define a first width of the semiconductor fins structure, and a hard mask layer disposed on a top surface of the semiconductor fin structure. Portions of the sidewalls are etched to form recessed sidewalls that define a thinned portion, wherein a distance between the recessed sidewalls defines a second width of the thinned portion of the semiconductor fin structure, which is less than the first width. Facetted semiconductor alloy layers are formed on the recessed sidewalls, and then anisotropically etched using the hard mask layer as an etch mask to form planarized semiconductor alloy layers of uniform thickness on the recessed sidewalls of the thinned portion of the semiconductor fin structure.

Abstract: Inverters and methods of manufacture thereof are disclosed. In some embodiments, an inverter includes a substrate and a first tunnel FET (TFET) disposed over the substrate. The first TFET is a first fin field effect transistor (FinFET). A second TFET is over the first TFET. The second TFET is a second FinFET. A junction isolation region is disposed between a source of the first TFET and a source of the second TFET.

Abstract: A method and system of forming large-diameter SiC single crystals suitable for fabricating high crystal quality SiC substrates of 100, 125, 150 and 200 mm in diameter are described. The SiC single crystals are grown by a seeded sublimation technique in the presence of a shallow radial temperature gradient. During SiC sublimation growth, a flux of SiC bearing vapors filtered from carbon particulates is substantially restricted to a central area of the surface of the seed crystal by a separation plate disposed between the seed crystal and a source of the SiC bearing vapors. The separation plate includes a first, substantially vapor-permeable part surrounded by a second, substantially non vapor-permeable part. The grown crystals have a flat or slightly convex growth interface. Large-diameter SiC wafers fabricated from the grown crystals exhibit low lattice curvature and low densities of crystal defects, such as stacking faults, inclusions, micropipes and dislocations.