Abstract: A power semiconductor device has a semiconductor body coupled to first and second load terminal structures, the semiconductor body configured to conduct a load current during a conducting state of the device and having a drift region. The power semiconductor device includes a plurality of cells, each cell having: a first mesa in a first cell portion, the first mesa including: a first port region, and a first channel region, the first mesa exhibiting a total extension of less than 100 nm in a lateral direction, and a second mesa in a second cell portion including: a second port region, and a second channel region. A trench structure includes a control electrode structure configured to control the load current by inversion or accumulation. A guidance zone of the second conductivity type is below the second channel region and is displaced from the first and the second channel regions.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In n?-type drift layer, an n-type region, a lower second p+-type region and a first p+-type region are provided. A part of the lower second p+-type region extending in a direction opposite that of a depth of the trench and connected to the p-type base layer.

Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.

Abstract: The present disclosure relates to a power module and a manufacturing method thereof. The power module includes: a group of switch elements, a molding part and a connector. The group of switch elements includes at least one pair of switch elements. The molding part molds the group of switch elements. The connector includes a signal terminal and a power terminal respectively electrically connected to the signal end and power end of the group of switch elements, and both fanned out from the molding part. The power terminal includes a positive power terminal, a negative power terminal and an output power terminal. The positive power terminal and the negative power terminal are respectively a first metal layer and a second metal layer which are at least partially stacked, and an insulating layer is disposed between the first metal layer and the second metal layer.

Abstract: According to one embodiment, a power generation element includes a first conductive layer, a second conductive layer, a first member provided between the first conductive layer and the second conductive layer, and a second member separated from the first member and provided between the first member and the second conductive layer. The first member includes a first region including Alx1Ga1-x1N (0?x1<1), and a second region including Alx2Ga1-x2N (x1<x2?1) and being provided between the first region and the second member. A <000-1> direction of the first member has a component in an orientation from the first conductive layer toward the second conductive layer.

Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.

Abstract: A SiC epitaxial wafer includes: a substrate having an off angle of less than 4 degrees; and a SiC epitaxial growth layer disposed on the substrate having the off angle of less than 4 degrees, wherein an Si compound is used for a supply source of Si, and a C compound is used as a supply source of C, for the SiC epitaxial growth layer, wherein the uniformity of carrier density is less than 10%, and the defect density is less than 1 count/cm2; and a C/Si ratio of the Si compound and the C (carbon) compound is within a range of 0.7 to 0.95. There is provide a high-quality SiC epitaxial wafer excellent in film thickness uniformity and uniformity of carrier density, having the small number of surface defects, and capable of reducing costs, also in low-off angle SiC substrates on SiC epitaxial growth.

Abstract: Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments, formation of a CEM switch may comprise depositing metal layers, such layers of a transition metal, over a conductive substrate. Dopant layers may subsequently be deposited on the layers of the transition metal, followed by annealing of the layers of transition metal and dopant layers. Responsive to annealing, dopant from the dopant layers may diffuse into the one or more layers of transition metal, thereby forming a CEM.

Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having first and second planes; first and second trenches extending in a first direction; first and second gate electrodes; a first silicon carbide region of a first conductivity type; a plurality of second silicon carbide regions of a second conductivity type between the first silicon carbide region and the first plane, located between the first trench and the second trench, and separated from each other in the first direction; a fourth silicon carbide region of the second conductivity type between two of the second silicon carbide regions and contacting the second silicon carbide region; a fifth silicon carbide region of the second conductivity type between the two second silicon carbide regions and contacting the second silicon carbide region; a first electrode contacting the first silicon carbide region; and a second electrode.

Abstract: A SiC epitaxial wafer having a SiC epitaxial layer formed on a SiC single crystal substrate having an offset angle of 4 degrees or less in a<11-20>direction from a (0001) plane. A trapezoidal defect included in the SiC epitaxial wafer includes an inverted trapezoidal defect in which a length of a lower base on a downstream side of a step flow is equal to or less than a length of an upper base on an upstream side of the step flow. Also disclosed is a method for manufacturing the SiC epitaxial wafer.

Abstract: Embodiments described herein include systems and techniques for converting (i.e., transducing) a quantum-level (e.g., single photon) signal between the three wave forms (i.e., optical, acoustic, and microwave). A suspended crystalline structure is used at the nanometer scale to accomplish the desired behavior of the system as described in detail herein. Transducers that use a common acoustic intermediary transform optical signals to acoustic signals and vice versa as well as microwave signals to acoustic signals and vice versa. Other embodiments described herein include systems and techniques for storing a qubit in phonon memory having an extended coherence time. A suspended crystalline structure with specific geometric design is used at the nanometer scale to accomplish the desired behavior of the system.

Abstract: Embodiments described herein include systems and techniques for converting (i.e., transducing) a quantum-level (e.g., single photon) signal between the three wave forms (i.e., optical, acoustic, and microwave). A suspended crystalline structure is used at the nanometer scale to accomplish the desired behavior of the system as described in detail herein. Transducers that use a common acoustic intermediary transform optical signals to acoustic signals and vice versa as well as microwave signals to acoustic signals and vice versa. Other embodiments described herein include systems and techniques for storing a qubit in phonon memory having an extended coherence time. A suspended crystalline structure with specific geometric design is used at the nanometer scale to accomplish the desired behavior of the system.

Abstract: A semiconductor device includes a first semiconductor module and a second semiconductor module. The first semiconductor module configures an upper arm, and includes first semiconductor elements connected in parallel to each other, a sealing resin body, and a positive electrode terminal. The second semiconductor module configures a lower arm, and includes second semiconductor elements connected in parallel to each other, a sealing resin body, and a negative electrode terminal. The first and second semiconductor modules are aligned in an alignment direction. At least one of the first and second semiconductor modules has a relay terminal for electrically relaying electrodes on a low potential side of the first semiconductor elements and electrodes on a high potential side of the second semiconductor elements.

Abstract: According to one embodiment, a semiconductor device includes first, second, and third semiconductor regions, first, second, and third electrodes, and a first insulating portion. The first semiconductor region includes first and second partial regions. A first direction from the second partial region toward the second semiconductor region crosses a second direction from the second region toward the first partial region. The third semiconductor region is provided between the second partial region and the second semiconductor region in the first direction. The first insulating portion includes a first insulating region provided between the third semiconductor region and the first electrode in the second direction, a second insulating region provided between the first partial region and the first electrode in the first direction, and a third insulating region provided between the first partial region and the first insulating region in the first direction.

Abstract: Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.

Abstract: Semiconductor devices include a plurality of gate fingers extending on a wide bandgap semiconductor layer structure. An inter-metal dielectric pattern is formed on the gate fingers, the inter-metal dielectric pattern including a plurality of dielectric fingers that cover the respective gate fingers. A top-side metallization is provided on the inter-metal dielectric pattern and on exposed portions of the upper surface of the wide bandgap semiconductor layer structure. The top-side metallization includes a first conductive diffusion barrier layer on the inter-metal dielectric pattern and on the exposed portions of the upper surface of the wide bandgap semiconductor layer structure, a conductive contact layer on an upper surface of the first conductive diffusion barrier layer, and a grain stop layer buried within the conductive contact layer.

Abstract: A method of measuring a SiC ingot includes a measuring step of measuring a curving direction of an atomic arrangement plane of a SiC single crystal at least along a first direction passing through a center in plan view and a second direction intersecting with the first direction to obtain a shape of the atomic arrangement plane; and a crystal growth step of performing crystal growth using the SiC single crystal as a seed crystal, in which in a case where the shape of the atomic arrangement plane measured in the measuring step is a saddle type, a crystal growth condition in the crystal growth step is set such that a convexity of a second growth front at the end of crystal growth becomes larger than a convexity of a first growth front when an amount of crystal growth in the center of the seed crystal is 7 mm.

Abstract: A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.

Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.

Abstract: In a vertical MOSFET of a trench gate structure, a high-concentration implantation region is provided in a p-type base region formed from a p-type silicon carbide layer formed by epitaxial growth, so as to include a portion in which a channel is formed. The high-concentration implantation region is formed by ion implantation of a p-type impurity into the p-type silicon carbide layer. The high-concentration implantation region is formed by p-type ion implantation and has an impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration that is higher than that of the p-type silicon carbide layer. In the p-type base region, disorder occurs partially in the crystal structure consequent to the ion implantation for forming the high-concentration implantation region.

Abstract: Assuming that one or more defects satisfying relations of Formula 1 and Formula 2 are first defects, and one or more defects satisfying relations of Formula 3 and Formula 2 are second defects, where an off angle is ?°, the thickness of a silicon carbide layer in a direction perpendicular to a second main surface is W ?m, the width of each of the one or more defects in a direction obtained by projecting a direction parallel to an off direction onto the second main surface is L ?m, and the width of each of the one or more defects in a direction perpendicular to the off direction and parallel to the second main surface is Y ?m, a value obtained by dividing the number of the second defects by the sum of the number of the first defects and the number of the second defects is greater than 0.5.

Abstract: The present invention includes: a plurality of semiconductor modules on a metal base (conductor base); a first insulating bus bar and a second insulating bus bar connecting the semiconductor modules; a box-like insulating resin frame around the semiconductor modules; a first insulating layer that seals the semiconductor modules, the first insulating layer having an upper surface at a position that is lower than upper ends of terminals extending from an insulating circuit substrate of the semiconductor module inside the insulating resin frame; and second insulating layers on the first insulating layer inside the insulating resin frame, the upper ends of the terminals being buried inside the second insulating layers. Interfaces formed by the first insulating layer, second insulating layers, and sidewall parts (third insulating layer) of the insulating resin frame are arranged between the terminals and ground positions formed at the lower ends of the sidewall parts.

Abstract: The present technology relates to diamond materials and structures created using chemical vapor deposition techniques (i.e., creation of synthetic diamond). The chemical vapor deposited diamond includes a multiphase material comprising (a) a single crystalline matrix phase and (b) plurality of diamond grains, each of the plurality of diamond grains being crystallographically distinct from the single crystalline matrix phase.

Abstract: In a transistor region of an active region, trench-gate MOS gates for a vertical MOSFET are formed on the front surface side of a semiconductor substrate. In a non-effective/pad region of the active region, a gate pad is formed on the front surface of the semiconductor substrate with an interlayer insulating film interposed therebetween. An n-type region is formed spanning across the entire non-effective region in the surface layer of the front surface of the semiconductor substrate. The portion directly beneath the gate pad is only an n-type region constituted by an n+ starting substrate, an n? drift region, and the n-type region, with the interlayer insulating film sandwiched thereabove. No n+ source region is formed in a p-type base region extension which is the portion of a p-type base region that extends into the non-effective region.

Abstract: Methods of manufacturing FinFETs including providing a precursor FinFET structure having a substrate with fins thereon, S/D junctions on fin tops, an STI layer on the substrate and between fins, a conformal first dielectric layer on the STI layer and S/D junctions, and a second dielectric layer on the first dielectric layer; forming a conformal third dielectric layer on the second dielectric layer and surfaces of the first dielectric layer located above the second dielectric layer; forming a fourth dielectric layer on the third dielectric layer such that third dielectric layer located between adjacent fins is exposed and such that third dielectric layer located above the adjacent fins is exposed; removing the exposed third dielectric layer and the first dielectric layer located thereunder, thereby exposing the S/D junctions; and forming a metal contact on the exposed S/D junctions and the exposed portion of the third dielectric layer between adjacent fins.

Abstract: It is assumed that a defect satisfying relations of Formula 1 and Formula 2 is a first defect, where an off angle is ?. It is assumed that a defect having an elongated shape when viewed in a direction perpendicular to the second main surface, and satisfying relations of Formula 3 and Formula 4 is a second defect. A value obtained by dividing the number of the second defect by the sum of the number of the first defect and the number of the second defect is greater than 0.5.

Abstract: The present application discloses a semiconductor device and a method for forming a p-type conductive channel in a diamond using an abrupt heterojunction, which pertain to the technical field of fabrication of semiconductor devices. The method includes: forming a diamond layer on a substrate; forming one or multiple layers of a heterogeneous elementary substance or compound having an acceptor characteristic on an upper surface of the diamond layer; forming a heterojunction at an interface between the diamond layer and an acceptor layer; forming two-dimensional hole gas at one side of the diamond layer with a distance of 10 nm-20 nm away from the heterojunction; and using the two-dimensional hole gas as a p-type conductive channel. The method enables a concentration and a mobility of carriers to maintain stable at a temperature range of 0° C.-1000° C., thereby realizing normal operation of the diamond device at high temperature environment.

Abstract: The present invention relates to a UV-radiation sensor with a radiation-sensitive region of diamond, which is formed on the first face of a semiconductor substrate and with which electrical contact can be made via at least two contact electrodes. In the proposed UV-radiation sensor, the radiation-sensitive region has two differently doped regions of diamond that form a pn-junction for purposes of radiation detection. Such a UV-radiation sensor has a high sensitivity in the wavelength range ?200 nm.

Abstract: Many of the physical properties of a silicon semiconductor have already been understood, whereas many of the physical properties of an oxide semiconductor have been still unclear. In particular, an adverse effect of an impurity on an oxide semiconductor has been still unclear. In view of the above, a structure is disclosed in which an impurity that influences electrical characteristics of a semiconductor device including an oxide semiconductor layer is prevented or is eliminated. A semiconductor device which includes a gate electrode, an oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer and in which the nitrogen concentration in the oxide semiconductor layer is 1×1020 atoms/cm3 or less is provided.

Abstract: To improve reliability of a semiconductor device, in a method of manufacturing the semiconductor device, a ground plane region of an n-type MISFET is formed by ion-implanting a p-type impurity and nitrogen (N) and a ground plane region of a p-type MISFET is formed by ion-implanting an n-type impurity and one of carbon (C) and fluorine (F).

Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.

Abstract: To improve a TCT characteristic of a circuit substrate. The circuit substrate comprises a ceramic substrate including a first and second surfaces, and first and second metal plates respectively bonded to the first and second surfaces via first and second bonding layers. A three-point bending strength of the ceramic substrate is 500 MPa or more. At least one of L1/H1 of a first protruding portion of the first bonding layer and L2/H2 of a second protruding portion of the second bonding layer is 0.5 or more and 3.0 or less. At least one of an average value of first Vickers hardnesses of 10 places of the first protruding portion and an average value of second Vickers hardnesses of 10 places of the second protruding portion is 250 or less.

Abstract: A semiconductor device is described. The semiconductor device includes a dielectric layer oriented substantially parallelly to a substrate. The semiconductor device includes a metal layer formed on top of the dielectric layer. The semiconductor device includes a fin extending substantially orthogonally from the substrate through the dielectric layer into the metal layer. The semiconductor device includes a gate insulator deposited on top of the fins and the dielectric layer. The semiconductor device includes an optical projection lithography (OPL) material deposited on a portion of a surface area of the device to form a first covered surface area and a first exposed surface area. The semiconductor device includes a first exposed gate insulator area formed by removing the metal layer under the first exposed surface area. The semiconductor device includes a first exposed fin area formed by removing the gate insulator from the first exposed gate insulator area.

Abstract: An integrated circuit is provided including a first substrate with a first thermal conductivity. An active layer is deposited on the first substrate. At least one native device is fabricated on the active layer. A window is formed in the active layer, which exposes a portion of the first substrate. A non-native device is fabricated on a second substrate with a second thermal conductivity lower than the first thermal conductivity. The non-native device is flip-chip mounted in the widow on the first substrate and electrically connected to the at least one native device. The non-native device is also thermally connected to the first substrate such that heat generated by the non-native device is removed through the first substrate.

Abstract: The present invention relates to a method for manufacturing a nitrogen-face polarity gallium nitride epitaxial structure, which includes: providing a gallium nitride template which includes a substrate and a first nitrogen-face polarity gallium nitride layer positioned on the substrate; re-growing the gallium nitride on a surface of the first nitrogen-face polarity gallium nitride layer to form a second nitrogen-face polarity gallium nitride layer; and sequentially growing a barrier layer and a channel layer on the second nitrogen-face polarity gallium nitride layer. The method for manufacturing the nitrogen-face polarity gallium nitride epitaxial structure provided by the present application enables a simple growth of the nitrogen-face polarity gallium nitride, can effectively eliminate the radio frequency dispersion phenomenon, and is beneficial to large-scale production and utilization of the nitrogen-face polarity gallium nitride epitaxial structure.

Abstract: A silicon carbide epitaxial substrate includes a silicon carbide single-crystal substrate of one conductivity type, a first silicon carbide layer of the above-mentioned one conductivity type, a second silicon carbide layer of the above-mentioned one conductivity type, and a third silicon carbide layer of the above-mentioned one conductivity type. The silicon carbide single-crystal substrate has first impurity concentration. The first silicon carbide layer is provided on the silicon carbide single-crystal substrate, and has second impurity concentration that is lower than the first impurity concentration. The second silicon carbide layer is provided on the first silicon carbide layer, and has third impurity concentration that is higher than the first impurity concentration. The third silicon carbide layer is provided on the second silicon carbide layer, and has fourth impurity concentration that is lower than the second impurity concentration.

Abstract: A silicon nitride film having a thickness in a range from 1 [nm] to 3 [nm] is deposited on a front surface of a silicon carbide semiconductor base, by an ALD method. Next, on the silicon nitride film, for example, a silicon oxide film having a thickness in a range from 20 [nm] to 100 [nm] is deposited. After deposition of the silicon oxide film, for example, heat treatment is performed at a temperature in a range from 1100 degrees C. to 1350 degrees C., in a gas atmosphere that includes oxygen. By this heat treatment, nitrogen surface density of an interface of the silicon carbide semiconductor base and the silicon oxide film (gate insulating film) is increased, reducing interface state density of the interface of the silicon carbide semiconductor base and the silicon nitride film.

Abstract: An epitaxial substrate for semiconductor elements suppresses leakage current and has a high breakdown voltage. The epitaxial substrate for semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN doped with Zn; a buffer layer formed of a group 13 nitride adjacent to the free-standing substrate; a channel layer formed of a group 13 nitride adjacent to the buffer layer; and a barrier layer formed of a group 13 nitride on an opposite side of the buffer layer with the channel layer therebetween, wherein part of a first region consisting of the free-standing substrate and the buffer layer is a second region containing Si at a concentration of 1×1017cm?3 or more, and a minimum value of a concentration of Zn in the second region is 1×1017cm?3.

Abstract: An AlGaN template including a substrate and an Al1-xGaxN crystallization thin film deposited on the substrate, where 0<x<1. A method for preparing the AlGaN template includes providing a substrate; and depositing an Al1-xGaxN crystallization thin film on the substrate.

Abstract: A method for producing an organic EL device having an anode, a cathode, at least one organic functional layer disposed between the anode and the cathode, and a sealing layer, comprising a step of forming the anode, a step of forming the cathode, a step of forming the at least one organic functional layer and a step of forming the sealing layer, wherein the average concentration: A (ppm) of ammonia to which the organic EL device during production is exposed from initiation time of the step of forming the at least one organic functional layer until termination time of the step of forming the sealing layer and the exposure time thereof: B (sec) satisfy the formula (1-1): 0?A×B?105??(1-1).

Abstract: A semiconductor device of an embodiment includes a silicon carbide layer having a first and a second plane, a trench, a gate electrode in the trench, an n-type first silicon carbide region, a p-type second silicon carbide region and a p-type third silicon carbide region provided between the first silicon carbide region and the first plane and interposing the trench therebetween, a p-type sixth silicon carbide region between the first silicon carbide region and the second silicon carbide region, a p-type seventh silicon carbide region between the first silicon carbide region and the third silicon carbide region, an eighth silicon carbide region between the first silicon carbide region and the sixth silicon carbide region, and a ninth silicon carbide region between the first silicon carbide region and the seventh silicon carbide region. The eighth silicon carbide region has a plurality of first regions extending toward the ninth silicon carbide region.

Abstract: Provided are graphene-based nanopore and nanostructure devices, which devices may include an insulating layer disposed atop the graphene, which can be in a planar shape or nanostructured into a ribbon or other shapes, containing a single graphene layer or several layers. Graphene layers and nanostructures can be placed nearby horizontally or stacked vertically. Also provided are related methods of fabricating and processing such devices and also methods of using such devices in macromolecular analysis.

Abstract: A silicon carbide semiconductor element includes a silicon carbide semiconductor layer of a first conductivity type, a body region of a second conductivity type, a channel layer made of a silicon carbide semiconductor disposed on the silicon carbide semiconductor layer so as to be in contact with at least a part of the body region, and a gate electrode disposed on the channel layer via a gate insulating film. The channel layer has a multilayer structure of a high-concentration impurity layer containing impurities of the first conductivity type, a first medium-concentration impurity layer containing impurities of the first conductivity type, and a first low-concentration impurity layer containing impurities of the first conductivity type. The first low-concentration impurity layer is disposed closer to the body region than the high-concentration impurity layer and the first medium-concentration impurity layer.

Abstract: A silicon carbide semiconductor element includes n-type silicon carbide epitaxial layers formed on an n+-type silicon carbide semiconductor substrate, plural p base layers selectively formed in surfaces of the silicon carbide epitaxial layers, a p-type silicon carbide epitaxial layer formed in the silicon carbide epitaxial layer, and a trench penetrating at least the silicon carbide epitaxial layer. The silicon carbide semiconductor element also includes, in a portion of the silicon carbide epitaxial layer, a mesa portion exposing the p base layer. The silicon carbide semiconductor element further includes, between consecutive mesa side faces of the mesa portion, a flat portion substantially parallel to the silicon carbide substrate. The remaining thickness of the exposed p base layer is larger than 0.5 ?m and smaller than 1.0 ?m.

Abstract: A substrate is made of gallium-nitride-based material. The n-type layer is disposed on a first surface of the substrate. A p-type layer is disposed on the n-type layer, and constitutes, along with the n-type layer, a semiconductor layer on the first surface of the substrate, the semiconductor layer being provided with a mesa shape having a bottom surface, a side surface, and a top surface. An anode electrode is disposed on the p-type layer. A cathode electrode is disposed on a second surface of the substrate. An insulating film continuously extends over the bottom surface and the top surface to cover the side surface. The top surface is provided with at least one trench. The at least one trench includes a trench filled with the insulating film.

Abstract: A second source portion having an impurity concentration lower than that of a first source portion, both forming a source region, includes a first sub-portion having a depth from a bottom surface of the first source portion down to a second height higher than a first height, and a second sub-portion having an upper surface in contact with a part of a bottom surface of the first sub-portion, one side surface in a second direction perpendicular to a first direction in contact with an outer side surface of the trench, another side surface in the second direction, both side surfaces in the first direction, and a bottom surface in contact with the base layer, and having a depth from a bottom surface of the first sub-portion up to at least the first height.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, a fourth impurity region, a fifth impurity region, and a sixth impurity region. A first main surface of the silicon carbide substrate is provided with a trench defined by a side surface and a bottom portion. The sixth impurity region includes a first region which faces the bottom portion and a second region which faces a second main surface of the silicon carbide substrate. The first region is higher in impurity concentration than the second region. In a direction perpendicular to the second main surface, a fifth main surface of the fourth impurity region is located between a sixth main surface of the second impurity region and the second main surface.

Abstract: A switchable array micro-lattice comprises a plurality of interconnected units wherein the units are formed of graphene tubes. JFET gates are provided in selected members of the micro-lattice. Gate connectors are routed from an external surface of an integrated circuit (IC) through openings in the micro-lattice to permit control of the JFET gates.

Abstract: In a crystal growth apparatus and method, polycrystalline source material and a seed crystal are introduced into a growth ambient comprised of a growth crucible disposed inside of a furnace chamber. In the presence of a first sublimation growth pressure, a single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a first gas that includes a reactive component that reacts with and removes donor and/or acceptor background impurities from the growth ambient during said sublimation growth. Then, in the presence of a second sublimation growth pressure, the single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a second gas that includes dopant vapors, but which does not include the reactive component.