Abstract: A semiconductor device includes a first layer of a first semiconductor material disposed on a semiconductor substrate and a second layer of a second semiconductor material disposed on the first layer. The second semiconductor material is formed of an alloy that includes a first element and a second element. The first semiconductor material and the second semiconductor material are different. A gate structure is disposed on a first portion of the second layer. A surface region of a second portion of the second layer not covered by the gate structure has a higher concentration of the second element than an internal region of the second portion of the second layer, and the surface region surrounds the internal region.

Abstract: In a termination region of a SiC-MOSFET, suppressing operation of a p-n diode between a well and a drift layer sometimes decreases reliability during high-speed switching. In a termination region of a SiC-MOSFET with a built-in SBD are provided second well region having an impurity concentration lower than the impurity concentration in a well region in an active region, and a high-concentration region that is formed on a surface layer of the second well region, has an impurity concentration higher than the impurity concentration in the well region in the active region, and is ohmic-connected to a source electrode.

Abstract: A method of forming a photovoltaic device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands.

Abstract: A semiconductor device includes a semiconductor layer on a first electrode. The semiconductor layer includes a first region of a first type, a second region of a second type, a third region of the second type, and a fourth region of the first type. The second region is above the first region. The third region surrounds the second region. The fourth region surrounds the third region. The second electrode includes a first portion above the second region and a second portion surrounding the first portion. The third electrode surrounds the second electrode and is electrically connected to the fourth region. The semi-insulating layer is electrically connected to the second electrode and the third electrode. A first end portion of the first insulating layer is above the third region.

Abstract: A present invention includes the following: a third impurity region having a second conductivity type and disposed in an outer peripheral region that is the outer periphery of a cell arrangement region in which a unit cell is disposed; a field insulating film disposed in the outer peripheral region; an interlayer insulating film; a first main electrode disposed on the interlayer insulating film. The third impurity region includes a fourth impurity region having the second conductivity type, having a higher impurity concentration than the third impurity region. A gate wire and a gate pad are disposed in the outer peripheral region. The fourth impurity region is adjacent to the cell arrangement region, surrounds at least a region below the gate pad, and is electrically connected to the first main electrode.

Abstract: A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. In a direction parallel to a central region, a ratio of a standard deviation of a carrier concentration of the silicon carbide layer to an average value of the carrier concentration of the silicon carbide layer is less than 5%. The average value of the carrier concentration is more than or equal to 1×1014 cm?3 and less than or equal to 5×1016 cm?3. In the direction parallel to the central region, a ratio of a standard deviation of a thickness of the silicon carbide layer to an average value of the thickness of the silicon carbide layer is less than 5%. The central region has an arithmetic mean roughness (Sa) of less than or equal to 1 nm. The central region has a haze of less than or equal to 50.

Abstract: A semiconductor device based on SiC-MOSFET realizes high voltage endurance, high current, low breakover voltage, low switching loss and low noise. The SiC-MOSFET is a combination of a Si-MOSFET with high channel mobility and a drift layer formed by SiC with high bulk mobility, so that the first conductive SiC wafer forming the drift layer joins the second conductive Si wafer, excavates out a trench gate in part of the SiC to make the MOSFET, and a second conductive barrier layer is arranged in the Si region adjacent to the SiC.

Abstract: A gate connection layer (14) includes a portion placed on an outer trench (TO) with a gate insulating film (7) being interposed. A first main electrode (10) includes a main contact (CS) electrically connected to a well region (4) and a first impurity region (5) within an active region (30), and an outer contact (CO) being spaced away from the active region (30) and in contact with a bottom face of the outer trench (TO). A trench-bottom field relaxing region (13) is provided in a drift layer (3). A trench-bottom high-concentration region (18) has an impurity concentration higher than that of the trench-bottom field relaxing region (13), is provided on the trench-bottom field relaxing region (13), and extends from a position where it faces the gate connection layer (14) with the gate insulating film (7) being interposed, to a position where it is in contact with the outer contact (CO) of the first main electrode (10).

Abstract: An embodiment relates to a device comprising a unit cell on a SiC substrate, the unit cell comprising a gate insulator film, a trench in the well region, and a first sinker region of a second conduction type, wherein the first sinker region has a depth that is equal to or greater than a depth of a well region; wherein the device has an on-resistance of less than 3 milliohm-cm2, a gate threshold voltage of greater than 2.8V, a breakdown voltage of greater than 1450V, and an electric field of less than 3.5 megavolt/cm in the gate insulator film at a drain voltage of less than or equal to 1200 V.

Abstract: Semiconductor devices and methods of forming the same include partially etching sacrificial layers in a first stack of alternating sacrificial layers and channel layers to form first recesses. A first inner spacer sub-layer is formed in the first recesses from a first dielectric material. A second inner spacer sub-layer is formed in the first recesses from a second dielectric material, different from the first dielectric material. The sacrificial layers are etched away. The first inner spacer sub-layer is etched away. A gate stack is formed on and around the channel layers and in contact with the second inner spacer sub-layer.

Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a semiconductor substrate, a first fin and a second fin extending from the semiconductor substrate, a first lower semiconductor feature directly over the first fin, and a second lower semiconductor feature directly over the second fin. Each of the first and second lower semiconductor features includes a top surface bending downward towards the semiconductor substrate. The semiconductor also further includes an upper semiconductor feature directly over and in physical contact with the first and second lower semiconductor features. The semiconductor device further includes a dielectric layer on sidewalls of the first and second lower semiconductor features.

Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.

Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.

Abstract: A silicon carbide semiconductor device includes a first doped region including a plurality of first leg portions, a plurality of body portions, and a plurality of first arm portions. The first leg portions are extending along a second direction, the body portions connect at least two of the first leg portions, and the first arm portions are extending along a first direction and connecting at least two of the first leg portions. A second doped region includes a plurality of second leg portions, a plurality of source portions, and a plurality of second arm portions. The second leg portions are extending along the second direction, the source portions are arranged in the body portions and connecting at least two of the second leg portions, and the second arm portions are extending along the first direction and connecting at least two of the second leg portions.

Abstract: A semiconductor element bonding body including: a substrate, in which a concave portion is formed; and a semiconductor element placed in the concave portion to be mounted to the substrate. A portion of the substrate in which the concave portion is formed is made of Cu. The concave portion has a perimeter portion in which a level difference is formed, and the level difference has a height d of 20 ?m or more and less than 50 ?m. The concave portion has a bottom surface having a flatness degree of ?/8.7 ?m or more and ?/1.2 ?m or less when a wavelength ? of a laser is 632.8 nm. A metal film is formed on the semiconductor element, and the bottom surface of the concave portion and the metal film are bonded directly to each other.

Abstract: A method for manufacturing a semiconductor device includes: forming an ohmic electrode including Al on a semiconductor substrate; forming a SiN film covering the ohmic electrode; forming a first photoresist on the SiN film, the first photoresist having an opening pattern overlapping the ohmic electrode; performing ultraviolet curing of the first photoresist; forming an opening in the SiN film exposed through the opening pattern and causing a surface of the ohmic electrode to be exposed inside the opening; forming a barrier metal layer on the first photoresist and on the ohmic electrode exposed through the opening; forming a second photoresist in the opening pattern; performing a heat treatment on the second photoresist and covering the barrier metal layer overlapping the opening with the second photoresist; and etching the barrier metal layer using the second photoresist.

Abstract: A fin field effect transistor is provided. The FinFET device includes a base substrate; an isolation layer on the base substrate; first fins in the isolation layer and on the base substrate. The first fins is made of a material having a thermal conductivity greater than a material of the base substrate.

Abstract: A semiconductor device may include a plurality of active patterns and a plurality of gate structure on a substrate, a first insulating interlayer covering the active patterns and the gate structures, a plurality of first contact plugs extending through the first insulating interlayer, a plurality of second contact plugs extending through the first insulating interlayer, and a first connecting pattern directly contacting a sidewall of at least one contact plug selected from the first and second contact plugs. Each of gate structures may include a gate insulation layer, a gate electrode and a capping pattern. Each of first contact plugs may contact the active patterns adjacent to the gate structure. Each of the second contact plugs may contact the gate electrode in the gate structures. An upper surface of the first connecting pattern may be substantially coplanar with upper surfaces of the first and second contact plugs.

Abstract: A phosphor comprises a crystal phase that has a chemical composition of (Y1-x-y,Cex,Lay)?Si?-zAlzN?O, where the ? satisfies 5.5???6.5, the ? satisfies 9.5???12.5, the ? satisfies 17.5???22.5, the x satisfies 0<x?0.1, the y satisfies 0?y?0.4, and the z satisfies 0?z?0.5. A light emission spectrum of the phosphor includes a peak within a wavelength range of not less than 600 nm and not more than 660 nm.

Abstract: A silicon carbide epitaxial substrate has a silicon carbide single-crystal substrate and a silicon carbide layer. An average value of carrier concentration in the silicon carbide layer is not less than 1×1015 cm?3 and not more than 5×1016 cm?3. In-plane uniformity of the carrier concentration is not more than 2%. The second main surface has: a groove 80 extending in one direction along the second main surface, a width of the groove in the one direction being twice or more as large as a width thereof in a direction perpendicular to the one direction, and a maximum depth of the groove from the second main surface being not more than 10 nm; and a carrot defect. A value obtained by dividing a number of the carrot defects by a number of the grooves is not more than 1/500.

Abstract: A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm.

Abstract: A silicon carbide single crystal substrate includes a first main surface and an orientation flat. The orientation flat extends in a <11-20> direction. The first main surface includes an end region extending by at most 5 mm from an outer periphery of the first main surface. In a direction perpendicular to the first main surface, an amount of warpage of the end region continuous to the orientation flat is not greater than 3 ?m.

Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce a breakdown voltage. In the SiC-MOSFET with the built-in Schottky diode, a conductive layer in Schottky connection with the second well region is provided on the second well region in the terminal part, and the conductive layer is electrically connected with a source electrode of the MOSFET. A conductive layer contact hole is provided for connecting only the conductive layer and the source electrode.

Abstract: A Schottky diode device includes a substrate having a first conductivity type, a first well region having a second conductivity type disposed in the substrate, and a first doped region having the second conductivity type in the first well region, wherein the first doped region includes a first portion and a second portion, and the first portion and the second portion have different doping concentrations. The first portion includes a region having at least four sides, from a top-view perspective, abutting the second portion.

Abstract: Provided is an SiC substrate evaluation that includes irradiating a first surface of an SiC substrate which is cut out from an SiC ingot with excitation light before an epitaxial film is laminated on the first surface to perform photoluminescence measurement.

Abstract: A light emitting element has first and second electrodes. In plan view, the first electrode has a first connecting portion, a first extending portion, and two second extending portions. The second electrode has a second connecting portion, and two third extending portions. The first extending portion extends linearly toward the second connecting portion, and the second extending portions are arranged on two sides of the first extending portion. The second extending portions each has two bent portions and a linear portion extending parallel to the first extending portion and disposed between the two bent portions. The third extending portions extend parallel to the first extending portion between the first extending portion and the second extending portions. The second extending portions extend beyond the second connecting portion. The first and second connecting portions are symmetrically arranged with respect to a virtual line parallel to one side of the light emitting element.

Abstract: A semiconductor structure is provided and includes a substrate; a gate dielectric layer on the substrate; a dielectric barrier layer structure on the gate dielectric layer; a work function layer on the dielectric barrier layer structure; a gate barrier layer structure on the work function layer; and a gate electrode layer on the gate barrier layer structure. The dielectric barrier layer structure is doped with silicon and the gate barrier layer structure is doped with silicon.

Abstract: A method of yielding a thinner product wafer from a thicker base SiC wafer cut from a SiC ingot includes: supporting the base SiC wafer with a support substrate: and while the base SiC wafer is supported by the support substrate, cutting through the base SiC wafer in a direction parallel to a first main surface of the base SiC wafer using a wire as part of a wire electrical discharge machining (WEDM) process, to separate the product wafer from the base SiC wafer, the product wafer being attached to the support substrate when cut from the base SiC wafer.

Abstract: A semiconductor device includes trench gate structures that extend from a first surface into a semiconductor body of silicon carbide. The trench gate structures include a gate electrode and are spaced apart from one another along a first horizontal direction and extend into a body region with a longitudinal axis parallel to the first horizontal direction. First sections of first pn junctions between the body regions and a drift structure are tilted to the first surface and parallel to the first horizontal direction. Source regions form second pn junctions with the body regions. A gate length of the gate electrode along a second horizontal direction orthogonal to the first horizontal direction is greater than a channel length between the first sections of the first pn junctions and the second pn junctions.

Abstract: The object of the present invention is to enhance the device yield of SiC epitaxial wafers. The SiC epitaxial wafer includes a drift layer which is a SiC epitaxial layer. The drift layer has a film thickness of 18 ?m or more and 350 ?m or less and has arithmetic average roughness of 0.60 nm or more and 3.00 nm or less, and the impurity concentration thereof is 1×1014/cm3 or more and 5×1015/cm3 or less.

Abstract: A semiconductor layer (2,3) is provided on a substrate (1). A gate electrode (4), a source electrode (5) and a drain electrode (6) are provided on the semiconductor layer (3). A first passivation film (7) covers the gate electrode (4) and the semiconductor layer (3). A source field plate (9) is provided on the first passivation film (7), and extends from the source electrode (5) to a space between the gate electrode (4) and the drain electrode (6). A second passivation film (10) covers the first passivation film (7) and the source field plate (9). An end portion on the drain electrode (6) side of the source field plate (9) is curved to be rounded.

Abstract: A semiconductor component includes a field effect transistor structure in a SiC semiconductor body having a gate structure at a first surface of the SiC semiconductor body and a drift zone of a first conductivity type. A zone of the first conductivity type is formed in a vertical direction between a semiconductor region of a second conductivity type and the drift zone. The zone is spaced apart from the gate structure and is at a maximal distance of 1 ?m from the semiconductor region in the vertical direction.

Abstract: A power semiconductor device has a semiconductor body coupled to first and second load terminal structures, the semiconductor body configured to conduct a load current during a conducting state of the device and having a drift region. The power semiconductor device includes a plurality of cells, each cell having: a first mesa in a first cell portion, the first mesa including: a first port region, and a first channel region, the first mesa exhibiting a total extension of less than 100 nm in a lateral direction, and a second mesa in a second cell portion including: a second port region, and a second channel region. A trench structure includes a control electrode structure configured to control the load current by inversion or accumulation. A guidance zone of the second conductivity type is below the second channel region and is displaced from the first and the second channel regions.

Abstract: A silicon carbide MOSFET includes first and second source regions respectively disposed in the first and second well regions. Each of the first and second source regions extends up to a top surface of the substrate. First and second channel regions of the respective first and second well regions laterally separate the first and second source regions from a JFET region by a channel length. The first and second channel regions extend up to the top surface. The first and second channel regions are each arranged in a wave-shaped pattern at the top surface of the substrate. The wave-shaped pattern extends in first and second lateral directions. In an on-state, current flows laterally from the first and second source regions to the JFET region, and then in a vertical direction down through an extended drain region to the drain region.

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of body region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed body region extensions have the same conductivity-type as the body region and extend outwardly from the body region and into the JFET region of a first device cell such that a distance between the body region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

Abstract: A transistor comprises a pair of source/drain regions having a channel there-between. A transistor gate construction is operatively proximate the channel. The channel comprises Si1-yGey, where “y” is from 0 to 0.6. At least a portion of each of the source/drain regions comprises Si1-xGex, where “x” is from 0.5 to 1. Other embodiments, including methods, are disclosed.

Abstract: A method for forming a semiconductor device includes: forming, in a silicon carbide layer of a first conductivity type having a first side, a first silicon carbide region and a second silicon carbide region that forms a pn-junction with the first silicon carbide region; forming a contact region that forms an Ohmic contact with the second silicon carbide region; forming a barrier-layer on the contact region and the first silicon carbide region so that a Schottky-junction is formed between the barrier-layer and the first silicon carbide region and so that an Ohmic connection is formed between the barrier-layer and the contact region, the barrier-layer comprising molybdenum nitride; and forming a first metallization on the barrier-layer, and in Ohmic connection with the barrier-layer.

Abstract: A semiconductor device according to an embodiment includes first electrode; second electrode; silicon carbide layer between the first electrode and the second electrode, the silicon carbide layer having first and second plane, the silicon carbide layer including first silicon carbide region of first-conductivity-type, second silicon carbide region and third silicon carbide region between the first silicon carbide region and the first plane, fourth silicon carbide region between the second silicon carbide region and the first plane, the fourth silicon carbide region contacting the first electrode, fifth silicon carbide region between the second silicon carbide region and the third silicon carbide region, the fifth silicon carbide region having a higher first-conductivity-type impurity concentration than the first silicon carbide region, sixth silicon carbide region between the fifth silicon carbide region and the first plane, the sixth silicon carbide region contacting the first electrode; gate electrode facin

Abstract: Described herein is a semiconductor structure and method of manufacture. The semiconductor structure includes a plurality of semiconductor fins on a substrate and a plurality of raised active regions, wherein each raised active region is located on sidewalls of a corresponding semiconductor fin among said plurality of semiconductor fins. The raised active regions are laterally spaced from any other of the raised active regions. Each raised active region comprises angled sidewall surfaces that are not parallel or perpendicular to a topmost horizontal surface of said substrate. The raised active regions are silicon germanium (SiGe). The semiconductor structure includes a metal semiconductor alloy region contacting at least said angled sidewall surfaces of at least two adjacent raised active regions. The semiconductor alloy region includes a material selected from the group consisting of nickel silicide, nickel-platinum silicide and cobalt silicide.

Abstract: The present invention provides a process and structure of microfabricated air bridges for planar microwave resonator circuits. In an embodiment, the invention includes depositing a superconducting film on a surface of a base material, where the superconducting film is formed with a compressive stress, where the compressive stress is higher than a critical buckling stress of a defined structure, etching an exposed area of the superconducting film, thereby creating the at least one bridge, etching the base material, thereby forming a gap between the at least one bridge and the base material, depositing the at least one metal line on at least part of the superconducting film and at least part of the base material, where the at least one metal line runs under the bridge.

Abstract: A display substrate, a method of manufacturing the same, and a display device are disclosed. The display substrate includes a driving substrate and a micro LED chip, wherein the micro LED chip includes a main body and an electrode pin, a TFT is arranged on the driving substrate, the micro LED chip is coupled to the TFT, and the display substrate further includes: a heat dissipation structure arranged between the micro LED chip and the TFT, wherein the heat dissipation structure is electrically coupled to the electrode pin of the micro LED chip.

Abstract: An etching method in which: molten sodium hydroxide in a prescribed temperature range is used as a molten alkali, whereby an Si surface of an etching surface of an SiC substrate, in which the substrate surface is configured from the Si surface and a C surface, is removed at a higher speed than is the C surface while an oxide film is formed on the etching surface in a high-temperature environment containing oxygen.

Abstract: A semiconductor device includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes first and second layers and first and second regions. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the first layer. The first region is across the first layer and the second layer, and includes at least one first element selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth) and the first region having a first concentration peak of the at least one first element. The second region is provided in the first layer, includes a second element from Ta (tantalum), Nb (niobium), and V (vanadium) and, the second region having a second concentration peak of the at least one second element.

Abstract: Provided is a semiconductor device including: a semiconductor layer of a first conductivity type provided on the semiconductor substrate; a first main electrode provided on the semiconductor layer; a second main electrode provided on a main surface of the semiconductor substrate, opposite to a side on which the first main electrode is provided; an electric field limiting region of a second conductivity type provided in an outside terminal end region on an outer peripheral side of the semiconductor device, a first protective film covering at least the electric field limiting region; a protective metal film provided on a portion from an outside end edge portion of the first protective film to a front surface of the semiconductor layer; and a second protective film provided covering portions on an end edge portion of the first main electrode, the first protective film, and the protective metal film.

Abstract: A semiconductor device is provided that includes a silicon carbide substrate including a main surface at which a plurality of doped zones are formed in a junction termination extension zone of the silicon carbide substrate, the plurality of doped zones are arranged such that a lateral dopant concentration gradient is formed that decreases from a central region of the silicon carbide substrate to an outer edge region of the silicon carbide substrate.

Abstract: Technology for light detection and ranging (LIDAR) sensor can include an optical signal source, an optical modulation array and optical detector on the same integrated circuit (IC) chip, multi-chip module (MCM) or similar solid-state package.

Abstract: A method of manufacturing a semiconductor laser including providing a substrate having a semiconductor layer sequence with an active layer that generates light during operation of the semiconductor laser, applying a continuous contact layer having at least one first partial region and at least one second partial region on a bottom side of the substrate opposite the semiconductor layer sequence, and locally annealing the contact layer only in the at least one first partial region.

Abstract: A light emitting device includes a wavelength conversion layer, at least one light emitting unit and a reflective protecting element. The wavelength conversion layer has an upper surface and a lower surface opposite to each other. The light emitting unit has two electrode pads located on the same side of the light emitting unit. The light emitting unit is disposed on the upper surface of the wavelength conversion layer and exposes the two electrode pads. The reflective protecting element encapsulates at least a portion of the light emitting unit and a portion of the wavelength conversion layer, and exposes the two electrode pads of the light emitting unit.