Abstract: A semiconductor device includes a plurality of semiconductor elements each having a front surface and a back surface; a front surface-side heatsink that is positioned on a front-surface side of the semiconductor elements and dissipates heat generated by the semiconductor elements; a back surface-side heatsink that is positioned on a back surface-side of the semiconductor elements and dissipates heat generated by the semiconductor elements; a sealing material that covers the semiconductor device except for a front surface of the front surface-side heatsink and a back surface of the back surface-side heatsink; a primer that is coated on at least one of the front surface-side heatsink and the back surface-side heatsink and improves contact with the sealing member; and a protruding portion positioned between the plurality of semiconductor elements, on at least one of the back surface of the front surface-side heatsink and the front surface of the back surface-side heatsink.

Abstract: A semiconductor device includes: a first output unit configured to output a first phase; a second output unit configured to output a second phase different from the first phase, the second output unit being disposed to be stacked on the first output unit; and a controller configured to control the output units.

Abstract: An integrated circuit package comprising an active semiconductor device layer and at least one heat-transfer semiconductor layer on the active semiconductor device layer. The heat-transfer semiconductor layer has a coefficient of thermal expansion that substantially matches a coefficient of thermal expansion of the active semiconductor device layer.

Abstract: A semiconductor device includes a substrate, a semiconductor chip mounted on the substrate, an encapsulating body encapsulating the semiconductor chip on the substrate, the encapsulating body including a top surface and a side surface, and a plurality of heat sink plates embedded in the encapsulating body, each of the heat sink plates including an upper portion and a lower portion, the upper portion having an upper surface exposed from the top surface of the encapsulating body, the lowering portion being embedded in the encapsulating body, each of the plurality of heat sink plates being spaced from the semiconductor chip by the encapsulating body. The lower portion of each of the plurality of the heat sink plates includes a protrusion extending horizontally to an outside of an outer edge of the lower portion.

Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.

Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

Abstract: A power conversion device is provided with a plurality of semiconductor modules. Each semiconductor module includes a heat dissipation member, an insulating substrate, a semiconductor element, an external connection terminal, and a resin portion. The insulating substrate is fixed to the heat dissipation member. The semiconductor element is mounted on the insulating substrate. The external connection terminal includes a first end, which is electrically connected to the semiconductor element, and an opposite second end. The resin portion is molded to the insulating substrate, the semiconductor element, the first end, and at least part of the heat dissipation member. The semiconductor modules each form a unit.

Abstract: A thin-film semiconductor component having a carrier layer and a layer stack which is arranged on the carrier layer, the layer stack containing a semiconductor material and being provided for emitting radiation, wherein a heat dissipating layer provided for cooling the semiconductor component is applied on the carrier layer. A component assembly is also disclosed.

Abstract: One implementation of present disclosure includes a semiconductor package stack. The semiconductor package stack includes an upper package coupled to a lower package by a plurality of solder balls. The semiconductor package stack also includes a lower active die situated in a lower package substrate in the lower package. The lower active die is thermally coupled to a heat spreader in the upper package by a thermal interface material. An upper active die is situated in an upper package substrate in the upper package, the upper package substrate being situated over the heat spreader. The thermal interface material can include an array of aligned carbon nanotubes within a filler material. The heat spreader can include at least one layer of metal or metal alloy. Furthermore, the heat spreader can be connected to ground or a DC voltage source. The plurality of solder balls can be situated under the heat spreader.

Abstract: A LED module with separate heat-dissipation and electrical conduction paths is disclosed, having a metal substrate; a plastic layer, including one or more hollow regions, and attached to the metal substrate; one or more conducting elements attached to the plastic layer; one or more LED chips positioned in the one or more hollow regions of the plastic layer and directly attached to the metal substrate; and a plurality of conducting wires for electrically connecting the one or more conducting elements and the one or more LED chips; wherein inner sides of the one or more hollow regions include one or more inclined surfaces each having an included angle with an upper surface of the metal substrate, and the included angle is between 90˜180 degrees.

Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.

Abstract: A stackable integrated circuit package system including mounting an integrated circuit device over a package carrier, mounting a stiffener over the package carrier and mounting a mountable package carrier over the stiffener with a vertical gap between the integrated circuit device and the mountable package carrier.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming a sacrificial microchannel material on a device, forming an overmold material on the sacrificial microchannel material, and vaporizing the sacrificial microchannel material to form microchannel structures in the overmold that are conformal to the surfaces of the device.

Abstract: A packaged semiconductor device includes a package substrate, a semiconductor die on the package substrate, an encapsulant over the semiconductor die and package substrate, and a heat spreader having a pedestal portion and an outer portion surrounding the pedestal portion. The encapsulant includes an opening within a perimeter of the semiconductor die. The bottom surface of the pedestal portion of the heat spreader faces the top surface of the semiconductor die, wherein a first portion of the opening and at least a portion of the encapsulant is between the bottom surface of the pedestal portion and the semiconductor die.

Abstract: A semiconductor device which provides a small and simple design with efficient cooling. A first electrically conducting cooling element is in contact with first electrodes of semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the first electrodes of the semiconductor elements to an external apparatus. A second electrically conducting cooling element is in contact with second electrodes of the semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the second electrodes of the semiconductor elements to an external apparatus. The semiconductor device includes an interface which is electrically connected to gates of the semiconductor elements for external control of respective states of the semiconductor elements.

Abstract: System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.

Abstract: A semiconductor device according to the present disclosure includes: a plate (13) having a through hole (15); a metal column (16) fixed to the through hole with an insulating member (17) interposed therebetween, and having a projection projecting from the upper surface of the plate; a semiconductor element (12) fixed to the projection; a lead frame (11) electrically connected to the semiconductor element; and a package (14) covering the semiconductor element, and also covering at least part of each of the plate, the metal column, and the lead frame. The lower surface (13b) of the plate is exposed from the package.

Abstract: A method of making a semiconductor device includes providing a first semiconductor die and a conductive frame member having at least one conductive via. A first encapsulation layer is formed. A first redistribution layer is formed opposite the first encapsulation layer. A second redistribution layer is formed opposite the first redistribution layer. A second semiconductor die is mounted and electrically connected with receptor pads in the second redistribution layer. A third semiconductor die is mounted to the second semiconductor die and electrically connected with bond wires to a conductor in the second redistribution layer. A second encapsulation layer embeds the second and third semiconductor dies, the wires, and the conductor in the second redistribution layer.

Abstract: A method and apparatus are provided for manufacturing a lead frame based, over-molded semiconductor package (7) with an exposed pad or power die flag (70) having multiple integrated THT heat spreader pins (71) configured for insertion into one or more vias (77) formed in a printed circuit board (78). The through hole heat spreader pins (71) may be formed as an integral part of the exposed pad (52) or may be solidly connected with the exposed pad (62).

Abstract: A package and method for packaging a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices.

Abstract: A purpose of the application is to provide a semiconductor device production method capable of reducing complexity of production operations and keeping production costs low, and enhancing reliability, and a semiconductor device. One aspect of the invention provides a method of producing a semiconductor device, the method including a first bonding step of bonding a first electrode plate and a semiconductor device portion, and a second bonding step of bonding the semiconductor device portion and a second electrode plate. The method includes a sealing step of forming a sealed composite body by covering target surfaces of a composite body formed by the first bonding step with resin, the target surfaces being surfaces other than a second surface of the first electrode plate and the second surface of the semiconductor device portion. The second bonding step is performed after the sealing step.

Abstract: A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect.

Abstract: A semiconductor device includes a carrier and a first chip attached to the carrier. The semiconductor device includes a sintered insulation material over at least a portion of the carrier and the first chip.

Abstract: Disclosed are a light emitting device and a light unit using the same. The light emitting device includes a body, a light emitting diode installed in the body, a plurality of lead frames disposed in the body and electrically connected to the light emitting diode; and a heat dissipation member received in the body, thermally connected to the light emitting diode, and having a plurality of heat dissipation fins exposed from a lower surface of the body.

Abstract: A surface mount optical semiconductor device and circuit can efficiently transfer and dissipate heat even when being mounted together with electronic circuit components. The optical semiconductor device can include a lead frame having a concave portion for mounting a light-emitting element therein and a pair of electrode terminals connected to a board. A sealing resin portion can be provided for sealing a surrounding region of the concave portion. A bottom surface of the concave portion is located at a predetermined distance from a connecting surface on which the pair of electrode terminals is connected to the board. The bottom surface of the concave portion can also be exposed from a bottom surface of the sealing resin portion. Thus, the bottom surface of the concave portion and the device in general can be air-cooled efficiently.

Abstract: A semiconductor device has a substrate. An insulating layer is formed over a surface of the substrate. A semiconductor die is mounted over the surface of the substrate. A channel is formed in the insulating layer around the semiconductor die. An underfill material is deposited between the semiconductor die and the substrate and in the channel. A heat spreader is mounted over the semiconductor die with the heat spreader thermally connected to the substrate. A thermal interface material is formed over the semiconductor die. The underfill material is deposited between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. The channel extends partially through the insulating layer formed over the substrate with the insulating layer maintaining coverage over the substrate within a footprint of the channel.

Abstract: A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from a first side to a second side thereof, and a wire in the via electrically insulated from the semiconductor substrate having a first end with a bonded connection to the substrate contact and a second end proximate to the second side of the semiconductor substrate. The through wire interconnect also includes a first contact on the wire proximate to the first side of the semiconductor substrate, a second contact on the second end of the wire, and a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed. The through wire interconnect can also include a bonding member bonded to the first end of the wire and to the substrate contact having a tip portion forming the first contact.

Abstract: Embodiments of the present disclosure describe semiconductor device packaging techniques and devices that incorporate a heat spreader into the insulating material of a packaged semiconductor device. In one embodiment, a device comprising a semiconductor device is coupled to a substrate, and insulating material covers (i) a portion of the semiconductor device and (ii) a portion of the substrate. The device also comprises a heat spreader embedded in the insulating material and the heat spreader is isolated from the substrate at least in part by the insulating material.

Abstract: A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.

Abstract: An apparatus has external and/or internal capacitive thermal material for enhanced thermal package management. The apparatus includes an integrated circuit (IC) package having a heat generating device. The apparatus also includes a heat spreader having a first side that is attached to the IC package. The apparatus also includes capacitive thermal material reservoirs contacting the first side of the heat spreader. The capacitive thermal material reservoirs may be disposed laterally relative to the heat generating device.

Abstract: Method for manufacturing a rigid power module with a layer that is electrically insulating and conducts well thermally and has been deposited as a coating, the structure having sprayed-on particles that are fused to each other, of at least one material that is electrically insulating and conducts well thermally, having the following steps: manufacturing a one-piece lead frame; populating the lead frame with semiconductor devices, possible passive components, and bonding corresponding connections, inserting the thus populated lead frame into a compression mold so that accessibility of part areas of the lead frame is ensured, pressing a thermosetting compression molding compound into the mold while enclosing the populated lead frame, coating the underside of the thus populated lead frame by thermal spraying in at least the electrically conducting areas and overlapping also the predominant areas of the spaces, filled with mold compound.

Abstract: A technology with which the reliability of a package making up a semiconductor device can be enhanced is provided. A feature of the technical idea of the invention is that: a heat sink unit and an outer lead unit are separated from each other: and the outer lead unit is provided with chip placement portions and each of the chip placement portions and each heat sink are joined together. As a result, when a sealing body is formed at a resin sealing step, tying portions function as a stopper for preventing resin leakage and the formation of resin burr in a package product can be thereby prevented. In addition, camber does not occur in the heat sink unit and cracking in a sealing body caused by winding (camber) can be suppressed.

Abstract: A lateral thermal dissipation LED and a fabrication method thereof are provided. The lateral thermal dissipation LED utilizes a patterned metal layer and a lateral heat spreading layer to transfer heat out of the LED. The thermal dissipation efficiency of the LED is increased, and the lighting emitting efficiency is accordingly improved.

Abstract: A heat releasing semiconductor package, a method for manufacturing the same, and a display apparatus including the same. The heat releasing semiconductor package includes a film, an electrode pattern formed over the film, a semiconductor device mounted over the electrode pattern, and a first heat releasing layer formed over the semiconductor device including the electrode pattern, the first heat releasing layer including a first adhesive and a first heat releasing material.

Abstract: A thermally enhanced expanded wafer level ball grid array package. The expanded wafer level ball grid array package includes an integrated thermally conductive heat dissipater. In one embodiment the heat dissipater is positioned in close proximity to a non-active face of a die and is separated from the non-active face by a thermal interface material. In another embodiment the heat dissipater includes legs that displace the heat dissipater a short distance from the non-active die face, with the intervening space occupied by encapsulation material. In yet another embodiment, the thermal interface material exists between the non-active die face and the heat dissipater, but extends beyond the edge of the semiconductor die to also cover a portion of the encapsulation material. Methods for making the various embodiments of the expanded wafer level ball grid array package are also shown.

Abstract: A method of manufacturing a package module structure of a high power device using a metal substrate that can improve reliability by minimizing stress due to a thermal expansion coefficient difference between a metal substrate and a semiconductor device includes: preparing a metal substrate; forming an oxide layer by selectively anodizing the metal substrate; forming a mounting groove for mounting a semiconductor device by etching a portion of the oxide layer; installing a shock-absorbing substrate that is made of a material having a thermal expansion coefficient in a range similar to a material of a semiconductor device to expose the entirety or a portion of a bottom portion of the mounting groove; mounting the semiconductor device in the shock-absorbing substrate exposed to the mounting groove; and electrically connecting an electrode terminal of the semiconductor device and an electrode line formed in an upper surface of the oxide layer.

Abstract: An electronic device includes an integrated circuit and a heat spreader. The integrated circuit includes a substrate with an active via located therein. The heat spreader includes a thermally conductive core. The active via is connected to a corresponding heat spreader via that passes through the thermally conductive core.

Abstract: A light-emitting diode includes a circuit board, a pair of electrodes provided on the circuit board, at least one light-emitting diode element electrically connected to the pair of electrodes, a central electrode for heat-dissipation, provided between the pair of electrodes on the circuit board, and a heat-dissipation plate disposed on the central electrode for heat-dissipation and including a reflection surface. The central electrode for heat-dissipation includes an upper central electrode disposed on the upper surface of the circuit board and a lower central electrode disposed on the lower surface of the circuit board and the upper central electrode thermally connected to the lower central electrode.

Abstract: The present disclosure provides systems and methods for forming a semiconductor device. The semiconductor device includes a substrate having a first side and a second side opposite the first side. A first heat producing element is formed on the first side of the substrate. A second heat producing element is formed on the first side of substrate co-planar with, but not touching the first heat producing element. A heat spreader is coupled to the second side of the substrate using a thermal interface material. The heat spreader includes a first and second vapor chambers. The first vapor chamber is embedded in the heat spreader substantially opposite the first heat producing element. The second vapor chamber is embedded in the heat spreader substantially opposite the second heat producing element. As an example, the first heat producing element may be a light-emitting diode (LED) and the second heat producing element may be a driver circuit for the LED.

Abstract: A semiconductor device includes a multilayer wiring substrate and a double-sided multi-electrode chip. The double-sided multi-electrode chip includes a semiconductor chip and has multiple electrodes on both sides of the semiconductor chip. The double-sided multi-electrode chip is embedded in the multilayer wiring substrate in such a manner that the double-sided multi-electrode chip is not exposed outside the multilayer wiring substrate. The electrodes of the double-sided multi-electrode chip are connected to wiring layers of the multilayer wiring substrate.

Abstract: A semiconductor package includes a print circuit part, a lower chip, an upper chip, a thermal conductivity part, and an encapsulation resin. The lower chip and the upper chip are mounted on the print circuit part through wire bonding connection. The thermal conductivity part efficiently dissipates heat from the chips to the outside of the package. The encapsulation resin entirely seals the package while exposing the thermal conductivity part. A adhesive sheet is hardened to form a bonding layer between the thermal conductivity part and the upper chip, a bonding layer between the semiconductor chips, and a bonding layer between the semiconductor chip and the wired component. The configuration contributes to miniaturization, high integration, and heat resistance reduction of a semiconductor package using high-heat-generating ICs.

Abstract: An integrated circuit heat spreader stacking system includes: an integrated circuit on a substrate; a heat spreader having a heat sink dome; a stacking stand-off for the heat spreader; and the heat spreader mounted with the heat sink dome over the integrated circuit.

Abstract: A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming an indent, having a flange and an indent side, from a peripheral region of the active side; and forming a conformal interconnect, having an elevated segment, a slope segment, and a flange segment, over the indent.

Abstract: A method for fabricating a stacked semiconductor system with encapsulated through wire interconnects includes providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The method also includes stacking two or more substrates and electrically connecting the through wire interconnects on the substrates.

Abstract: A semiconductor device includes a semiconductor element, a first heat sink, a second heat sink, and a resin member. The semiconductor element has first and second surfaces. The first heat sink has a first heat radiation surface and a first end surface. The first end surface is coupled with the first surface. The second heat sink has a second heat radiation surface, the second end surface being opposite the second heat radiation surface, and a depressed section depressed toward the second heat radiation surface. The second surface of the semiconductor element is coupled with a bottom surface of the depressed section. The resin member is disposed in the depressed section and seals the semiconductor element, the first heat sink, and the second heat sink in such a manner that the first heat radiation surface is exposed outside the resin member.

Abstract: A package structure including a circuit substrate, at least a chip, leads and an encapsulant is provided. The circuit substrate has a first surface, a second surface opposite to the first surface, and contacts disposed on the first surface. The chip is disposed on the second surface of the circuit substrate and electrically connected to the circuit substrate. The leads are disposed on the periphery of the second surface and surround the chip. Each lead has an inner lead portion and an outer lead portion and is electrically connected to the circuit substrate via the inner lead portion. The encapsulant encapsulates the circuit substrate, the chip and the inner lead portion and exposes the first surface of the circuit substrate and the outer lead portion, wherein the upper surface of the encapsulant and the first surface of the circuit substrate are coplanar with each other.

Abstract: An encapsulated semiconductor device includes: a first conduction path formative plate (1); a second conduction path formative plate (5) joined to the first conduction path formative plate; a power element (12) bonded to the first conduction path formative plate; a heatsink (14) held by the first conduction path formative plate with an insulation sheet (13) interposed between the heatsink and the first conduction path formative plate; and an encapsulation resin (9) configured to encapsulate the first and second conduction path formative plates. A through hole (3) or a lead gap (1b) is formed in a region of the first conduction path formative plate in contact with the insulation sheet. The insulation sheet is press-fitted into the through hole or the lead gap.

Abstract: A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.

Abstract: Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane.

Abstract: An integrated circuit package having a selectively etched leadframe strip defining a die attach pad and a plurality of contact pads, at least one side of the die attach pad having a plurality of spaced apart pad portions; a semiconductor die mounted to the die attach pad and wires bonding the semiconductor die to respective ones of the contact pads; a first surface of the leadframe strip, including the semiconductor die and wire bonds, encapsulated in a molding material such that at least one surface of the leadframe strip is exposed, and wherein solder paste is disposed on said contact pads and said at least one side of said die attach pad.