With Heat Sink Embedded In Encapsulant Patents (Class 257/796)
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Patent number: 7598123Abstract: A semiconductor component comprising two stacked semiconductor dice and a method of manufacture. A leadframe having an active area that includes leadframe leads and a cavity is mounted to a support material such as an adhesive tape. A packaged semiconductor die that includes a first semiconductor die mounted to a support structure and encapsulated within a mold compound is mounted on the adhesive tape. A second semiconductor die is mounted to the packaged semiconductor die. Bond pads on the second semiconductor die are electrically connected to the leadframe, the support structure on which the first semiconductor die is mounted, or both. A mold compound is formed around the second semiconductor die, portions of the leadframe, and the packaged semiconductor die. The adhesive tape is removed and the leadframe is singulated to form multi-chip packages.Type: GrantFiled: March 2, 2007Date of Patent: October 6, 2009Assignee: Semiconductor Components Industries, L.L.C.Inventors: Jay A. Yoder, Joseph K. Fauty, James P. Letterman
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Patent number: 7586180Abstract: A thin semiconductor device difficult to cause breakage of a semiconductor chip is disclosed.Type: GrantFiled: July 2, 2008Date of Patent: September 8, 2009Assignee: Renesas Technology Corp.Inventors: Toshiyuki Hata, Hiroshi Sato
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Patent number: 7569920Abstract: An electronic component includes a vertical semiconductor power transistor and a further semiconductor device arranged on the transistor to form a stack. The first vertical semiconductor power transistor has a semiconductor body having a first side and a second side and device structures, at least one first electrode positioned on the first side and at least one second electrode positioned on the second side. The semiconductor body further has at least one electrically conductive via. The via extends from the first side to the second side of the semiconductor body and is galvanically isolated from the device structures of the semiconductor body and from the first electrode and the second electrode.Type: GrantFiled: May 10, 2006Date of Patent: August 4, 2009Assignee: Infineon Technologies AGInventors: Ralf Otremba, Klaus Schiess
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Patent number: 7554210Abstract: A semiconductor device including a semiconductor chip having first and second principal surfaces is disclosed. The semiconductor chip includes a first electrode formed on the first principal surface and a second electrode formed on the second principal surface. A first lead frame includes a first connecting portion connected to the first electrode and a first terminal portion. A second lead frame includes a second connecting portion connected to the second electrode and a second terminal portion. The semiconductor chip is sealed by a housing. The housing is formed so as not to cover part of surfaces of the first and second connecting portions.Type: GrantFiled: April 11, 2006Date of Patent: June 30, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Satoshi Yanagisawa
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Patent number: 7554179Abstract: A multi-leadframe semiconductor package and method of manufacture includes a first leadframe having a die pad and a plurality of contact leads around the periphery of the die pad. A die is attached to the die pad and electrically connected to the plurality of contact leads. A heat spreader leadframe having a heat spreader and a plurality of terminal leads around the periphery of the heat spreader is provided. The die pad is attached to the heat spreader, and the plurality of contact leads is attached to the plurality of terminal leads.Type: GrantFiled: February 7, 2005Date of Patent: June 30, 2009Assignee: Stats Chippac Ltd.Inventors: Il Kwon Shim, Seng Guan Chow, Jeffrey D. Punzalan, Pandi Chelvam Marimuthu
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Patent number: 7550843Abstract: A semiconductor device includes a base member made of a material containing at least a thermosetting resin, and at least one semiconductor constructing body mounted on the base member, and having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base member around the semiconductor constructing body. An interconnection of at least one layer is formed on one sides of the semiconductor constructing body and insulating layer, electrically connected to the external connecting electrode of the semiconductor constructing body, and having a connecting pad portion, the semiconductor substrate is fixed to the base member by fixing force of the base member.Type: GrantFiled: July 13, 2006Date of Patent: June 23, 2009Assignee: Casio Computer Co., Ltd.Inventor: Ichiro Mihara
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Patent number: 7547964Abstract: A semiconductor device package includes a die pad, a substrate disposed on the die pad, and a III-nitride based semiconductor device disposed on the substrate. The device package may also include a second semiconductor device disposed on the die pad or the substrate, which device may be electrically connected to the III-nitride based device to form a circuit.Type: GrantFiled: April 24, 2006Date of Patent: June 16, 2009Assignee: International Rectifier CorporationInventors: Mark Pavier, Norman Glyn Connah
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Patent number: 7545017Abstract: A wafer level package for a surface acoustic wave (SAW) device and a fabrication method thereof. The SAW device wafer level package includes a SAW device in which a SAW element is formed on a top surface of a device wafer, a cap wafer which is bonded with a top surface of the SAW device and has a viahole penetrating the cap wafer, and a conductive member to fill a part of the viahole. The viahole has a first via portion and a second via portion, the first via portion has a gradually smaller diameter from a bottom surface of the cap wafer until a certain depth, and the second via portion has a gradually greater diameter from the first via portion until a top surface of the cap wafer.Type: GrantFiled: June 7, 2006Date of Patent: June 9, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Moon-chul Lee, Jun-sik Hwang, Ji-hyuk Lim, Woon-bae Kim
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Patent number: 7535087Abstract: By disposing a rear surface of a first island 12 and a top surface of a second island 13 so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip 20 are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.Type: GrantFiled: March 28, 2007Date of Patent: May 19, 2009Assignee: Sanyo Electric Co., Ltd.Inventors: Hideyuki Inotsume, Hirokazu Fukuda
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Patent number: 7535085Abstract: A semiconductor package having improved adhesiveness between the chip paddle and the package body and having improved ground-bonding of the chip paddle. A plurality of through-holes are formed in the chip paddle for increasing the bonding strength of encapsulation material in the package body. A plurality of tabs are formed in the chip paddle may also be used alone or in conjunction with the through-holes to further increase the bonding strength of the encapsulation material in the package body. The tabs provide additional area for the bonding site to ground wires from the semiconductor chip by increasing the length of the chip paddle.Type: GrantFiled: April 21, 2006Date of Patent: May 19, 2009Assignee: Amkor Technology, Inc.Inventor: Sung Sik Jang
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Patent number: 7528415Abstract: A semiconductor laser improved in heat sinkability of portions in the vicinity of a light-emitting end face of a main body in order to prevent occurrence of COD is provided. A main body 150 having a light-emitting end face 150a for emitting laser light is formed on a semiconductor substrate, n-type GaAs substrate. Thickness of a front end portion 112a in the vicinity of the light-emitting end face 150a of a plated metal layer 112 formed on the main body 150 is larger than thickness of a central portion 112b of the plated metal layer 112 in a direction along a cavity.Type: GrantFiled: April 20, 2006Date of Patent: May 5, 2009Assignee: Sharp Kabushiki KaishaInventor: Fumie Kunimasa
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Patent number: 7528467Abstract: The present invention relates to an IC substrate provided with over voltage protection functions and thus, a plurality of over voltage protection devices are provided on a single substrate to protect an IC chip directly. According to the present invention, there is no need to install protection devices at respective I/O ports on a printed circuit board to prevent the IC devices from damage by surge pulses. Therefore, the costs to design circuits are reduced, the limited space is efficiently utilized, and unit costs to install respective protection devices are lowered down.Type: GrantFiled: February 28, 2006Date of Patent: May 5, 2009Assignee: Inpaq Technology Co., Ltd.Inventor: Chun-Yuan Lee
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Patent number: 7521794Abstract: A semiconductor device for dissipating heat generated by a die during operation and having a low height profile, a semiconductor die package incorporating the device, and methods of fabricating the device and package are provided. In one embodiment, the semiconductor device comprises a thick thermally conductive plane (e.g., copper plane) mounted on a thin support substrate and interfaced with a die. Thermally conductive via interconnects extending through the substrate conduct heat generated by the die from the conductive plane to conductive balls mounted on traces on the opposing side of the substrate. In another embodiment, the semiconductor devices comprises a thick thermally conductive plane (e.g., copper foil) sandwiched between insulative layers, with signal planes (e.g., traces, bonding pads) disposed on the insulative layers, a die mounted on a first signal plane, and solder balls mounted on bonding pads of a second signal plane.Type: GrantFiled: August 31, 2006Date of Patent: April 21, 2009Assignee: Micron Technology, Inc.Inventors: Pak Hong Yee, Teck Kheng Lee
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Publication number: 20090096115Abstract: A semiconductor package and a method for fabricating the same are disclosed. The present invention discloses mounting and electrically connecting a semiconductor chip to a chip carrier, forming an interfacial layer or a heat-dissipating member having the interfacial layer on the semiconductor chip, and forming an encapsulant for covering the semiconductor chip, the interfacial layer or the heat dissipating member. The method further includes cutting the encapsulant along edges of the interfacial layer, and removing the redundant encapsulant on the interfacial layer so as to expose the semiconductor chip or the heat-dissipating member without forming burr or heavily wearing cutting tools.Type: ApplicationFiled: June 12, 2007Publication date: April 16, 2009Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Ping Huang, Han-Ping Pu, Ho-Yi Tsai
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Patent number: 7518233Abstract: A sealing structure for multi-chip modules stable in cooling performance and excelling in sealing reliability is to be provided. The under face of a frame 5 compatible with a wiring board 1 in thermal expansion rate is fixed with solder 8 to the face of the wiring board 1 for mounting semiconductor devices 2; a rubber O-ring 15 is placed between the upper face of the frame 5 and the under face of the circumference of an air-cooled: heat sink 7; the plastic member 6 making possible relative sliding is placed between the upper face of the circumference of the heat sink 7 and the upper frame 10; the upper face of a plastic member 6 is restrained with the inside middle stage of an upper frame 10; and the lower part of the upper frame 10 and the frame 5 are fastened together with bolts 9.Type: GrantFiled: June 9, 2000Date of Patent: April 14, 2009Assignees: Hitachi, Ltd., Hitachi Information Technology Co., Ltd.Inventors: Kouichi Takahashi, Kenichi Kasai, Takahiro Daikoku, Takayuki Uda, Toshitada Netsu, Takeshi Yamaguchi, Takahiko Matsushita, Osamu Maruyama
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Patent number: 7504736Abstract: A semiconductor packaging mold includes first and second mold bodies, a cavity defined by the first and second mold bodies to provide a space for molding a semiconductor package, and a resin bleed preventing formation on a cavity surface of one of the first and second mold bodies to suppress resin bleeding.Type: GrantFiled: March 28, 2006Date of Patent: March 17, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Uk Kim, Han-Shin Youn
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Patent number: 7501585Abstract: A support element and a semiconductor component including the support element, where the support element having at least one surface with a subregion for receiving a semiconductor device and at least one fluid-tight boundary, which is arranged on the surface and at least partly surrounds the subregion of the surface. A method is also disclosed for arranging a semiconductor device on the surface of a support element, with the steps of: providing a support element which has at least one surface with a subregion for receiving a semiconductor device and at least one fluid-tight boundary which is arranged on the surface and at least partly surrounds the subregion of the surface, introducing an adhesive fluid within the fluid-tight boundary, and introducing a semiconductor device into the adhesive fluid.Type: GrantFiled: January 26, 2005Date of Patent: March 10, 2009Assignee: Infineon Technologies AGInventors: Thomas Killer, Hans-Ludwig Althaus, Melanie Ring
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Publication number: 20090057929Abstract: A power module includes: an encapsulation-target portion having at least one semiconductor element; and an encapsulation member that has first and second planes between which the encapsulation-target portion is interposed, and that encapsulates the encapsulation-target portion. The encapsulation member has, on the at least one semiconductor element, at least one opening that exposes part of a surface of the encapsulation-target portion the surface being on a side of the first plane. Thus, a semiconductor device of which size can be reduced can be provided.Type: ApplicationFiled: March 19, 2008Publication date: March 5, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Taishi SASAKI, Mikio ISHIHARA
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Patent number: 7495346Abstract: There is provided a semiconductor package including: a substrate having a plurality of electrode pads on a surface thereof; a semiconductor chip mounted on the substrate, the semiconductor chip electrically connecting with the plurality of electrode pads; and a stiffener arranged on the substrate so as to surround the semiconductor chip. The stiffener includes: an insulating material layer; and a rigid plate mounted substantially parallel to a surface of the substrate in the insulating material layer, the rigid plate having formed therein a plurality of through holes, at least a part of the through holes being filled with the insulating material.Type: GrantFiled: August 1, 2008Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventors: Tohru Nakanishi, Kosei Tanahashi
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Patent number: 7491583Abstract: A power module fabrication method and structure thereof is disclosed.Type: GrantFiled: March 9, 2006Date of Patent: February 17, 2009Assignee: Delta Electronics, Inc.Inventors: Chin Chi Kuo, Yi Hwa Hsieh
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Patent number: 7479693Abstract: One of the aspects of the present invention is to provide a power semiconductor device, including a first substrate having a first circuit pattern formed thereon, and a second substrate having a second circuit pattern formed thereon. The first substrate has a first center line extending along a predetermined transverse direction. At least one power semiconductor chip is mounted on the first circuit pattern of the first substrate, and has at least one chip electrode opposing to the second circuit pattern of the second substrate. Also, a plurality of first conductive connectors on the first circuit pattern is provided for electrical connection with the second circuit pattern of the second substrate. The first conductive connectors are arranged symmetrically in relative to the first center line of the first substrate.Type: GrantFiled: September 8, 2005Date of Patent: January 20, 2009Assignees: Mitsubishi Denki Kabushiki Kaisha, Alstom Transport SAInventors: Makoto Kondou, Kiyoshi Arai, Jose Saiz, Pierre Solomalala, Emmanuel Dutarde, Benoit Boursat, Philippe Lasserre
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Patent number: 7476967Abstract: Embodiments of a composite carbon nanotube structure comprising a number of carbon nanotubes disposed in a matrix comprised of a metal or a metal oxide. The composite carbon nanotube structures may be used as a thermal interface device in a packaged integrated circuit device.Type: GrantFiled: February 22, 2006Date of Patent: January 13, 2009Assignee: Intel CorporationInventor: Valery M. Dubin
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Patent number: 7473995Abstract: An integrated heat spreader, heat sink or heat pipe with pre-attached phase change thermal interface material and a method of making an electronic assembly.Type: GrantFiled: March 25, 2002Date of Patent: January 6, 2009Assignee: Intel CorporationInventors: Christopher L. Rumer, Sabina J. Houle, Saikumar Jayaraman, Paul A. Koning, Ashay Dani
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Patent number: 7466015Abstract: A supporting frame is used to solidly bridge to the two metallic contacts of a surface mount diode chip. Any bending or twisting stress between the two contacts is borne by the supporting frame instead of the diode chip. Otherwise the stress may damage the diode chip. wherein said supporting forms a cantilever over said first metallic contact and the overhanging end of the cantilever is glued to said second metallic contact.Type: GrantFiled: December 11, 2006Date of Patent: December 16, 2008Inventor: Jiahn-Chang Wu
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Patent number: 7446408Abstract: A package is provided for a semiconductor device including a semiconductor device support substrate having at least one interconnect metal therein connectible to a ground and having at least one opening exposing the surface of the interconnect metal. A heat sink has elastic means integral therewith for cooperating with the opening to position and secure the heat sink to the semiconductor support substrate.Type: GrantFiled: June 16, 2003Date of Patent: November 4, 2008Assignee: ST Assembly Test Services Pte LtdInventors: Il Kwon Shim, Seng Guan Chow, Gerry Balanon
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Publication number: 20080237898Abstract: A semiconductor device of the present invention includes: a laminate structure, including a semiconductor chip, partially sealed with a resin; and a stress relief section for relieving a stress during resin sealing, provided as a convex section including a plain top surface on an uppermost section of the laminate structure, the stress relief section being provided in an annular shape on a peripheral region of the uppermost section so as to come into contact with the sealing resin. This makes it possible to improve the manufacturing yield of the semiconductor device in which the member of the uppermost section is exposed.Type: ApplicationFiled: March 17, 2008Publication date: October 2, 2008Inventors: Yuji YANO, Yasuki Fukui, Koji Miyata
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Patent number: 7405107Abstract: A semiconductor device has at least one semiconductor element, at least one radiator plate thermally connected with said semiconductor element, and a molded resin covering and sealing said semiconductor device and said radiator, wherein an outer main surface of the radiator plate and at least a part of the side surface adjoining the outer main surface are exposed from the molded resin.Type: GrantFiled: November 14, 2005Date of Patent: July 29, 2008Assignee: Denso CorporationInventors: Shusaku Nakazawa, Tsutomu Onoue, Hiroaki Mizuno, Hidehisa Nasu
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Patent number: 7399657Abstract: Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the container by thermally conductive supports formed in the container or attached to the container. The die contacts the supports so that the die and the container form a cavity that is at least partially filled with a thermally conductive material such as a conductive epoxy to promote thermal conduction between the die and the container. The die electrically connects to the substrate with bond wires that extend through an aperture in the substrate and attach to bond pads provided on the substrate. The aperture is typically filled with a protective layer of resin, epoxy, or other material that also encapsulates the bond wires.Type: GrantFiled: July 31, 2002Date of Patent: July 15, 2008Assignee: Micron Technology, Inc.Inventors: Todd O. Bolken, Chad A. Cobbley
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Patent number: 7400049Abstract: An integrated circuit package system is provided forming an external interconnect from a padless lead frame, encapsulating a heat sink and the external interconnect, mounting an integrated circuit die on the heat sink, and encapsulating the integrated circuit die, the heat sink, and the external interconnect.Type: GrantFiled: February 16, 2006Date of Patent: July 15, 2008Assignee: Stats Chippac Ltd.Inventors: Il Kwon Shim, Henry D. Bathan, Zigmund Ramirez Camacho, Jeffrey D. Punzalan
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Patent number: 7388286Abstract: A semiconductor package comprising a semiconductor chip and a first heat spreader adhered to the upper surface of the semiconductor chip is provided. The first heat spreader comprises a flat metal plate and a plurality of metal balls adhered to the flat metal plate. A method of fabricating the semiconductor chip package is also provided.Type: GrantFiled: December 22, 2005Date of Patent: June 17, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-uk Kim, Yun-hyeok Im
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Patent number: 7378731Abstract: A heat spreader and package structure utilizing the same. The heat spreader is embedded in an encapsulant of a package and above a chip therein, wherein the package has a substrate, having a molding gate, and the chip has a center and a corner which is the farthest from the molding gate. The spreader includes a base with a hollow portion therethrough, a plurality of support leads, protruding from the base, on the inner edge, and a cap plate, having a hole at least directly above a region between the center and the corner of the chip, fixed by the support leads to be above the hollow portion, the cap plate.Type: GrantFiled: February 12, 2007Date of Patent: May 27, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chender Huang, Pei-Haw Tsao, Allan Lin, Jeffrey Hsu
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Patent number: 7371617Abstract: A semiconductor package with a heat sink and a method for fabricating the same are proposed. The heat sink is provided with a rigid and thermally resistant detach member on a top surface thereof, and is attached via its bottom surface to a chip mounted on a chip carrier. The detach member is sized larger than the heat sink and can be easily removed from the top surface of the heat sink. Subsequently, a molding process is performed to form an encapsulant for completely encapsulating the chip, the heat sink and the detach member. Then, a singulation process is performed to cut along predetermined cutting lines located between sides of the heat sink and corresponding sides of the detach member. Finally, the detach member and a portion of the encapsulant formed on the detach member are removed from the heat sink. The above fabrication method reduces the packaging cost.Type: GrantFiled: October 12, 2006Date of Patent: May 13, 2008Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ho-Yi Tsai, Chien-Ping Huang
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Patent number: 7372146Abstract: A semiconductor module includes a parts-mounting or packaging substrate, a plurality of power metal insulator semiconductor (MIS) chips which have top surfaces and back surfaces and are mounted by flip chip bonding on or above the package substrate while letting the top surfaces face the package substrate, a drive-use integrated circuit (IC) chip which is mounted by flip chip bonding above the package substrate for driving the gates of metal insulator semiconductor field effect transistors (MISFETs) that are formed on the power MIS chips a plurality of heat sinks disposed on or above the back surfaces of the power MIS chips, and a resin member for sealing the power MIS chips and the driver IC chip together in a single package.Type: GrantFiled: December 13, 2005Date of Patent: May 13, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Nobuyuki Sato
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Patent number: 7368810Abstract: Invertible microfeature device packages and associated methods for manufacture and use are disclosed. A package in accordance with one embodiment includes a microfeature device having a plurality of device contacts, and a conductive structure electrically connected to the contacts. The conductive structure can have first and second package contacts accessible for electrical coupling to at least one device external to the package, with the first package contacts accessible from a first direction and the second package contacts configured to receive solder balls and accessible from a second direction opposite the first. An encapsulant can be disposed adjacent to the microfeature device and the conductive structure and can have apertures aligned with the second package contacts to contain solder balls carried by the second package contacts.Type: GrantFiled: August 29, 2003Date of Patent: May 6, 2008Assignee: Micron Technology, Inc.Inventors: Eric Tan Swee Seng, Lim Thiam Chye
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Patent number: 7365422Abstract: A package of a leadframe with heatsinks, including a leadframe, a die, a first heatsink and a second heatsink. The leadframe has a die pad and a plurality of leads, and the leads are disposed around the die pad. The die is disposed on the die pad. The first heatsink is disposed on a first side of the leadframe and has a plurality of first positioning portions. The second heatsink is disposed on a second side of the leadframe. The second heatsink has a plurality of second positioning portions. The second positioning portions correspond to the first positioning portions of the first heatsink, whereby the warping problem of the leadframe is resolved.Type: GrantFiled: December 21, 2005Date of Patent: April 29, 2008Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Pai-Chou Liu, Jun-Cheng Liu, Kenneth Kinhang Ku, Yu-Li Chung
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Patent number: 7359201Abstract: A cover is mounted to a heat-generating electronic part (T) for electrical insulation and heat dissipation purposes. The cover comprises a hollow cover body (20) of rectangular prism shape having a top wall (23), bottom wall (24), side walls, open front wall (21) and closed rear wall (22) and defining a hollow interior (27) into which the electronic part (T) is to be inserted. The interior has sufficient dimensions to accommodate the electronic part. The top and bottom walls are formed flat for slidable contact with the electronic part. The bottom wall is at least 0.1 mm thicker than the top wall.Type: GrantFiled: October 5, 2006Date of Patent: April 15, 2008Assignee: Shin-Etsu Chemical Co., Ltd.Inventor: Takeshi Nakajima
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Patent number: 7355289Abstract: A semiconductor package (10) uses a plurality of thermal conductors (56-64) that extend upward within an encapsulant (16) from one or more thermal bond pads (22, 24, 26) on a die (14) to disperse heat. The thermal conductors may be bond wires or conductive stud bumps and do not extend beyond a lateral edge of the die. One or more of the thermal conductors may be looped within the encapsulant and exposed at an upper surface of the encapsulant. In one form a heat spreader (68) is placed overlying the encapsulant for further heat removal. In another form the heat spreader functions as a power or ground terminal directly to points interior to the die via the thermal conductors. Active bond pads may be placed exclusively along the die's periphery or also included within the interior of the die.Type: GrantFiled: July 29, 2005Date of Patent: April 8, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Kevin J. Hess, Chu-Chung Lee
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Patent number: 7335982Abstract: A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.Type: GrantFiled: March 30, 2005Date of Patent: February 26, 2008Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chin-Li Kao, Yi-Shao Lai, Jeng-Da Wu, Tong-Hong Wang
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Publication number: 20080042302Abstract: The specification describes lidded IC plastic overmolded packages with chimney-type heat sinks. The packages have mechanical hold-down structures in the package lids that, when overmold is applied, form complementary hold-down structures in the overmold.Type: ApplicationFiled: August 16, 2006Publication date: February 21, 2008Inventors: Robert B. Crispell, Robert Scott Kistler, John W. Osenbach
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Patent number: 7323769Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.Type: GrantFiled: May 8, 2006Date of Patent: January 29, 2008Assignee: United Test and Assembly Center Ltd.Inventors: Hien Boon Tan, Anthony Yi Sheng Sun, Francis Koon Seong Poh
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Publication number: 20070296077Abstract: In various embodiments, semiconductor components and methods to manufacture semiconductor components are disclosed. In one embodiment, a method to manufacture semiconductor components includes attaching multiple heat spreaders to a semiconductor wafer. Other embodiments are described and claimed.Type: ApplicationFiled: June 27, 2006Publication date: December 27, 2007Inventor: Dan Moline
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Patent number: 7304372Abstract: A semiconductor package including a bidirectional compound semiconductor component and two power semiconductor devices connected in a cascode configuration.Type: GrantFiled: September 21, 2006Date of Patent: December 4, 2007Assignee: International Rectifier CorporationInventors: Kunzhong Hu, Chuan Cheah
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Patent number: 7285855Abstract: A method of packaging an integrated circuit die (12) includes the steps of loading an array of soft conductive balls into recesses formed in a platen and locating the platen in a first part of a mold cavity. A second part of the mold is pressed against the balls to flatten a surface of the balls. A first mold compound then is injected into the mold cavity such that the mold compound surrounds exposed portions of the balls. The balls are removed from the platen and a first side of an integrated circuit die is attached to the balls such that the die is surrounded by the balls. Die bonding pads on a second side of the die are electrically connected to respective ones of the balls surrounding the die, and then the die, the electrical connections, and a top portion of the conductive balls is encapsulated with a second mold compound. The result is an encapsulated IC having a bottom side with exposed balls.Type: GrantFiled: January 22, 2007Date of Patent: October 23, 2007Assignee: Freescale Semiconductor, IncInventor: Chee Seng Foong
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Patent number: 7273769Abstract: A method and apparatus for encapsulating microelectronic devices. In one embodiment, the method includes removing a portion of encapsulating material that at least partially surrounds a microelectronic substrate by directing a source of laser radiation toward the encapsulating material. The method can further include exposing a surface of the microelectronic substrate, for example, to enhance a rate at which heat is transferred away from the microelectronic substrate. Alternatively, the encapsulating material can be removed to form heat transfer structures, such as pins or ribs, also to enhance a rate at which heat is transferred away from the microelectronic substrate. In still another embodiment, a portion of the encapsulating material or a support member to which the substrate is attached can be removed to define interlocking features that allow one microelectronic substrate package to be stacked on another and to resist relative movement between the two packages.Type: GrantFiled: August 16, 2000Date of Patent: September 25, 2007Assignee: Micron Technology, Inc.Inventor: Joseph M. Brand
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Patent number: 7265444Abstract: To provide an excellent image by reducing buckling of a CCD device having one-dimensional CCD elements mounted thereon due to changes in temperature. A resin molded semiconductor device including a heat sink having a support face with a semiconductor chip mounted thereon electrically connected to a lead frame, a resin molded case forms a space for accommodating the semiconductor chip therein, and has an opening on an upper face thereof defined by side walls including a plurality of linearly arrayed resin projections above a top surface portion of the side walls, and molds the lead frame and heat sink, and a glass cap closing the opening and secured to the resin molded case by a bonding agent layer. The case has a thermal coefficient of expansion matched with that of the heat sink, and mechanical stress between the case and the cap is absorbed by the bonding agent layer having a thickness greater that the height of the linearly arrayed resin projections above the top surface portion of the side walls.Type: GrantFiled: June 18, 2004Date of Patent: September 4, 2007Assignee: NEC Electronics CorporationInventors: Masahiro Koike, Hirochika Narita
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Patent number: 7259451Abstract: Invertible microfeature device packages and associated methods for manufacture and use are disclosed. A package in accordance with one embodiment includes a microfeature device having a plurality of device contacts, and a conductive structure electrically connected to the contacts. The conductive structure can have first and second package contacts accessible for electrical coupling to at least one device external to the package, with the first package contacts accessible from a first direction and the second package contacts configured to receive solder balls and accessible from a second direction opposite the first. An encapsulant can be disposed adjacent to the microfeature device and the conductive structure and can have apertures aligned with the second package contacts to contain solder balls carried by the second package contacts.Type: GrantFiled: August 15, 2005Date of Patent: August 21, 2007Assignee: Micron Technology, Inc.Inventors: Eric Tan Swee Seng, Thiam Chye Lim
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Patent number: 7253505Abstract: The present invention relates to an IC substrate provided with over voltage protection functions and thus, a plurality of over voltage protection devices are provided on a single substrate to protect an IC chip directly. According to the present invention, there is no need to install protection devices at respective I/O ports on a printed circuit board to prevent the IC devices from damage by surge pulses. Therefore, the costs to design circuits are reduced, the limited space is efficiently utilized, and unit costs to install respective protection devices are lowered down.Type: GrantFiled: February 28, 2006Date of Patent: August 7, 2007Assignee: INPAQ Technology Co., Ltd.Inventor: Chun-Yuan Lee
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Patent number: 7250672Abstract: A semiconductor package that includes two semiconductor die each disposed on a respective die pad and a large tracking distance interposed between at least two leads of the package for better creepage characteristics.Type: GrantFiled: November 12, 2004Date of Patent: July 31, 2007Assignee: International Rectifier CorporationInventors: Mark Pavier, Ajit Dubhashi, Jorge Cerezo, Leigh Cormie, Vijay Bolloju
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Patent number: 7247944Abstract: An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame over the conductive traces proximate the semiconductor die periphery and directly attaches to and makes electrical contact with the conductive traces in a LOC arrangement. Alternatively, a connector may contact a portion of the conductive trace to make contact therewith.Type: GrantFiled: April 5, 2005Date of Patent: July 24, 2007Assignee: Micron Technology, Inc.Inventor: Trung T. Doan
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Patent number: RE39957Abstract: A method is provided of making a semiconductor package with a heat spreader in which a chip carrier module plate consisting of a plurality of array-arranged chip carriers is mounted with at least one chip on each of the chip carriers. A heat spreader module plate is attached to the chips, with an interface layer formed on a top surface of the heat spreader module plate. The chip carrier module plate, the chips and the heat spreader module plate are encapsulated. Adhesion force between the interface layer and the encapsulant is larger than that between the interface layer and the heat spreader module plate, and adhesion force between the interface layer and the heat spreader module plate is smaller than that between the heat spreader module plate and the encapsulant.Type: GrantFiled: September 3, 2004Date of Patent: December 25, 2007Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Ping Huang, Tzong-Da Ho, Cheng-Hsu Hsiao