Abstract: A double-face-cooled semiconductor module with an upper arm and a lower arm of an inverter circuit includes first and second heat dissipation members, each having a heat dissipation surface on one side and a conducting member formed on another side through an insulation member. On the conducting member on the first dissipation plate is provided with a fixing portion that fixes a collector surface of the semiconductor chip and a gate conductor connected to a gate terminal of the semiconductor module. The gate electrode terminal and the gate conductor are wire bonded. The conducting member on the second heat dissipation member is connected to an emitter surface of the semiconductor chip connected to the first heat dissipation member. The productivity and reliability are improved by most of formation operations for the upper and lower arms series circuit on one of the heat dissipation member.

Abstract: Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane.

Abstract: An electronically active sheet includes a bottom substrate having a bottom electrically conductive surface. A top substrate having a top electrically conductive surface is disposed facing the bottom electrically conductive surface. An electrical insulator separates the bottom electrically conductive surface from the top electrically conductive surface. At least one bare die electronic element is provided having a top conductive side and a bottom conductive side. Each bare die electronic element is disposed so that the top conductive side is in electrical communication with the top electrically conductive surface and so that the bottom conductive side is in electrical communication with the bottom electrically conductive surface.

Abstract: A mounting structure for a semiconductor element is disclosed. The semiconductor element is bonded to a die pad through an adhesive film, which is formed by applying a predetermined amount of a paste adhesive onto the surface of the die pad and placing the semiconductor element on the die pad so as to press and spread the adhesive between the lower surface of the semiconductor element and the die pad. A wire extends between the semiconductor element and a terminal pad disposed around the die pad. The die pad includes plural grooves in the surface thereof. Each of the grooves extends from the center of the die pad toward a peripheral edge of the die pad and ends at the inner side of the peripheral edge of the die pad.

Abstract: A semiconductor module and a method of manufacturing the same are disclosed including a semiconductor element having an electrode, a heat radiation plate placed in thermal contact with a main surface of the semiconductor element and electrically connected to the electrode thereof, an insulation body directly formed on an outside surface of the heat radiation plate, a metallic body directly formed on an outside surface of the insulation body and having a thickness lower than that of the insulation body, and a mold resin unitarily molding the heat radiation plate, the semiconductor element and the insulation body. The insulation body is covered with the metallic body and the mold resin and the metallic body has an outside surface exposed to an outside of the mold resin.

Abstract: An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package with at least two dice are stacked one atop another is disclosed. A top die is of smaller size compared with a bottom die such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die contains contact pads on the front side that couple with one or more passive components fabricated on the back side of the top die to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component.

Abstract: A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

Abstract: A load driving semiconductor apparatus includes: a driving transistor, which operates based on an input voltage from an external circuit; a power semiconductor device controlling power supply to a load in such a manner that the power semiconductor device supplies electric power to the load when the transistor operates, and the power semiconductor device stops supplying electric power to the load when the transistor stops operating; and a mounting board, on which the driving transistor and the power semiconductor device are mounted. The mounting board includes a heat radiation pattern for emitting heat generated in the power semiconductor device. The heat radiation pattern includes a heat receiving pattern, on which the driving transistor is mounted.

Abstract: An interposer includes a substrate, a conductive structure configured to contact the back side of a semiconductor device and contact pads. The interposer may include first and second sets of contact pads carried by the substrate. The interposer may also include conductive traces carried by the substrate to electrically connect corresponding contact pads of the first and second sets. The receptacles, which may be formed in a surface of the substrate and expose contacts of the second set, may be configured to at least partially receive conductive structures that are secured to the contact pads of the second set. Thus, the interposer may be useful in providing semiconductor device assemblies and packages of reduced height or profile. Such assemblies and packages are also described, as are multi-chip modules including such assemblies or packages.

Abstract: A light-emitting diode (LED) heat dissipation structure is provided, including a package body, a heat dissipation frame, at least one light emitting die, a plurality of conductive leads, and a plurality of conductive wires. The package body forms a cavity and has an outside surface. The heat dissipation frame is coupled to the package body and has a portion disposed inside the cavity. The end section of the heat dissipation frame that projects beyond the lateral segment of the outside surface is bent to extend along the outside surface. The light emitting die is accommodated in the cavity and set on the heat dissipation frame. The conductive leads are disposed in the cavity and each extends through a side wall of the cavity to project beyond a lateral segment of the outside surface. The conductive wires connect the light emitting die and the conductive leads inside the cavity.

Abstract: A power module includes: an encapsulation-target portion having at least one semiconductor element; and an encapsulation member that has first and second planes between which the encapsulation-target portion is interposed, and that encapsulates the encapsulation-target portion. The encapsulation member has, on the at least one semiconductor element, at least one opening that exposes part of a surface of the encapsulation-target portion the surface being on a side of the first plane. Thus, a semiconductor device of which size can be reduced can be provided.

Abstract: A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate.

Abstract: An electronic component has at least two semiconductor devices, a contact clip and a leadframe with a device carrier portion and a plurality of leads. The contact clip extends between the first side of at least two semiconductor devices and at least one lead of the leadframe to electrically connect a load electrode of the at least two semiconductor devices to at least one lead.

Abstract: A vertical stack type multi-chip package is provided having improved reliability by increasing the grounding performance and preventing the decrease in reliability of the multi-chip package from moisture penetration into a lower semiconductor chip. The vertical stack type multi-chip package comprises an organic substrate having a printed circuit pattern on which a semiconductor chip is mounted. A first semiconductor chip is mounted on a die bonding region of the organic substrate and is electrically connected to the organic substrate through a first wire. A metal stiffener is formed on the first semiconductor chip and connected to the organic substrate by a first ground unit around the first semiconductor chip. An encapsulant is used to seal the first semiconductor chip below the metal stiffener. A second semiconductor chip, which is larger in size than that the first semiconductor chip, is mounted on the metal stiffener and connected by a second ground unit.

Abstract: A multi-chip module suitable for use in a battery protection circuit. The multi-chip module includes an integrated circuit chip, a first power transistor, a second power transistor, a first connection structure electrically coupling the integrated circuit chip to the first power transistor, a second connection structure electrically coupling the integrated circuit chip to the second power transistor, and a leadframe structure comprising a first lead, a second lead, a third lead and a fourth lead, wherein the integrated circuit chip, the first power transistor, and the second power transistor are mounted on the leadframe structure. A molding material covers at least part of the integrated circuit chip, the first power transistor, the second power transistor, the first connection structure, and the second connection structure.

Abstract: Integrated circuit systems with thermal dissipation enhancement features are described. In one aspect, an integrated circuit system includes a die incorporating an integrated circuit. The die has a top side and a bottom side. The top side supports an electrical signal communication metallization and a top side thermal dissipation metallization. The bottom side supports a bottom side thermal dissipation metallization.

Abstract: An encapsulated semiconductor device, comprising a first substrate having an electrically conductive surface; a second substrate having an electrically conductive pattern disposed thereon; and a pattern of semiconductor elements, each of the semiconductor elements having a first conductor and a second conductor.

Abstract: A heat releasing semiconductor package, a method for manufacturing the same, and a display apparatus including the same. The heat releasing semiconductor package includes a film, an electrode pattern formed over the film, a semiconductor device mounted over the electrode pattern, and a first heat releasing layer formed over the semiconductor device including the electrode pattern, the first heat releasing layer including a first adhesive and a first heat releasing material.

Abstract: A package and a package assembly for a power device having a high operation voltage and impulse voltage are provided. The package assembly for a power device comprises an assembly wherein the power device is encapsulated and electrically connected to a lead protruding outside the package, and an isolation spacer filling a clearance distance between the package and a heat sink attached to the package.

Abstract: This application relates to a semiconductor device, the semiconductor device comprising a metal carrier, an insulating foil partially covering the metal carrier, a first chip attached to the metal carrier over the insulating foil, and a second chip attached to the metal carrier over a region not covered by the insulating foil.

Abstract: According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.

Abstract: In one embodiment the present invention includes a semiconductor power device. The semiconductor power device includes a single gauge lead frame, a semiconductor die, and a heat sink. The semiconductor die is attached to a first level of the lead frame. The heat sink is attached to a second level of the lead frame. A molding compound encapsulates the semiconductor die and a portion of the lead frame, such that a portion of the heat sink is outside of the molding compound. The resulting device may be efficiently manufactured as compared to dual gauge lead frame devices or devices where the semiconductor die is not attached to the lead frame.

Abstract: A semiconductor device including: a heat sink, a die on the heat sink, resin encapsulating the die, and a mounting aperture in the resin having at least a segment between the heat sink and a first end of the resin, wherein the thickness of the heat sink is no greater than 35% of the thickness of the device.

Abstract: A semiconductor package (20) includes an organic substrate (24) and a semiconductor die subassembly (22). A method (50) for making the semiconductor package (20) entails providing (52) the organic substrate (24) having an opening (26) and electrical contacts (36). The subassembly (22) is formed by producing (64) a semiconductor die (28) and bonding it to a platform layer (30). An elastomeric adhesive (38) is utilized (92) to secure the subassembly (22) in the opening (26). Electrical interconnects (32) are provided (106) between the semiconductor die (28) and the electrical contacts (36) of the organic substrate (24). The organic substrate (24), semiconductor die (28), elastomeric adhesive (38), and electrical interconnects (32) are encapsulated (114) in a packaging material (46). The elastomeric adhesive (38) provides mechanical anchoring of the subassembly (22) to the substrate (24) and provides mechanical stress isolation of the semiconductor die (28) within the semiconductor package (20).

Abstract: A method includes: mounting a plurality of semiconductor elements on a substrate having wirings; connecting electrically electrodes of the semiconductor elements and the wirings; sealing the semiconductor elements with a resin, which is carried out by bringing a thermal conductor having a concavity and the substrate to be in contact with each other so that the semiconductor elements are positioned within the concavity and by filling the concavity with the resin; and separating respective semiconductor elements 1. In the resin-sealing step, in a state where the thermal conductor is arranged with its concavity facing up and the concavity of the thermal conductor is filled with a liquid resin, the semiconductor elements are dipped in the liquid resin in the concavity and the liquid resin is solidified.

Abstract: A semiconductor device and method having high output and having reduced external resistance is reduced and improved radiating performance. A MOSFET (70) has a connecting portion for electrically connecting a surface electrode of a semiconductor pellet and a plurality of inner leads, a resin encapsulant (29), a plurality of outer leads (37), (38) protruding in parallel from the same lateral surface of the resin encapsulant (29) and a header (28) bonded to a back surface of the semiconductor pellet and having a header protruding portion (28c) protruding from a lateral surface of the resin encapsulant (29) opposite to the lateral surface from which the outer leads protrude, wherein the header (28) has an exposed surface (28b) exposed from the resin encapsulant (29); the outer leads (37), (38) are bent; and the exposed of the outer leads (37), (38) are provided at substantially the same height.

Abstract: A double-face-cooled semiconductor module with an upper arm and a lower arm of an inverter circuit includes first and second heat dissipation members, each having a heat dissipation surface on one side and a conducting member formed on another side through an insulation member. On the conducting member on the first dissipation plate is provided with a fixing portion that fixes a collector surface of the semiconductor chip and a gate conductor connected to a gate terminal of the semiconductor module. The gate electrode terminal and the gate conductor are wire bonded. The conducting member on the second heat dissipation member is connected to an emitter surface of the semiconductor chip connected to the first heat dissipation member. The productivity and reliability are improved by most of formation operations for the upper and lower arms series circuit on one of the heat dissipation member.

Abstract: A lead frame with downset baffle paddles and a semiconductor package utilizing the same are revealed. The lead frame primarily comprises a plurality of leads formed on a first plane, a baffle paddle formed on a second plane in parallel, and an internal tie bar formed between the first plane and the second plane. The internal tie bar has at least two or more windings such as “S” shaped to flexibly connect the baffle paddle to an adjacent one of the leads. Therefore, the internal tie bar can reduce the shifting and twisting of the connected lead during the formation of the downset of the baffle paddle.

Abstract: An electronic component includes a lead frame, a semiconductor chip and an encapsulating body. The lead frame includes a heat spreader area, a plurality of conductive lead fingers, at least one non-conductive tie bar, and a metal joint. The metal joint connects the at least one non-conductive tie bar to the heat spreader area. The semiconductor chip is provided on a die pad located on the heat spreader area. The encapsulating body covers at least part of the semiconductor chip, at least part of the at least one non-conductive tie bar and part of the lead frame.

Abstract: A light emitting diode (10) includes an LED chip (14) and an encapsulant (16) enclosing the LED chip. The LED chip has a light emitting surface (141), and the encapsulant has a light output surface (161) over the light emitting surface. The light output surface defines a plurality of annular, concentric grooves (163). Each groove is cooperatively enclosed by a first groove wall (165) and a second groove wall (166). The first groove wall is a portion of a circumferential side surface of a cone, and a conical tip of the cone is located on the light emitting surface of the LED chip.

Abstract: A semiconductor apparatus includes a semiconductor chip 61 including a power semiconductor device using a wide band gap semiconductor, base materials 62 and 63, first and second intermediate members 65 and 68a, a heat conducting member 66, a radiation fin 67, and an encapsulating material 68 for encapsulating the semiconductor chip 61, the first and second intermediate member 65 and 68a and the heat conducting member 66. The tips of the base materials 62 and 63 work respectively as external connection terminals 62a and 63a. The second intermediate member 68a is made of a material with lower heat conductivity than the first intermediate member 65, and a contact area with the semiconductor chip 61 is larger in the second intermediate member 68a than in the first intermediate member.

Abstract: A substrate includes a inorganic material base board has a recess and at least one penetration hole provided around the recess, and a semiconductor device accommodated in the recess and including at least one electrode pad provided on a surface of the semiconductor device. A resin filling is provided in the at least one penetration hole and has at least one through-hole for electrically connecting a top surface and a back surface of the resin filling. An insulating layer covers the surfaces of the semiconductor device, the resin filling and the inorganic material base board and has a first opening corresponding to the at least one through-hole and a second opening corresponding to the at least one electrode pad. A conductive wiring is formed on a surface of the insulating layer for electrically connecting the at least one through-hole and the at least one electrode pad.

Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.

Abstract: A multi-chip package system is provided including providing a first carrier having a first integrated circuit die thereover, providing a second carrier, placing the first carrier coplanar with the second carrier, and molding a package encapsulation around and exposing the first carrier.

Abstract: The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.

Abstract: A package for receiving electronic part has a heat radiating plate having a mounting area where the electronic part is mounted at a center portion of one main surface, a frame body adhered to the one main surface to surround the mounting area, and a wiring conductor derived from the inside to the outside of the frame body. The heat radiating plate has a metallic base body, a metallic body filling inside of the metallic base body, and a metal layer deposited on the metallic base body and the metallic body. The mounting area is formed on the metal layer so as to be located above the metallic body, both of the metallic body and the metal layer have higher thermal conductivity than the metallic body, and both of the frame body and the metallic base body have a smaller coefficient of thermal expansion than the metal layer.

Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. An interlayer material is formed on the second attachment surface of the electrically conductive attachment region. The interlayer material is a thermally conductive, dielectric material. A housing at least in part encloses the semiconductor die and the interlayer material.

Abstract: Provided are semiconductor packages and methods of fabricating the same. An exemplary semiconductor package includes a die pad including a dimple filled with an insulating material in an upper surface or a lower surface thereof. A semiconductor chip is mounted on the upper surface of the first die pad. A package body encapsulates the first die pad and the first semiconductor chip and includes a pinhole. A bottom surface of the pinhole terminates at the insulating material.

Abstract: A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.

Abstract: A heat slug includes a heat spreading member and a supporting member. The supporting member extends outwardly from the edge of the heat spreading member. The tips of the supporting member are formed with a plurality of contact portions, wherein each said contact portion has a bottom face inclined to the surface of the chip carrier art an angle of more that 5 degrees.

Abstract: A light emitting diode (LED) assembly and a method of making the assembly, in which a container having an open top is provided with a two sets of holes through a bottom of the container, an electrically conductive heat sink is attached to the container bottom beneath the first set of holes, and in which an electrically conductive sheet is attached to the container bottom beneath the second set of holes, where the heat sink and sheet are isolated from each other. LEDs are placed in the first set of holes so that each has a first LED terminal on and adhered to an exposed part of the heat sink through the respective one of the first holes and in which a second LED terminal is connected via a wire lead to the sheet through a respective one of the second holes.

Abstract: A semiconductor device in which chips are resin-molded, including: frames having front and back surfaces and die pads; power chips mounted on the surfaces of the die pads; an insulation resin sheet having a first and a second surfaces which are opposed against each other, the resin sheet being disposed such that the back surfaces of the die pads contact the first surface of the resin sheet; and a mold resin applied on the first surface of the resin sheet so as to seal up the power chips. The thermal conductivity of the resin sheet is larger than that of the mold resin.

Abstract: A laser mounted in a casing is driven by and mounted close to its driving circuit. To reduce the effect on the laser of heat generated by the driver circuit, the casing includes a passive heat sink element on which the driver circuit is mounted whereby heat generated by the driver is dissipated by the passive heat sink element.

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.

Abstract: A chip package is provided, which includes a dielectric layer, at least a conductive layer, a chip, a wiring layer and at least a conductive via. The dielectric layer has a first surface, a second surface opposite to the first surface and a plurality of lateral surfaces joined between the first surface and the second surface. One of the lateral surfaces has at least a groove, wherein the groove is extended from the first surface to the second surface. The conductive layer is disposed on the wall of the groove. The chip is inserted in the dielectric layer. The wiring layer is located on the first surface and electrically connected to the conductive layer. The conductive via is located in the dielectric layer to electrically connect the chip to the wiring layer.

Abstract: A semiconductor package is disclosed. In one embodiment, the semiconductor package includes a leadframe including a chip position and a plurality of leadfingers. Each leadfinger includes a cutout in an inner edge providing a chip recess. The semiconductor package further includes a semiconductor chip located in the chip recess. The semiconductor chip has an active surface with a plurality of chip contact pads on each of which an electrically conductive bump is disposed. The inner portions of the leadfingers protrude into the chip position and are electrically connected to the chip contact pads by electrically conductive bumps.

Abstract: The present invention provides an integrated circuit and method of manufacture therefore. The integrated circuit, in one embodiment, includes heat conducting elements located proximate a plurality of heat generating components located over a substrate. The integrated circuit may further include a heat radiating element comprising one or more fins in thermal communication and physical contact with the heat conducting elements, the heat radiating element configured to dissipate heat generated by the heat generating components away from the integrated circuit.

Abstract: A panel and a semiconductor component including a composite board with semiconductor chips and plastic package molding compound and a method for the production thereof is disclosed. In one embodiment, the panel includes a composite board with semiconductor chips arranged in rows and columns in a corresponding plastic package molding compound with a plurality of semiconductor component positions. The thickness of the plastic package molding compound corresponds to the thickness of the semiconductor chips so that a coplanar upper side and a coplanar rear side are formed on the composite board. Located on the coplanar rear side of the composite board is a plastic layer whose coefficient of thermal expansion corresponds to the coefficient of thermal expansion of the composite board. Located on the coplanar upper side of the composite board is a wiring structure which has corresponding external contacts.

Abstract: A QFN integrated circuit is mounted on a leadframe having multiple lead lands and resin material encapsulates the integrated circuit leaving the lead lands exposed. Subsequently a sawing operation divides the lead lands into multiple leads, and the leadframe and resin material are partitioned to form packages. The pitch of the resultant leads is not limited by the pitch of the lead lands of the leadframe, so the leadframe can be of the relatively cheap generic leadframe variety, in which the pitch of the lead lands is higher than the desired pitch of the leads of the completed package. The sawing operation may further include reshaping the diepad area of the leadframe to produce heat sink fins, for improved heat dissipation. The proposed process is suitable both to produce packages including only a single integrated circuit, and also to produce multi-chip modules.

Abstract: A heat dissipation semiconductor package includes a chip carrier, a semiconductor chip, a heat conductive adhesive, a heat dissipation member, and an encapsulant. The semiconductor chip is flip-chip mounted on the chip carrier and defined with a heat conductive adhesive mounting area. Periphery of the heat adhesive mounting area is spaced apart from edge of the semiconductor chip. The heat dissipation member is mounted on the heat conductive adhesive formed in the heat conductive adhesive mounting area. The encapsulant formed between the chip carrier and the heat dissipation member encapsulates the semiconductor chip and the heat conductive adhesive, and embeds edges of the active surface and non-active surface and side edge of the semiconductor chip, thereby increasing bonding area between the encapsulant and the semiconductor chip. The side edges of the heat conductive adhesive and the semiconductor chip are not flush with each other, thereby preventing propagation of delamination.