Miscellaneous Patents (Class 257/798)
  • Patent number: 11279802
    Abstract: The present invention provides an alkali-soluble resin with which a cured film having high extensibility, reduced stress, high adhesion to a metal, and high heat resistance can be obtained, and a photosensitive resin composition containing the alkali-soluble resin, and the present invention is an alkali-soluble resin (A) including a structure represented by a general formula (1) wherein X1 represents a divalent organic group having 2 to 100 carbon atoms, Y1 and Y2 each represent a divalent to hexavalent organic group having 2 to 100 carbon atoms, X2 represents a tetravalent organic group having 2 to 100 carbon atoms, p and q each represent an integer in a range of 0 to 4, and n1 and n2 each represent an integer in a range of 5 to 100,000, wherein (I) and (II) described below are satisfied: (I) an organic group having an aliphatic chain having 8 to 30 carbon atoms is contained as X1 of the general formula (1) at a content of 30 to 70 mol % based on 100 mol % of a total of X1 and X2, and (II) an organic group h
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: March 22, 2022
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Yutaro Koyama, Yuki Masuda, Masao Tomikawa
  • Patent number: 11257816
    Abstract: A semiconductor device includes active gate structures and dummy gate electrodes. The active gate structures are above an active region of a substrate. The dummy gate electrodes are above the active region of the substrate. A number of the dummy gate electrodes is less than a number of the active gate structures. The active gate structures and the dummy gate electrodes have different materials, and a distance between adjacent one of the dummy gate electrodes and one of the active gate structures is substantially the same as a gate pitch of the active gate structures.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Ya-Chen Kao
  • Patent number: 11174350
    Abstract: A resin and a photosensitive resin composition whereby a cured film exhibiting high extensibility, reduced stress, and high adhesion to metals can be obtained are provided. A resin (A) including a polyamide structure and at least any structure of an imide precursor structure and an imide structure, wherein at least any of the structures of the resin (A) include a diamine residue having an aliphatic group.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: November 16, 2021
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Yuki Masuda, Yu Shoji, Kimio Isobe, Ryoji Okuda
  • Patent number: 11114633
    Abstract: A method for constructing a solar rectenna array by growing carbon nanotube antennas between lines of metal, and subsequently applying a bias voltage on the carbon nanotube antennas to convert the diodes on the tips of the carbon nanotube antennas from metal oxide carbon diodes to geometric diodes. Techniques for preserving the converted diodes by adding additional oxide are also described.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: September 7, 2021
    Assignee: NOVASOLIX, INC.
    Inventors: Jyotsna Iyer, Laurence H. Cooke
  • Patent number: 11088007
    Abstract: A component structure comprises a substrate and a sacrificial layer comprising a sacrificial material disposed on or in the substrate. The sacrificial layer defines sacrificial portions laterally spaced apart by anchors. A component is disposed entirely over each sacrificial portion and connected to at least one anchor by a tether. A spacer comprising a spacer material is disposed in or on the sacrificial portion at least partially between the tether and the substrate. For at least one etchant, the spacer material etches faster than the sacrificial material when exposed to the etchant.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: August 10, 2021
    Assignee: X-Celeprint Limited
    Inventor: Alin Mihai Fecioru
  • Patent number: 10957669
    Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin. An indium preform is placed between the second adhesion layer and the lid and the indium preform is reflowed.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 23, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas P. Dolbear, Daniel Cavasin, Sanjay Dandia
  • Patent number: 10884464
    Abstract: An information handling system may include a processor having a plurality of cores integrated within an integrated circuit package and a thermal controller communicatively coupled to the processor and configured to, responsive to absence of a condition for operating the processor with a reduced core count, control the processor in accordance with a standard thermal profile defining a maximum operating temperature of the processor as a function of power consumed by the processor, and responsive to presence of the condition for operating the processor with the reduced core count, control the processor in accordance with a modified thermal profile defining a modified maximum operating temperature of the processor as a function of power consumed by the processor, wherein for a given power consumption of the processor, the modified thermal profile defines a modified maximum temperature that is greater than the maximum operating temperature defined by the standard thermal profile.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 5, 2021
    Assignee: Dell Products L.P.
    Inventors: Mukund P. Khatri, William K. Coxe, Robert B. Curtis
  • Patent number: 10819282
    Abstract: A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (PDip), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (VGB) chosen so as to move the trough toward a given operating power of the radiofrequency circuit.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: October 27, 2020
    Assignee: Soitec
    Inventors: Marcel Broekaart, Frederic Allibert, Eric Desbonnets, Jean-Pierre Raskin, Martin Rack
  • Patent number: 10804154
    Abstract: A wafer processing method includes a grouping step of dividing a wafer along division lines demarcating a plurality of devices as one block on the wafer to form a plurality of group pieces, a reattaching step of attaching one of the group pieces to an expansion tape, a modified layer forming step of emitting a laser beam having a wavelength transmittable through the wafer along the division lines for each group piece to form modified layers, a dividing step of expanding the expansion tape, and dividing each of the group pieces in which the modified layers are formed into individual devices.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: October 13, 2020
    Assignee: DISCO CORPORATION
    Inventor: Jinyan Zhao
  • Patent number: 10769341
    Abstract: A simulated-evolution-based macro refinement method includes evaluating a score of each placed macro cell to be refined; generating a random number; determining whether the score satisfies a predetermined condition; placing the macro cell into a queue if the score associated with the macro cell satisfies the predetermined condition; and sorting and placing macro cells of the queue according to scores of the macro cells in the queue.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 8, 2020
    Assignees: NCKU Research and Development Foundation, Himax Technologies Limited
    Inventors: Chia-Min Lin, You-Lun Deng
  • Patent number: 10468486
    Abstract: A silicon-on-insulator (SOI) substrate includes a semiconductor substrate and a multi-layered polycrystalline silicon structure. The multi-layered polycrystalline silicon structure is disposed over the semiconductor substrate. The multi-layered polycrystalline silicon structure includes a plurality of polycrystalline silicon layers stacked over one another, and a native oxide layer between each adjacent pair of polycrystalline silicon layers.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ta Wu, Kuo-Hwa Tzeng, Chih-Hao Wang, Yeur-Luen Tu, Chung-Yi Yu
  • Patent number: 10431562
    Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 1, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas P. Dolbear, Daniel Cavasin, Sanjay Dandia
  • Patent number: 10242962
    Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: March 26, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas P. Dolbear, Daniel Cavasin, Sanjay Dandia
  • Patent number: 10141204
    Abstract: To provide a film which is excellent in releasing property with respect to a resin sealed portion and excellent in low migration property and peeling property with respect to a semiconductor chip, a source electrode or a sealing glass and which is suitable as a mold release film for producing a semiconductor element having a part of the surface of a semiconductor chip, source electrode or sealing glass exposed. A film 1 which comprises a substrate 3 and an adhesive layer 5, wherein the storage elastic modulus at 180° C.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: November 27, 2018
    Assignee: AGC Inc.
    Inventors: Seigo Kotera, Wataru Kasai, Masami Suzuki
  • Patent number: 9929039
    Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: March 27, 2018
    Assignee: STMicroelectronics SA
    Inventors: Didier Dutartre, Herve Jaouen
  • Patent number: 9892226
    Abstract: A method for providing a macro placement of an integrated circuit is provided. An initial placement of the integrated circuit is obtained, wherein the initial placement includes a plurality of first macro blocks. The first macro blocks are divided into a plurality of groups according to the hierarchy of the integrated circuit. A value of layout area is obtained for each of the groups according to macro areas of the first macro blocks. A plurality of candidate placements are obtained for each of the groups according to the value of placement area corresponding to the group, wherein the candidate placement includes the first macro blocks corresponding to the group. A first macro placement is obtained according to a specific placement o selecting from the candidate placements for each of the groups.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: February 13, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chin-Hsiung Hsu, Chun-Chih Yang, Shih-Ying Liu, Che-Jung Lou, Chao-Neng Huang, Chi-Yuan Liu
  • Patent number: 9824891
    Abstract: The invention disclosed a method of manufacturing the thin film, which belongs to the technological field of SOI wafer manufacture. By growing a layer of dielectric material (silicon oxide) on the provided high-resistivity silicon wafer, then to grow a layer of amorphous silicon on the dielectric material, to transfer a layer of silicon oxide to the amorphous silicon, to make the mono crystalline silicon exist on the oxidation layer, so that a SOI wafer with a layer of amorphous silicon is manufactured. The process above is completed in specific process conditions. The manufactured thin film, e.g. SOI wafer with amorphous silicon layer, is used main for RF apparatus.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: November 21, 2017
    Assignee: Shenyang Silicon Technology Co., Ltd.
    Inventor: Wei Sun
  • Patent number: 9590636
    Abstract: A system-on-chip including circuit instances, a selector module, a circuit instance module, and a comparing module. The circuit instances have respectively nodes. The circuit instances are designed to provide nominally a same value at each of the nodes. The selector module is configured to generate a selection signal. The circuit instance module is configured to (i) monitor states of the nodes, and (ii) based on the selection signal, select (a) two or more of the states of the nodes, or (b) two or more parameter values generated based on the two or more of the states of the nodes. The comparing module is configured to: compare (i) the two or more of the states of the nodes, or (ii) the two or more parameter values; and based on the comparison, output a bit of (i) a silicon fingerprint of the system-on-chip, or (ii) a unique response code of the system-on-chip.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: March 7, 2017
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Patrick A. McKinley, Walter Lee McNall
  • Patent number: 9584329
    Abstract: Approaches for using a physically unclonable function (PUF) are described. A selector map is used to indicate stable and unstable bits in a PUF value that is generated by a PUF circuit. The stable bits of the PUF value generated by the PUF circuit may be selected for use by an application, and the unstable bits ignored.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: February 28, 2017
    Assignee: XILINX, INC.
    Inventor: Stephen M. Trimberger
  • Patent number: 9574090
    Abstract: A resin composition containing a binder resin (A), alkoxysilyl group-containing (meth)acrylate compound (B), tetrafunctional or higher functional (meth)acrylate compound (C), and photopolymerization initiator (D), wherein a total content of the alkoxysilyl group-containing (meth)acrylate compound (B) and the tetrafunctional or higher functional (meth)acrylate compound (C) is 0.5 to 10 parts by weight with respect to 100 parts by weight of the binder resin (A) is provided.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: February 21, 2017
    Assignee: ZEON CORPORATION
    Inventor: Hiroaki Shindo
  • Patent number: 9373526
    Abstract: According to an embodiment of the present invention, a method for forming a chip package is provided. The method includes: providing a conducting plate, wherein a plurality of conducting pads are disposed on an upper surface of the conducting plate; forming a plurality of conducting bumps on a lower surface of the conducting plate; patterning the conducting plate by removing a portion of the conducting plate, wherein the patterned conducting plate has a plurality of conducting sections electrically insulated from each other, and each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; forming an insulating support layer to partially surround the conducting bumps; and disposing a chip on the conducting pads.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: June 21, 2016
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Ming-Chieh Lin, Ta-Jen Yu
  • Patent number: 9333330
    Abstract: A micro-needle (4) comprising a sharp tip (31), an elongated body (32) and a head (36) containing at least two parallel independent lumens (5, 6), each of said lumens (5, 6) communicating with a distal side opening (7, 8) of the head (36); said openings (7, 8) being essentially oriented in a direction which is perpendicular with respect to its lumen (5, 6) main direction and wherein the distal top end (33, 34) of said lumen (5, 6) is in the head (36) of the micro-needle (4).
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: May 10, 2016
    Assignee: DEBIOTECH S.A.
    Inventors: Francois Cannehan, Astrid Cachemaille
  • Patent number: 9301401
    Abstract: A fabricated substrate has at least one plurality of posts. The plurality is fabricated such that the two posts are located at a predetermined distance from one another. The substrate is exposed to a fluid matrix containing functionalized carbon nanotubes. The functionalized carbon nanotubes preferentially adhere to the plurality of posts rather than the remainder of the substrate. A connection between posts of the at least one plurality of posts is induced by adhering one end of the functionalized nanotube to one post and a second end of the functionalized carbon nanotube to a second post.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: March 29, 2016
    Assignee: THE BOEING COMPANY
    Inventor: Keith Daniel Humfeld
  • Patent number: 9269795
    Abstract: A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: February 23, 2016
    Assignee: Micron Technology, Inc.
    Inventors: John K. Zahurak, Sanh D. Tang, Lars P. Heineck, Martin C. Roberts, Wolfgang Mueller, Haitao Liu
  • Patent number: 9209375
    Abstract: Methods and devices for controlling thermal conductivity and thermoelectric power of semiconductor nanowires are described. The thermal conductivity and the thermoelectric power are controlled substantially independently of the electrical conductivity of the nanowires by controlling dimensions and doping, respectively, of the nanowires. A thermoelectric device comprising p-doped and n-doped semiconductor nanowire thermocouples is also shown, together with a method to fabricate alternately p-doped and n-doped arrays of silicon nanowires.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: December 8, 2015
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Akram Boukai, Yuri Bunimovich, William A. Goddard, James R. Heath, Jamil Tahir-Kheli
  • Patent number: 9082638
    Abstract: A semiconductor device is made by forming an oxide layer over a substrate and forming a first conductive layer over the oxide layer. The first conductive layer is connected to ground. A second conductive layer is formed over the first conductive layer as a plurality of segments. A third conductive layer is formed over the second conductive layer as a plurality of segments. If the conductive layers are electrically isolated, then a conductive via is formed through these layers. A first segment of the third conductive layer operates as a first passive circuit element. A second segment operates as a second passive circuit element. A third segment is connected to ground and operates as a shield disposed between the first and second segments. The shield has a height at least equal to a height of the passive circuit elements to block cross-talk between the passive circuit elements.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: July 14, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: YongTaek Lee, Gwang Kim, ByungHoon Ahn
  • Patent number: 9076832
    Abstract: In a wafer processing tape, circular or tongue-shaped notched parts facing the center of an adhesive layer, as seen in a plan view, are formed so as to correspond to a pasting region to a wafer ring to a depth that reaches a release base material from the side of a base material film. Due to the formation of the notched parts, when a peeling force acts on the wafer processing tape, portions of a tacky material layer and the base material film which are more outward than the notched parts are peeled off first, and a portion that is more inward than the notched parts remains on the wafer ring in a protruding state. Accordingly, a peeling strength between the wafer processing tape and the wafer ring can be increased. Methods of manufacturing the tape and a semiconductor device are also provided.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: July 7, 2015
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Kouhei Taniguchi, Takayuki Matsuzaki, Shinya Katou, Kouji Komorida, Michio Mashino, Tatsuya Sakuta, Rie Katou
  • Patent number: 9076833
    Abstract: In a wafer processing tape, circular or tongue-shaped notched parts facing the center of an adhesive layer, as seen in a plan view, are formed so as to correspond to a pasting region to a wafer ring to a depth that reaches a release substrate from the side of a base material film. Due to the formation of the notched parts, when a peeling force acts on the wafer processing tape, portions of a tacky material layer and the base material film which are more outward than the notched parts are peeled off first, and a portion that is more inward than the notched parts remains on the wafer ring in a protruding state. Accordingly, a peeling strength between the wafer processing tape and the wafer ring can be increased and the wafer processing tape can be suppressed from being peeled off from the wafer ring during processes.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: July 7, 2015
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Kouhei Taniguchi, Takayuki Matsuzaki, Shinya Katou, Kouji Komorida, Michio Mashino, Tatsuya Sakuta, Rie Katou
  • Publication number: 20150132924
    Abstract: A method of removing a handler wafer. There is provided a handler wafer and a semiconductor device wafer having a plurality of semiconductor devices, the semiconductor device wafer having an active surface side and an inactive surface side. An amorphous carbon layer is applied to a surface of the handler wafer. An adhesive layer is applied to at least one of the amorphous carbon layer of the handler wafer and the active surface side of the semiconductor device wafer. The handler wafer is joined to the semiconductor device wafer through the adhesive layer or layers. Laser radiation is applied to the handler wafer to cause heating of the amorphous carbon layer that in turn causes heating of the adhesive layer or layers. The plurality of semiconductor devices of the semiconductor device wafer are then separated from the handler wafer.
    Type: Application
    Filed: November 13, 2013
    Publication date: May 14, 2015
    Applicant: International Business Machines Corporation
    Inventors: Bing Dang, Sarah H. Knickerbocker, Douglas C. La Tulipe, JR., Spyridon Skordas, Cornelia K. Tsang, Kevin R. Winstel
  • Publication number: 20150115480
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 30, 2015
    Inventors: Igor Peidous, Illaria Katia Marianna Pellicano
  • Patent number: 8987923
    Abstract: Among other things, a semiconductor seal ring and method for forming the same are provided. The semiconductor seal ring comprises a plurality of dielectric layers formed over a semiconductor substrate upon which a semiconductor device is formed. A plurality of conductive layers is arranged among at least some of the plurality of dielectric layers. An upper conductive layer is formed over the plurality of dielectric layers. An upper passivation layer is formed over the upper conductive layer to isolate the upper conductive layer from conductive debris resulting from a die saw process along a die saw cut line. In an example, a first columnar region comprising a first portion of the conductive layers is electrically isolated from the semiconductor device because the first columnar region is disposed relatively close to the die saw cut line and thus can be exposed to conductive debris which can cause undesired short circuits.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Chih Chou, Huei-Ru Liou, Kong-Beng Thei
  • Patent number: 8957457
    Abstract: A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: February 17, 2015
    Assignee: STMicroelectronics SA
    Inventors: Richard Fournel, Pierre Dautriche
  • Publication number: 20140353853
    Abstract: The invention relates to a method for manufacturing a multilayer strucute on a first substrate, the method including: using the first substrate made of a first material having a Young's modulus Ev and a thickness ev, and using a second substrate covered by the multilayer structure, the second substrate being made of a second material having a Young's modulus Es that is different from the Young's modulus Ev and a thickness es, the thicknesses es and ev complying, plus or minus 10%, with the relation (I); molecularly bonding the first substrate and the multilayer structure together; and removing the second substrate.
    Type: Application
    Filed: December 27, 2012
    Publication date: December 4, 2014
    Inventors: Umberto Rossini, Thierry Flahaut, Vincent Larrey
  • Patent number: 8902123
    Abstract: To provide a semiconductor device in which wireless communication is performed between devices formed over different substrates and connection defects of wirings are reduced. A first device having a first antenna is provided over a first substrate, a second device having a second antenna which can communicate with the first antenna is provided over a second substrate, and the first substrate and the second substrate are bonded to each other to manufacture a semiconductor device. The first substrate and the second substrate are bonded to each other by bonding with a bonding layer interposed therebetween, anodic bonding, or surface activated bonding.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: December 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Dairiki, Konami Izumi
  • Patent number: 8896138
    Abstract: A chip identification for organic laminate packaging and methods of manufacture is provided. The method includes forming a material on a wafer which comprises a plurality of chips. The method further includes modifying the material to provide a unique identification for each of the plurality of chips on the wafer. The organic laminate structure includes a chip with a device and a material placed on the chip which is modified to have a unique identification mark for the chip.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Albert J. Banach, Timothy H. Daubenspeck, Wolfgang Sauter
  • Patent number: 8872360
    Abstract: A device includes a housing, at least two qubits disposed in the housing and a resonator disposed in the housing and coupled to the at least two qubits, wherein the at least two qubits are maintained at a fixed frequency and are statically coupled to one another via the resonator, wherein energy levels |03> and |12> are closely aligned, wherein a tuned microwave signal applied to the qubit activates a two-qubit phase interaction.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jerry M. Chow, Jay M. Gambetta, Seth T. Merkel, Chad T. Rigetti, Matthias Steffen
  • Patent number: 8860184
    Abstract: Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: October 14, 2014
    Assignee: Intel Corporation
    Inventors: Swaminathan Sivakumar, Elliot N. Tan
  • Publication number: 20140299997
    Abstract: Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.
    Type: Application
    Filed: June 23, 2014
    Publication date: October 9, 2014
    Inventors: Gurtej Sandhu, Mark Kiehlbauch, Steve Kramer, John Smythe
  • Patent number: 8853815
    Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 7, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii
  • Patent number: 8836086
    Abstract: Disclosed is a semiconductor light emitting chip (20) that is composed of: a substrate (10), which has the C plane of a sapphire single crystal as the front surface, and the side surfaces (25, 26) configured of planes that intersect all the planes equivalent to the M plane of the sapphire single crystal, and which includes modified regions (23, 24) in the side surfaces (25, 26), the modified regions being formed by laser radiation; and a light emitting element (12), which is provided on the substrate front surface (10a) of the substrate (10). In the semiconductor light emitting chip, a tilt of the substrate side surfaces with respect to the substrate front surface is suppressed. Also disclosed is a method for processing the substrate.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: September 16, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Daisuke Hiraiwa, Takehiko Okabe
  • Patent number: 8823007
    Abstract: An integrated MEMS System. CMOS and MEMS devices can be provided in order to form an integrated CMOS-MEMS system. The system can include a silicon substrate layer, a CMOS layer, MEMS and CMOS devices, and a wafer level packaging (WLP) layer. The CMOS layer can form an interface region, one which any number of CMOS MEMS devices can be configured. The integrated MEMS devices can include, but not exclusively, an combination of the following types of sensors: magnetic, pressure, humidity, temperature, chemical, biological, or inertial. Furthermore, the overlying WLP layer can be configured to hermetically seal any number of these integrated devices. The present technique provides an easy to use process that relies upon conventional process technology without substantial modifications to conventional equipment and process and reduces off-chip connections, which make the mass production of smaller and thinner units possible.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: September 2, 2014
    Assignee: mCube Inc.
    Inventor: Xiao “Charles” Yang
  • Publication number: 20140239516
    Abstract: A silicon polymer material, which has a silicon polymer backbone with chromophore groups attached directly to at least a part of the silicon atoms, the polymer further exhibiting carbosilane bonds. The film forming composition and resulting coating properties can be tailored to suit the specific exposure wavelength and device fabrication and design requirements. By using two different chromophores the refractive index and the absorption co-efficient can be efficiently tuned. By varying the proportion of carbosilane bonds, and a desired Si-content of the anti-reflective coating composition can be obtained.
    Type: Application
    Filed: May 5, 2014
    Publication date: August 28, 2014
    Inventor: Ari Karkkainen
  • Publication number: 20140235060
    Abstract: There is provided a resist underlayer film used in lithography process that has a high n value and a low k value, and can effectively reduce reflection of light having a wavelength of 193 nm from the substrate in a three-layer process in which the resist underlayer film is used in combination with a silicon-containing intermediate layer. A resist underlayer film-forming composition used in lithography process including: a polymer containing a unit structure including a product obtained by reaction of a condensed heterocyclic compound and a bicyclo ring compound. The condensed heterocyclic compound is a carbazole compound or a substituted carbazole compound. The bicyclo ring compound is dicyclopentadiene, substituted dicyclopentadiene, tetracyclo[4.4.0.12,5.17,10]dodeca-3,8-diene, or substituted tetracyclo[4.4.0.12,5.17,10]dodeca-3,8-diene.
    Type: Application
    Filed: July 5, 2012
    Publication date: August 21, 2014
    Applicant: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Tetsuya Shinjo, Yasunobu Someya, Keisuke Hashimoto, Ryo Karasawa
  • Publication number: 20140235031
    Abstract: Substrates may be bonded according to a method comprising contacting a first bonding surface of a first substrate with a second bonding surface of a second substrate to form an assembly in the presence of an steam atmosphere under suitable conditions to form a bonding layer between the first and second surfaces, wherein the first bonding surface comprises a polarized surface layer; the second bonding surface comprises a hydrophilic surface layer; the first and second bonding surfaces are different.
    Type: Application
    Filed: October 31, 2012
    Publication date: August 21, 2014
    Inventors: Nicole Herbots, Shawn Whaley, Robert Culbertson, Ross Bennett-Kennett, Ashlee Murphy, Matthew Bade, Sam Farmer, Brance Hudzietz
  • Publication number: 20140232018
    Abstract: A resist underlayer film forming composition for EUV lithography, comprising: as a silane, a hydrolyzable silane, a hydrolyzate of the hydrolyzable silane, a hydrolysis condensate of the hydrolyzable silane, or a mixture of any of the hydrolyzable silane, the hydrolyzate, and the hydrolysis condensate, wherein the hydrolyzable silane includes a combination of tetramethoxysilane, an alkyltrimethoxysilane, and an aryltrialkoxysilane, and the aryltrialkoxysilane is represented by formula (1): (R2)n2—R1—(CH2)n1—Si(X)3??Formula (1) In formula (1), R1 is an aromatic ring consisting of a benzene ring or a naphthalene ring or a ring including an isocyanuric acid structure, R2 is a substituent replacing a hydrogen atom on the aromatic ring and is a halogen atom or a C1-10 alkoxy group, and X is a C1-10 alkoxy group, a C2-10 acyloxy group, or a halogen group.
    Type: Application
    Filed: October 2, 2012
    Publication date: August 21, 2014
    Inventors: Shuhei Shigaki, Hiroaki Yaguchi, Rikimaru Sakamoto, Bang-ching Ho
  • Patent number: 8803340
    Abstract: A geometric diode, method and device applications are described. The geometric diode is produced including a device body formed from an electrically conductive material having an equilibrium mobile charge density, and having a device surface configuration. The material has a charge carrier mean free path with a mean free path length and the device body size is selected based on said the free path length to serve as an electrically conductive path between first and second electrodes delimited by the device surface configuration that is asymmetric with respect to a forward flow of current in a forward direction from the first electrode to the second electrode as compared to a reverse current flow in an reverse direction from the second electrode to the first electrode. A system includes an antenna for receiving electromagnetic radiation coupled with the geometric diode antenna to receive the electromagnetic radiation to produce an electrical response.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: August 12, 2014
    Assignee: The Regents of the University of Colorado, a Body Corporate
    Inventor: Garret Moddel
  • Patent number: 8742546
    Abstract: A semiconductor device includes a first pattern and a plurality of second patterns arranged at equal intervals. When the distance of the space between the first pattern and the second pattern closet to the first pattern is larger than a first distance, a plurality of dummy patterns are arranged in the space with shapes and intervals similar to those of the second patterns. When the distance of the space is equal to or less than the first distance and larger than a second distance, the dummy pattern is spaced from the second pattern closest to the first pattern, and extends toward the first pattern to be brought into contact with the first pattern. When the distance of the space is equal to or less than the second distance, the dummy pattern is spaced from the second pattern closest to the first pattern, and is connected to the first pattern.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: June 3, 2014
    Inventor: Kohei Kato
  • Patent number: 8735858
    Abstract: An ionic device includes a layer of an ionic conductor containing first and second species of impurities. The first species of impurity in the layer is mobile in the ionic conductor, and a concentration profile of the first species determines a functional characteristic of the device. The second species of impurity in the layer interacts with the first species within the layer to create a structure that limits mobility of the first species in the layer.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: May 27, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Dmitri B. Strukov, Alexandre M. Bratkovski, R. Stanley Williams, Zhiyong Li
  • Patent number: 8716876
    Abstract: Systems and methods for stacking a memory chip with respect to an integrated circuit (IC) chip are described. In the systems and methods, a plurality of like memory chips are stacked above one or more IC chip members of a family. The use of a plurality of like memory chips for the family may save costs and complications involved in designing, fabricating, and assembling memory chips of different sizes. The use of a plurality of the memory chips on a single IC chip can enable higher data transfer rates due to parallel data transmission.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: May 6, 2014
    Assignee: Altera Corporation
    Inventors: Richard G. Smolen, Jon M. Long
  • Publication number: 20140117529
    Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Vishal Sipani, Kyle Armstrong, Michael D. Hyatt, Michael Dean Van Patten, David A. Kewley, Ming-Chuan Yang