Light Coupled Transistor Structure Patents (Class 257/83)
  • Patent number: 7049636
    Abstract: A device and corresponding method are provided. The device includes an n-type transistor fabricated over a substrate, the n-type transistor having a gate and two current-carrying electrodes. The device also includes a non-inverted organic light emitting device fabricated over the substrate, the non-inverted organic light emitting device having an anode and a cathode. The cathode is connected to one of the current-carrying electrodes of the n-type transistor.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: May 23, 2006
    Assignee: Universal Display Corporation
    Inventors: Michael S. Weaver, Michael Hack, Min-Hao Michael Lu
  • Patent number: 7049637
    Abstract: A gate length L of a second TFT (21) is set longer than the gate length L of a peripheral TFT. This arrangement makes it possible to accurately control even a small current, using the second TFT (21).
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: May 23, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Shoichiro Matsumoto
  • Patent number: 7045821
    Abstract: A pixel structure of a display and a driving method thereof are disclosed. The pixel structure disclosed in the invention includes a structure with less elements than that of prior art. The driving method thereof is also much easier than that of prior art. The pixel structure and driving method thereof can completely compensate the variations of the threshold voltage of a driving transistor thereof. The pixel structure includes a switching transistor, a driving transistor, a capacitor, a light emitting diode (LED) and a reset transistor.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: May 16, 2006
    Assignee: Hannstar Display Corporation
    Inventors: Po-Sheng Shih, Kei-Hsiung Yang
  • Patent number: 7042024
    Abstract: The purpose of the invention is to improve reliability of a light emitting apparatus comprising TFTs and organic light emitting elements.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: May 9, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Masayuki Sakakura, Toru Takayama
  • Patent number: 7030422
    Abstract: A semiconductor laser diode module in which a laser diode and an optical fiber are optically coupled with each other efficiently irrespective of an ambient temperature change within the laser diode module. The laser diode module includes a laser diode, an optical system including an optical fiber and a lens portion, a holder configured to receive a portion of the optical system, a base having a holder mounting member and a fastening member, and a bottom plate configured to support the base. The holder is mounted to the fastening member at a first joint position, and the fastening member is mounted to the holder mounting member at a second joint position, where the first and second joint positions are located at substantially a same distance from the bottom plate. Alternatively, the first and second joint positions are coplanar with an active layer of the diode.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: April 18, 2006
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Jun Miyokawa, Yuichiro Irie, Etsuji Katayama, Kaoru Sekiguchi, Kiyokazu Tateno
  • Patent number: 7026655
    Abstract: A light-transmitting module of the present invention includes a light-emitting device such as a laser diode (LD), a transistor for shunting-drive the LD and a CAN type package with a base and an electrically conductive block. The LD and the transistor are mounted on a side of the block in side-by-side arrangement such that the LD substantially positions a center of the package. One of the current terminals of the transistor and one electrode of the LD are connected via the conductive block. The other of the current terminal of the transistor and the other of the electrodes of the LD are connected to one lead, while the control terminal of the transistor is connected to the other lead. Since the present module includes the transistor within the CAN type package, the size thereof may be miniaturized, and the quality of the optical output can be enhanced.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: April 11, 2006
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hisao Go, Eiji Tsumura, Akihiro Moto, Kiyoshi Kato, Toshiaki Kihara
  • Patent number: 7016007
    Abstract: A method of manufacturing an array substrate for a liquid crystal display device includes forming a gate line, a gate pad and a gate electrode on a substrate through a first mask process, forming a data line, a data pad, a source electrode, a drain electrode and an active layer on the substrate including the gate line, the gate pad and the gate electrode through a second mask process, wherein the data line crosses the gate line to define a pixel region, the source electrode is extended from the data line, the drain electrode is spaced apart from the source electrode, and the active layer is disposed between the gate electrode and the source and drain electrodes, forming a passivation layer on an entire surface of the substrate including the data line, the source electrode and the drain electrode through a third mask process, the passivation layer being etched to expose the substrate in the pixel region, a part of the drain electrode, the gate pad and the data pad, and forming a pixel electrode, a gate pad ter
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: March 21, 2006
    Assignee: LG.Philips LDC Co., Ltd.
    Inventors: Youn-Gyoung Chang, Heung-Lyul Cho, Soon-Sung Yoo
  • Patent number: 7012278
    Abstract: The object of the invention is to simultaneously achieve a reduction in the off current of a switching thin-film transistor and an increase in the on current of a current thin-film transistor in a current-drive thin-film transistor display apparatus. To achieve this object, the switching thin-film transistor is formed as a transistor of LDD structure or offset structure while the current thin-film transistor is formed as a transistor of self-alignment structure. Alternatively, each of the switching thin-film transistor and the current thin-film transistor is formed as a transistor of LDD structure or offset structure, and the LDD length or offset length of the switching thin-film transistor is increased relative to that of the current thin-film transistor.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: March 14, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Mutsumi Kimura, Hiroshi Kiguchi
  • Patent number: 7008852
    Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: March 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Douglas D. Coolbaugh, Jeffrey Gilbert, Joseph R. Greco, Glenn R. Miller
  • Patent number: 7005675
    Abstract: A current-input light-emitting device of the invention converts a current corresponding to a given video signal to a voltage by passing the current between two nodes of four nodes of a multi-terminal transistor, converts the voltage to a current again by shorting the other two nodes different and supplies the current to a light-emitting element. A threshold-corrected, voltage-input light-emitting device shorts two nodes of four nodes of a multi-terminal transistor to write a threshold value voltage into a storage capacitor and to write a voltage corresponding to a given video signal into the storage capacitor. Next, the other two nodes are shorted, and the voltage of the two nodes is converted to a current. Then the current is supplied to a light-emitting element.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: February 28, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiro Sakamoto, Takeshi Noda, Kazutaka Inukai
  • Patent number: 6995443
    Abstract: An integrated circuit with a number of optical fibers that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical fibers include a cladding layer and a core formed in the high aspect ratio hole. These optical fibers are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.
    Type: Grant
    Filed: February 5, 2004
    Date of Patent: February 7, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Joseph E. Geusic, Kie Y. Ahn, Leonard Forbes
  • Patent number: 6992333
    Abstract: A number of red LEDs, green LEDs, and blue LEDs are mounted on one surface of a polygonal flexible multilayer substrate. The LEDs are connected in series according to color. A red feeder terminal, a green feeder terminal, a blue feeder terminal, and a common terminal are provided on each of at least three sides of the periphery of the flexible multilayer substrate. Circuit patterns for connecting LEDs at the high-potential end of the red, green, and blue series-connected LEDs respectively to the red feeder terminals, green feeder terminals, and blue feeder terminals are provided to the flexible multilayer substrate. Also, a circuit pattern for connecting LEDs at the low-potential end of the red, green, and blue series-connected LEDs all to the common terminals is provided to the flexible multilayer substrate.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: January 31, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideo Nagai, Nobuyuki Matsui, Tetsushi Tamura, Masanori Shimizu
  • Patent number: 6992332
    Abstract: A light emitting element containing an organic compound has a disadvantage in that it tends to be deteriorated by various factors, so that the greatest problem thereof is to increase its reliability (make longer its life span). The present invention provides a method for manufacturing an active matrix type light emitting device and the configuration of such an active matrix type light emitting device having high reliability. In the method, a contact hole extending to a source region or a drain region is formed, and then an interlayer insulation film made of a photosensitive organic insulating material is formed on an interlayer insulation film. The interlayer insulation film has a curved surface on its upper end portion. Subsequently, an interlayer insulation film provided as a silicon nitride film having a film thickness of 20 to 50 nm is formed by a sputtering method using RF power supply.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: January 31, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Mitsuaki Osame
  • Patent number: 6979839
    Abstract: An electro-optical device having six image signal lines that are third layer leads comprising the same layer as data lines. A lead which is branched from one image signal line and crosses the other image signal lines is a parallel connection of a first layer lead and a second layer lead. The first layer lead comprises the same layer as the scanning lines in a display region and the second layer lead comprises the same layer as a barrier film of a thin film transistor (TFT) in the display region. Although the first and second layer leads have high resistance alone, the parallel connection can reduce resistance. In other portions, the second layer lead is used alone to improve the design versatility. Thus, the design versatility of peripheral circuits such as a sampling circuit in an electro-optical device is improved and the lead resistance in the peripheral circuit is reduced.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: December 27, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Masao Murade
  • Patent number: 6979582
    Abstract: The present invention provides a vertical-cavity surface emitting laser (VCSEL) diode and a method for producing the same. In this method, an n-type and a p-type ohmic contact electrodes are previously disposed, and then two pairs of distributed Bragger reflectors (DBRs) are formed. At last, a permanent metal substrate is plated. According to the present invention, reflectivity of the DBRs can be preserved without damage during rapid thermal annealing, and thus brightness of the laser diode is improved.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: December 27, 2005
    Assignee: National Chung-Hsing University
    Inventors: Ray-Hua Horng, Dong-Sing Wu
  • Patent number: 6975011
    Abstract: A radiation-emitting and/or radiation-receiving semiconductor component in which a radiation-emitting and/or radiation-receiving semiconductor chip is secured on a chip carrier part of a lead frame. The chip carrier part forms a trough in the region in which the semiconductor chip is secured wherein the inner surface of the trough is designed in such a way that it constitutes a reflector for the radiation emitted and/or received by the semiconductor chip.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: December 13, 2005
    Assignee: Osram GmbH
    Inventors: Karlheinz Arndt, Herbert Brunner, Franz Schellhorn, Günter Waitl
  • Patent number: 6963118
    Abstract: A method for forming a hybrid active electronic and optical circuit using a lithography mask. The hybrid active electronic and optical circuit comprising an active electronic device and at least one optical device on a Silicon-On-Insulator (SOI) wafer. The SOI wafer including an insulator layer and an upper silicon layer. The upper silicon layer including at least one component of the active electronic device and at least one component of the optical device. The method comprising projecting the lithography mask onto the SOI waver in order to simultaneously pattern the component of the active electronic device and the component of the optical device on the SOI wafer.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: November 8, 2005
    Assignee: SiOptical, Inc.
    Inventors: Shrenik Deliwala, Vipulkumar Patel
  • Patent number: 6956240
    Abstract: In an active matrix type light emitting device, a top surface exit type light emitting device in which an anode formed at an upper portion of an organic compound layer becomes a light exit electrode is provided. In a light emitting element made of a cathode, an organic compound layer and an anode, a protection film is formed in an interface between the anode that is a light exit electrode and the organic compound layer. The protection film formed on the organic compound layer has transmittance in the range of 70 to 100%, and when the anode is deposited by use of the sputtering method, a sputtering damage to the organic compound layer can be inhibited from being inflicted.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: October 18, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshimitsu Konuma, Hiroko Yamazaki
  • Patent number: 6946679
    Abstract: A liquid crystal display device comprises a pair of substrates (11, 12) bonded to each other by a sealing material (13) in the form of a frame provided therebetween, liquid crystal (14) held between the pair of substrates; a reflective layer (111) formed on one (11) of the substrates, and an alignment film (116) formed over the reflective layer (111) at the liquid crystal side. The surface of said one (11) of the substrates has a roughened area (11b) which is roughened and a flat area (11a) which is flat and surrounds the roughened area (11b). The alignment film (116) is formed in the roughened area (11b), and the sealing material (13) is formed in the flat area (11a).
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: September 20, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Naonori Miwa, Keiji Takizawa, Takeyoshi Ushiki, Yoshio Yamaguchi
  • Patent number: 6939771
    Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: September 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Douglas D. Coolbaugh, Jeffrey Gilbert, Joseph R. Greco, Glenn R. Miller
  • Patent number: 6936489
    Abstract: A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device. Not having a direct physical connection between the chip and the chip package decreases the inductive and capacitive effects commonly experienced with physical bonds.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: August 30, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Tim Murphy, Lee Gotcher
  • Patent number: 6930319
    Abstract: A method of fabricating a dense pixel array comprising the steps of: (a) printing a photoresist mask and applying said mask to a semiconductor material substrate to form a masked area and an unmasked area on said substrate; (b) applying a photoresist material layer to the unmasked area of the substrate, then applying a metal layer over the photoresist material layer and the substrate, and then applying a solvent to remove the photoresist material layer and said metal layer applied over said photoresist material layer to leave a plurality of metal layers superimposed over the unmasked area of the substrate; (c) removing the substrate to a depressed substrate surface between the metal layers formed in step (b) to form a plurality of pixels each having an upper metal layer; (d) superimposing an insulative layer over each of the metal layers formed in step (c); (e) forming a hole in at least one of the insulative layers formed in step (d) so as to expose the metal layer under the insulative layer; and (f) superim
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: August 16, 2005
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Lawrence F. DePaulis
  • Patent number: 6927469
    Abstract: A radiation-emitting and/or radiation-receiving semiconductor component, in which a radiation-emitting and/or radiation-receiving semiconductor chip is secured on a chip carrier part of a lead frame. The chip carrier part forms a trough in the region in which the semiconductor chip is secured wherein the inner surface of the trough is designed in such a way that it constitutes a reflector for the radiation emitted and/or received by the semiconductor chip.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: August 9, 2005
    Assignee: Osram GmbH
    Inventors: Karlheinz Arndt, Herbert Brunner, Franz Schellhorn, Günter Waitl
  • Patent number: 6921922
    Abstract: A substrate (2) is composed of laminated green sheets. The substrate (2) is provided with recesses (2f, 2g) formed on at least two locations deeper than implemented heights of ICs (4, 6) and elements (3, 5). A transmitter and a receiver are mounted in different recesses, which are individually covered with a mold resin to form a molded optical communication module (1), which operates fast and causes no optical and electrical crosstalk.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: July 26, 2005
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Katsumi Kobinata, Yoshiki Furukawa, Takahiko Nozaki
  • Patent number: 6919583
    Abstract: An edge-emitting thyristor having an improved external luminous efficiency and a self-scanning light-emitting device array comprising the edge-emitting thyristor are disclosed. To improve the external luminous efficiency of an edge-emitting light-emitting thyristor, a structure where the current injected from an electrode concentrates on and near the edge of the light-emitting thyristor is adopted.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: July 19, 2005
    Assignee: Nippon Sheet Glass Company, Limited
    Inventors: Takashi Tagami, Yukihisa Kusuda, Seiji Ohno, Nobuyuki Komaba
  • Patent number: 6911960
    Abstract: In an active-type electroluminescent (EL) display, a conductor interconnecting a cathode (55) of an EL panel (30, 40) and a connection terminal of a signal input substrate (35) has a multilayer structure formed of a cathode material and a conductive material used in a thin-film transistor forming step. The conductor may be formed of a conductive material used in a thin film transistor forming step. A metal material for a gate electrode or drain electrode is preferably used as the conductive material. The connection conductor structure can reduce the electrical resistance of the connection conductor, thus preventing a decrease in display intensity of an EL display.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: June 28, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Ryoichi Yokoyama
  • Patent number: 6911674
    Abstract: A light emitting device may include a light emitting layer such as an organic semiconductor material, one or more feedback structures, and a coupling structure. The one or more feedback structures may cause light emitted by the light emitting layer to be fed back through it along an axis in the plane of the device, thereby promoting the stimulated emission of light in the light emitting layer. The coupling structure couples some fraction of the feedback light out of the device. The coupled light may be emitted along an axis substantially normal to the plane of the device or at predetermined angles. The coupling and feedback structures may have a corrugated structure, a continuous variation of refractive index along an axis in the device plane, a period refractive index, or any combination thereof. The coupling and feedback structures may be separate, share common portion or combined together.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: June 28, 2005
    Assignee: ZEOLUX Corporation
    Inventor: Allan Keneth Evans
  • Patent number: 6909108
    Abstract: An InAs/GaAs quantum dot light emitting diode and a method of fabricating the same are disclosed. The InAs/GaAs quantum dot light emitting diode which is formed by turning off an As shutter and using As background concentration for epitaxy, comprises a Si-doped GaAs substrate, a N-type structure, an undoped quantum well, aseries of quantum dot layers, spacer layers, a barrier layer and a P-type structure.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: June 21, 2005
    Assignee: Chung-Shan Institute of Science and Technology
    Inventors: Shiang-Feng Tang, Shih-Yen Lin, Si-Chen Lee, Ya-Tung Cherng
  • Patent number: 6900499
    Abstract: A non-volatile memory comprising a semiconductor active layer provided on an insulating substrate, an insulating film provided on the semiconductor active layer, a floating gate electrode provided on the insulating film, an anodic oxidized film obtained by anodic oxidation of the floating gate electrode, and a control gate electrode provided in contact with the anodic oxidized film, and a semiconductor device, particularly a liquid crystal display device comprising the non-volatile memory.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: May 31, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 6900470
    Abstract: An active matrix type planar display device includes display elements arranged in a matrix and auxiliary wiring elements. The display element has an optical active layer between a first electrode formed on a substrate and a second electrode. The auxiliary wiring element is formed in the same layer or on the same surface as the first electrode, electrically insulated from the first electrode, and electrically connected to the second electrode.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: May 31, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Michiya Kobayashi, Kazushige Yamamoto
  • Patent number: 6891214
    Abstract: A semiconductor power module capable of efficiently utilizing the performance of the module and facilitating management of the module in custody. The semiconductor power module having one or more semiconductor power switching elements and a drive unit is provided with a non-volatile memory for storing use history of the module and a drive unit. The use history contains information of one of the number of switching times of the semiconductor power switching element, the number of over-current detections of the semiconductor power switching element and a temperature rise of the semiconductor power module.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: May 10, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhisa Mori, Takashi Ikimi, Shuji Katoh, Yutaka Sato
  • Patent number: 6891200
    Abstract: A number of red LEDs, green LEDs, and blue LEDs are mounted on one surface of a polygonal flexible multilayer substrate. The LEDs are connected in series according to color. A red feeder terminal, a green feeder terminal, a blue feeder terminal, and a common terminal are provided on each of at least three sides of the periphery of the flexible multilayer substrate. Circuit patterns for connecting LEDs at the high-potential end of the red, green, and blue series-connected LEDs respectively to the red feeder terminals, green feeder terminals, and blue feeder terminals are provided to the flexible multilayer substrate. Also, a circuit pattern for connecting LEDs at the low-potential end of the red, green, and blue series-connected LEDs all to the common terminals is provided to the flexible multilayer substrate.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: May 10, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideo Nagai, Nobuyuki Matsui, Tetsushi Tamura, Masanori Shimizu
  • Patent number: 6885788
    Abstract: A light reception/emission device built-in module with optical and electrical wiring combined therein includes: an optical waveguide layer including a core portion and a cladding portion; first and second wiring patterns formed on a main surface of the optical waveguide layer; a light reception device disposed inside the optical waveguide layer, the light reception device being optically connected with the core portion of the optical waveguide layer and being electrically connected with the first wiring pattern; and a light emission device disposed inside the optical waveguide layer, the light emission device being optically connected with the core portion of the optical waveguide layer and being electrically connected with the second wiring pattern. With this configuration, optical coupling between the optical waveguide and the light reception/emission device can be conducted precisely.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: April 26, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Iwaki, Yutaka Taguchi, Tetsuyoshi Ogura, Yasuhiro Sugaya, Toshiyuki Asahi, Tousaku Nishiyama, Yoshinobu Idogawa
  • Patent number: 6876004
    Abstract: An optoelectronic assembly includes a transistor outline (TO) package that houses an optoelectronic device. The TO package and the optoelectronic device are coupled to a circuit interconnect. The circuit interconnect includes an insulator having a first side for transmitting a signal current between the optoelectronic device and a device external to the TO package, and a second side for transmitting a ground current between the TO package and the external device. For a predefined operating frequency range, the impedance of the circuit interconnect approximately matches the impedance of the signal leads of the TO package and also approximately matches the impedance of the device external to the TO package. The optoelectronic device may include a laser diode or a photo diode. In addition, the present invention is an optoelectronic transceiver including a transmitter optoelectronic assembly and a receiver optoelectronic assembly.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: April 5, 2005
    Assignee: Finisar Corporation
    Inventors: Paul K. Rosenberg, Daniel K. Case, Jan Lipson, Rudolf J. Hofmeister, The' Linh Nguyen
  • Patent number: 6864509
    Abstract: Packaging methods suitable for optically linking two silicon chips together for the purpose of optical isolation are shown. These packaging methods rely on the integration of Light Emitting Diodes (LEDs) onto one or both of the silicon chips as well as silicon light detectors. The packaging methods include optically linking of side by side silicon chips and vertically stacked chips.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: March 8, 2005
    Inventor: Eugene Robert Worley
  • Patent number: 6855957
    Abstract: A TFT is manufactured using at least five photomasks in a conventional liquid crystal display device, and therefore the manufacturing cost is high. By performing the formation of the pixel electrode, the source region and the drain region by using three photomasks in three photolithography steps, a liquid crystal display device prepared with a pixel TFT portion, having a reverse stagger type n-channel TFT, and a storage capacitor can be realized.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: February 15, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 6849877
    Abstract: The present invention has an object of providing a light emitting device including an OLED formed on a plastic substrate, which can prevent the degradation due to penetration of moisture or oxygen. On a plastic substrate, a plurality of films for preventing oxygen or moisture from penetrating into an organic light emitting layer in the OLED (hereinafter, referred to as barrier films) and a film having a smaller stress than that of the barrier films (hereinafter, referred to as a stress relaxing film), the film being interposed between the barrier films, are provided. Owing to a laminate structure of a plurality of barrier films, even if a crack occurs in one of the barrier films, the other barrier film(s) can effectively prevent moisture or oxygen from penetrating into the organic light emitting layer. Moreover, the stress relaxing film, which has a smaller stress than that of the barrier films, is interposed between the barrier films, thereby making it possible to reduce a stress of the entire sealing film.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: February 1, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Mai Akiba
  • Patent number: 6847054
    Abstract: An optical transistor is disclosed that provides a fast switching time, an amplified gain, and isolation. The optical transistor receives a small optical input signal at an optical base port, generates an amplified replica at an optical emitter port, and generates an inverted replica on a vertical light at an collector port. One embodiment of the optical transistor is implemented with a vertical lasing semiconductor optical amplifiers (VLSOA), wherein the ballast light is used a signal for the collector port.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: January 25, 2005
    Assignee: Finisar Corporation
    Inventors: Sol P. DiJaili, Jeffrey D. Walker
  • Patent number: 6831301
    Abstract: A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device. Not having a direct physical connection between the chip and the chip package decreases the inductive and capacitive effects commonly experienced with physical bonds.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: December 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Tim Murphy, Lee Gotcher
  • Publication number: 20040238831
    Abstract: When an electrical characteristic of the TFT varies, display unevenness such as brightness unevenness or gradation unevenness is occurred in a display image. According to the present invention, a display device in which variation of an electrical characteristic of a TFT is reduced, and display unevenness is reduced is provided. To obtain the display device, the fluctuation ratio of ON current value in a saturation region of adjacent TFTs is set to be equal to or less than ±12% in a TFT array substrate in which a plurality of TFTs are arranged.
    Type: Application
    Filed: March 17, 2004
    Publication date: December 2, 2004
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuaki Osame, Aya Anzai, Yu Yamazaki, Tamae Takano, Takashi Hamada
  • Publication number: 20040232431
    Abstract: A semiconductor structure for providing cross-point switch functionality includes a monocrystalline silicone substrate, and an amorphous oxide material overlying the monocrystalline silicone substrate. A monocrystalline perovskite oxide material overlies the amorphous oxide material, and a monocrystalline compound semiconductor material overlies the monocrystalline perovskite oxide material. The monocrystalline compound semiconductor material includes an optical source component operable to generate a radiant energy transmission. A diffraction grating is optically coupled with the optical source component and has a configuration for passing the radiant energy transmission in a predetermined radiant energy intensity pattern, forming a plurality of replications of the radiant energy transmission.
    Type: Application
    Filed: June 29, 2004
    Publication date: November 25, 2004
    Applicant: MOTOROLA, INC.
    Inventors: Robert Lempkowski, Daniel Gamota
  • Patent number: 6815723
    Abstract: A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of different organic compound layers of adjacent light emitting elements overlap with each other, without depending upon the method of forming the organic compound layers or the film formation precision.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: November 9, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Toru Takayama
  • Patent number: 6809355
    Abstract: A solid-state imaging device having a gate structure including an oxide film and a nitride film includes upper layer films (for example, a planarization film, an insulating film, and a protective film) allowing ultraviolet rays having a wavelength of 400 nm or less to pass therethrough; and a metal made shield film or an organic film capable of absorbing the ultraviolet rays formed in such a manner as to cover a region of the gate structure (for example, an output gate and a reset gate), excluding a light receiving portion and a transfer portion, of the solid-state imaging device. With this configuration, it is possible to prevent the shift of a threshold voltage Vth, and hence to enhance the reliability of the transfer or reset of electric charges.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: October 26, 2004
    Assignee: Sony Corporation
    Inventor: Kazushi Wada
  • Publication number: 20040206965
    Abstract: A light emitting device may include a light emitting layer such as an organic semiconductor material, one or more feedback structures, and a coupling structure. The one or more feedback structures may cause light emitted by the light emitting layer to be fed back through it along an axis in the plane of the device, thereby promoting the stimulated emission of light in the light emitting layer. The coupling structure couples some fraction of the feedback light out of the device. The coupled light may be emitted along an axis substantially normal to the plane of the device or at predetermined angles. The coupling and feedback structures may have a corrugated structure, a continuous variation of refractive index along an axis in the device plane, a period refractive index, or any combination thereof. The coupling and feedback structures may be separate, share common portion or combined together.
    Type: Application
    Filed: April 16, 2003
    Publication date: October 21, 2004
    Inventor: Allan Kenneth Evans
  • Publication number: 20040188692
    Abstract: Provided is a method of realizing a semiconductor device having a structure in which a sufficient light shielding property is compatible with a sufficient storage capacitance without reducing an aperture ratio. A lower light shielding film is formed on a substrate, a TFT is formed on the lower light shielding film and an upper light shielding film is formed on the TFT via an interlayer insulating film to cover and fit the TFT. Thus, the TFT can be completely light-shielded by the lower light shielding film and the upper light shielding film and an occurrence of a photo leak current can be prevented.
    Type: Application
    Filed: April 5, 2004
    Publication date: September 30, 2004
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akira Ishikawa
  • Patent number: 6797985
    Abstract: An active matrix organic light-emitting diode and manufacturing method thereof is provided. A thin film transistor having a gate, a source and a drain is formed over a substrate. An anode layer is formed over the substrate such that the anode layer connects electrically with the source terminal of the thin film transistor. An organic layer is formed to cover the anode layer and the thin film transistor. The organic layer between the source and the drain serves as a channel region of the thin film transistor. A cathode layer is formed over the organic layer. Since the molecules inside the organic layer are aligned in a direction from the source to the drain and perpendicular to a direction from the anode layer to the cathode layer, electron mobility at the channel region is enhanced and the emitting efficiency of the diode is increased.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: September 28, 2004
    Assignee: Delta Optoelectronics, Inc.
    Inventors: Hsin-Fei Meng, Lai-Cheng Chen, Sheng-fu Horng, Lichi Lin
  • Patent number: 6791160
    Abstract: Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a vertical NPN bipolar transistor which are mounted together on the same semiconductor substrate. The lower wiring layer connected to the TiN lower electrode layer of the capacitive element of MIMC structure is formed on the insulating film and the first interlayer insulating film. Between this insulating film and the p-type semiconductor substrate is the p−-type low-concentration semiconductor layer whose impurity concentration is lower than that of the p-type semiconductor substrate. This construction suppresses the parasitic capacity of the capacitive element of the MIMC structure.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: September 14, 2004
    Assignee: Sony Corporation
    Inventors: Hirokazu Ejiri, Shigeru Kanematsu
  • Publication number: 20040169182
    Abstract: A flat panel display with a plurality of pixels. Each pixel has at least a first transistor and a second transistor and a semiconductor layer of the first transistor has a mobility which is different from a semiconductor layer of the second transistor.
    Type: Application
    Filed: October 29, 2003
    Publication date: September 2, 2004
    Applicant: Samsung SDI Co., Ltd.
    Inventors: Jae Bon Koo, Sang-Il Park
  • Publication number: 20040169183
    Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.
    Type: Application
    Filed: March 5, 2004
    Publication date: September 2, 2004
    Applicant: Semiconductor Energy Laboratory Co., Ltd., a Japan corporation
    Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
  • Patent number: 6777763
    Abstract: In a thin film transistor (TFT), a mask is formed on a gate electrode, and a porous anodic oxide is formed in both sides of the gate electrode using a relatively low voltage. A barrier anodic oxide is formed between the gate electrode and the porous anodic oxide and on the gate electrode using a relatively high voltage. A gate insulating film is etched using the barrier anodic oxide as a mask. The porous anodic oxide is selectively etched after etching barrier anodic oxide, to obtain a region of an active layer on which the gate insulating film is formed and the other region of the active layer on which the gate insulating film is not formed. An element including at least one of oxygen, nitrogen and carbon is introduced into the region of the active layer at high concentration in comparison with a concentration of the other region of the active layer. Further, N- or P-type impurity is introduced into the active layer.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: August 17, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Hideto Ohnuma, Naoaki Yamaguchi, Yasuhiko Takemura