Plural Heterojunctions In Same Device Patents (Class 257/96)
  • Patent number: 10923627
    Abstract: Light emitting diodes and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode (LED) includes a substrate, a semiconductor material carried by the substrate, and an active region proximate to the semiconductor material. The semiconductor material has a first surface proximate to the substrate and a second surface opposite the first surface. The second surface of the semiconductor material is generally non-planar, and the active region generally conforms to the non-planar second surface of the semiconductor material.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott D. Schellhammer, Scott E. Sills, Lifang Xu, Thomas Gehrke, Zaiyuan Ren, Anton J. De Villiers
  • Patent number: 10862273
    Abstract: Optical devices having a structured active region configured for selected wavelengths of light emissions are disclosed.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: December 8, 2020
    Assignee: Soraa Laser Diode, Inc.
    Inventor: James W. Raring
  • Patent number: 10847626
    Abstract: A stacked III-V semiconductor component having a p+ region with a top side, a bottom side, and a dopant concentration of 5·1018-5·1020 N/cm3, a first n? layer with a top side and a bottom side, a dopant concentration of 1012-1017 N/cm3, and a layer thickness of 10-300 ?m, an n+ region with a top side, a bottom side, and a dopant concentration of at least 1018 N/cm3, wherein the p+ regions, the n? layer, and the n+ region follow one another in the stated order, are each formed monolithically, and each comprise a GaAs compound or consist of a GaAs compound, the n+ region or the p+ region is formed as the substrate layer, and the n? layer comprises chromium with a concentration of at least 1014 N/cm3 or at least 1015 N/cm3.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 24, 2020
    Assignee: 3-5 Power Electronics GmbH
    Inventor: Volker Dudek
  • Patent number: 10840468
    Abstract: An organic EL element includes: an anode; a light-emitting layer that is disposed above the anode; a first interlayer that is disposed on the light-emitting layer; a second interlayer that is disposed on the first interlayer; a functional layer that is disposed on the second interlayer; and a cathode that is disposed above the functional layer. The first interlayer includes a fluorine compound including a first metal that is an alkali metal or an alkaline-earth metal. The second interlayer includes a second metal that has a property of cleaving a bond between the first metal and fluorine in the fluorine compound. The functional layer has at least one of an electron transport property and an electron injection property. A thickness D1 of the first interlayer and a thickness D2 of the second interlayer satisfy 3%?D2/D1?25%.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: November 17, 2020
    Assignee: JOLED INC.
    Inventors: Minh Hiep Hoang, Noriyuki Matsusue, Masaki Nishimura, Kazuhiro Yoneda
  • Patent number: 10825957
    Abstract: A light-emitting diode includes: a semiconductor epitaxial structure including a first semiconductor layer, a second semiconductor layer disposed over the first semiconductor layer, an active layer between the first and second semiconductor layers; a first electrode electrically coupled to the first semiconductor layer and including a plurality of first sub-electrodes, wherein the plurality of first sub-electrodes are divided into one or more groups, and any two adjacent first sub-electrodes in the same group have a same projection distance; a second electrode disposed over and electrically coupled to the second semiconductor layer; a third electrode coupled to the plurality of first sub-electrodes and including one or more third sub-electrodes, wherein one of the third sub-electrodes corresponds to one of said one or more groups of the first sub-electrodes and connects first sub-electrodes in the group; and a fourth electrode coupled to the second electrode.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: November 3, 2020
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Gaolin Zheng, Hou-Jun Wu, Anhe He, Shiwei Liu, Kang-Wei Peng, Su-Hui Lin, Chia-Hung Chang
  • Patent number: 10818647
    Abstract: A pixel structure of a display apparatus includes an electrode line, at least one ultra small light-emitting diode, and a connection electrode. The electrode line includes a second electrode separated from a first electrode and at a same level as the first electrode on a base substrate. The at least one ultra small light-emitting diode is on the base substrate and has a length less than a distance between the first and second electrodes. A connection electrode includes a first contact electrode connecting the first electrode to the ultra small light-emitting diode and a second contact electrode connecting the second electrode to the ultra small light-emitting diode.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: October 27, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Daehyun Kim, Hyundeok Im, Hyunmin Cho, Jonghyuk Kang, Sungjin Hong, Jooyeol Lee, Chio Cho
  • Patent number: 10720520
    Abstract: A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: July 21, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Seong-Eun Park, Jianwei Wan, Mihir Tungare, Peter Kim, Srinivasan Kannan
  • Patent number: 10707380
    Abstract: A light-emitting diode includes: a semiconductor epitaxial structure including a first semiconductor layer, a second semiconductor layer disposed over the first semiconductor layer, an active layer disposed between the first and second semiconductor layers; a first electrode electrically coupled to the first semiconductor layer; and a second electrode disposed over and electrically coupled to said second semiconductor layer; wherein: the first electrode includes a plurality of first sub-electrodes; the second electrode includes a plurality of second sub-electrodes; and any two adjacent first sub-electrodes and/or second sub-electrodes have a same projection distance.
    Type: Grant
    Filed: September 30, 2018
    Date of Patent: July 7, 2020
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Gaolin Zheng, Hou-Jun Wu, Anhe He, Shiwei Liu, Kang-Wei Peng, Su-Hui Lin, Chia-Hung Chang
  • Patent number: 10629779
    Abstract: A light-emitting diode according to the present invention comprises: a light-emitting structure which includes a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; passivation layer which protects the light-emitting structure; and a metal layer formed, between the light-emitting structure and the passivation layer, on the light-emitting structure, wherein a distance between the passivation layer and the metal layer is 4 to 12 times greater than the thickness of the passivation layer.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: April 21, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Youn Joon Sung, Sung Ho Jung
  • Patent number: 10594110
    Abstract: A vertical cavity surface emitting laser includes: a supporting base having a principal surface including III-V compound semiconductor containing gallium and arsenic as constituent elements; and a post disposed on the principal surface. The post has a lower spacer region including a III-V compound semiconductor containing gallium and arsenic as group-III elements, and an active layer having a quantum well structure disposed on the lower spacer region. The quantum well structure has a concentration of carbon in a range of 2×1016 cm?3 or more to 5×1016 cm?3 or less. The quantum well structure includes a well layer and a barrier layer. The well layer includes a III-V compound semiconductor containing indium as a group-III element, and the barrier layer includes a III-V compound semiconductor containing indium and aluminum as group-III elements. The lower spacer region is disposed between the supporting base and the active layer.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 17, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kei Fujii, Toshiyuki Tanahashi, Takashi Ishizuka, Susumu Yoshimoto, Takamichi Sumitomo, Koji Nishizuka, Suguru Arikata
  • Patent number: 10573781
    Abstract: A light emitting diode (LED) is manufactured using a process in which hydrogen diffuses out of a p-doped semiconductor layer via an exposed side wall of the p-doped semiconductor layer. The process includes forming a light generation layer on a base semiconductor layer and forming the p-doped semiconductor layer on the light generation layer. A tunnel junction layer is formed on the p-doped semiconductor layer and a contact layer is formed on the junction layer. The process also includes etching through at least the contact layer, the tunnel junction layer, and the p-doped semiconductor layer to expose the side wall of the p-doped semiconductor layer and enabling hydrogen to diffuse out of the p-doped semiconductor layer at least partially through the exposed side wall.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: February 25, 2020
    Assignee: Facebook Technologies, LLC
    Inventors: Anneli Munkholm, David Massoubre
  • Patent number: 10566493
    Abstract: A semiconductor device includes a substrate and a buffer layer disposed on a first portion, a second portion, and a third portion of the substrate. The semiconductor device further includes a multilayer light-emitting diode (LED) stack disposed on the first portion of the substrate, and an optical sensor disposed on the second portion of the substrate. The semiconductor device further includes at least one electrode disposed on the third portion of the substrate, a first conductor in contact with the multilayer LED stack, and a second conductor in contact with the optical sensor. The at least one electrode, the first conductor, and the second conductor are formed of a glassy carbon material.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steve Holmes, Devendra Sadana, Stephen W. Bedell, Bruce Doris, Hariklia Deligianni, Jia Chen
  • Patent number: 10516079
    Abstract: A method is specified for producing an optoelectronic semiconductor component, comprising the following steps: A) providing a structured semiconductor layer sequence (21, 22, 23) having a first semiconductor layer (21) with a base region (21c), at least one well (211), and a first cover region (21a) in the region of the well (211) facing away from the base surface (21c), an active layer (23), and a second semiconductor layer (22) on a side of the active layer (23) facing away from the first semiconductor layer (21), wherein the active layer (23) and the second semiconductor layer (22) are structured jointly in a plurality of regions (221, 231) and each region (221, 231) forms, together with the first semiconductor layer (21), an emission region (3), B) simultaneous application of a first contact layer (41) on the first cover surface (21a) and a second contact layer (42) on a second cover surface (3a) of the emission regions (3) facing away from the first semiconductor layer (21) in such a way that the firs
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: December 24, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Isabel Otto, Alexander F. Pfeuffer, Dominik Scholz
  • Patent number: 10505089
    Abstract: A method of manufacturing a light emitting device includes providing a substrate and establishing metallization on an upper surface of the substrate. A light emitting element is mounted on top of the metallization, and the metallization and light emitting element are electrically connected. Light reflective resin is provided at a position surrounding the light emitting element to reflect light from the light emitting element. The surfaces of metallization, a surface of the light emitting element, a conducting wire, and a top surface of the light reflective resin are covered continuously, with insulating material. An inside surrounded by the light reflective resin is filled with encapsulating material to encapsulate the light emitting element and the insulating material around the light emitting element.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: December 10, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Mototaka Inobe, Motokazu Yamada, Kazuhiro Kamada
  • Patent number: 10475956
    Abstract: An optoelectronic device comprising a semiconductor structure includes a p-type active region and an n-type active region. The semiconductor structure is comprised solely of one or more superlattices, where each superlattice is comprised of a plurality of unit cells. Each unit cell comprises at least two distinct substantially single crystal layers.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: November 12, 2019
    Assignee: Silanna UV Technologies Pte Ltd
    Inventor: Petar Atanackovic
  • Patent number: 10396246
    Abstract: An optoelectronic device includes a semiconductor stack, including a first semiconductor layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer; a first metal layer formed on a top surface of the second semiconductor layer; a second metal layer formed on a top surface of the first semiconductor layer; an insulative layer formed on the top surface of the first semiconductor layer and the top surface of the second semiconductor layer; wherein a space between a sidewall of the first metal layer and a sidewall of the semiconductor stack is less than 3 ?m.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: August 27, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Jia-Kuen Wang, Chao-Hsing Chen
  • Patent number: 10312223
    Abstract: A light-emitting device having a plurality of light-emitting elements closely adjacently disposed in spite of using only one substrate is provided. One or more light-emitting elements are flip-chip mounted on each of upper surface and lower surface of a substrate. The light-emitting elements are disposed so that the light-emitting elements on the upper surface of the substrate and the light-emitting elements on the lower surface of the substrate are closely adjacent to each other when they are seen from above the substrate. The light-emitting elements mounted on the upper surface of the substrate have light-emitting surfaces as the upper surfaces, and the light-emitting elements mounted on the lower surfaces of the substrate have light-emitting surfaces on the substrate side. The substrate transmits at least lights emitted by the light-emitting elements mounted on the lower surface of the substrate.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: June 4, 2019
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventor: Akihiko Hanya
  • Patent number: 10287709
    Abstract: In one instance, the seed crystal of this invention provides a nitrogen-polar c-plane surface of a GaN layer supported by a metallic plate. The coefficient of thermal expansion of the metallic plate matches that of GaN layer. The GaN layer is bonded to the metallic plate with bonding metal. The bonding metal not only bonds the GaN layer to the metallic plate but also covers the entire surface of the metallic plate to prevent corrosion of the metallic plate and optionally spontaneous nucleation of GaN on the metallic plate during the bulk GaN growth in supercritical ammonia. The bonding metal is compatible with the corrosive environment of ammonothermal growth.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: May 14, 2019
    Assignee: SixPoint Materials, Inc.
    Inventors: Tadao Hashimoto, Edward Letts, Daryl Key
  • Patent number: 10263124
    Abstract: A stacked III-V semiconductor diode having an n+ substrate with a dopant concentration of at least 1019 cm?3 and a layer thickness of 50-400 ?m, an n? layer with a dopant concentration of 1012-1016 cm?3 and a layer thickness of 10-300 ?m, a p+ layer with a dopant concentration of 5·1018-5·1020 cm?3, including a GaAs compound and with a layer thickness greater than 2 ?m, wherein the n+ substrate and the n? layer are integrally joined to one another. A doped intermediate layer with a layer thickness of 1-50 ?m and a dopant concentration of 1012-1017 cm?3 is arranged between the n? layer and the p+ layer, and the intermediate layer is integrally joined to the n? layer and to the p+ layer.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 16, 2019
    Assignee: 3-5 Power Electronics GmbH
    Inventor: Volker Dudek
  • Patent number: 10256385
    Abstract: LED packages and related methods are provided. The LED packages can include a submount having a top and bottom surface and a plurality of top electrically conductive elements on the top surface of the submount. An LED can be disposed on one of the top electrically conductive elements. The LED can emit a dominant wavelength generally between approximately 600 nm and approximately 650 nm, and more particularly between approximately 610 nm and approximately 630 nm when an electrical signal is applied to the top electrically conductive elements. A bottom thermally conductive element can be provided on the bottom surface and is not in electrical contact with the top electrically conductive elements. A lens can be disposed over the LED. The LED packages can have improved lumen performances, lower thermal resistances, improved efficiencies, and longer operational lifetimes.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: April 9, 2019
    Assignee: Cree, Inc.
    Inventors: Jeffrey Carl Britt, Yankun Fu
  • Patent number: 10243109
    Abstract: According to the present invention, a light-emitting diode with improved light extraction efficiency comprises: a semiconductor laminated structure including an N-layer, a light-emitting layer, and a P-layer formed on a substrate; an N-type electrode formed on the N-layer; and a P-type electrode formed on the P-layer, wherein the N-type electrode and the P-type electrode include a pad electrode and a dispersion electrode, and the N-type electrode and/or the P-type electrode includes a reflective electrode layer for reflecting light onto the dispersion electrode. Thus, the light-emitting diode has a reflective electrode layer on the electrode so as to improve light extraction efficiency. Further, a reflective layer is patterned beneath a pad unit, thus forming roughness and improving adhesion.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 26, 2019
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jin Woong Lee, Kyoung Wan Kim, Yeo Jin Yoon, Ye Seul Kim
  • Patent number: 10211370
    Abstract: An infrared LED having a monolithic and stacked structure, having an n-doped base substrate, which includes GaAs, a lower cladding layer, an active layer for generating infrared radiation, an upper cladding layer, a current distribution layer and an upper contact layer. The layers being preferably disposed in the specified order. A first tunnel diode is disposed between the upper cladding layer and the current distribution layer, and the current distribution layer predominantly including an n-doped, Ga-containing layer having a Ga content>1%.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: February 19, 2019
    Assignee: Azur Space Solar Power GmbH
    Inventors: Daniel Fuhrmann, Matthias Meusel
  • Patent number: 10205074
    Abstract: A semiconductor light emitting device package includes a semiconductor light emitting device including a plurality of electrodes, a circuit board including a mounting region, the semiconductor light emitting device being positioned on the mounting region of the circuit board, and a plurality of electrode pads on the circuit board, the plurality of electrode pads being electrically connected to the plurality of electrodes, wherein each of the plurality of electrode pads includes a first region and a second region, the first region overlapping the mounting region, and the second region excluding the first region, and wherein the plurality of electrode pads is arranged in a shape of rotational symmetry around a pivot point of the mounting region.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jong Sup Song
  • Patent number: 10134806
    Abstract: A semiconductor light emitting device includes first and second light emitting bodies, a first electrode, a second electrode and a first interconnection. The first and second light emitting bodies are disposed on a conductive substrate, and each includes first and second semiconductor layers and a light emitting layer therebetween. The first electrode is provided between the first light emitting body and the conductive substrate, and electrically connected to a first semiconductor layer and the conductive substrate. The second electrode is provided between the second light emitting body and the conductive substrate, and electrically connected to a first semiconductor layer. The first interconnection electrically connects the second semiconductor layer of the first light emitting body and the second electrode. The first interconnection includes a first portion extending over the first and second light emitting bodies and a second portion extending into the second light emitting body.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: November 20, 2018
    Assignee: Alpad Corporation
    Inventors: Koji Kaga, Jumpei Tajima, Toshiyuki Oka, Kazuyuki Miyabe
  • Patent number: 10109235
    Abstract: The present invention relates to the field of display apparatus, more specifically, to a compensation circuit, an AMOLED structure and a display device. Said circuit comprises a plurality of pixel units, each for the plurality of pixel units includes at least one light emitter, and each of said pixel units comprises: an anode initialization signal interface, a CST initialization port, a data control port and an enable signal control port. Compared with the prior art, the advantages of the present invention are: according to the invention, there is no need to individually set up an anode initialization signal line, the umber of the signal lines are reduced from 4 to 3, which is benefit for achieving the design of the product HPPI. And the signal control lines reduce the space occupied by jumper wire during the connection process, which is benefit to the design of narrow border products.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: October 23, 2018
    Assignee: EVERDISPLAY OPTRONICS (SHANGHAI) LIMITED
    Inventors: Nana Xiong, Yu-Hsiung Feng, Jiangang Wang
  • Patent number: 10103515
    Abstract: A vertical cavity surface emitting laser includes: a substrate; and a laminated body which is provided over the substrate, wherein the laminated body includes a first mirror layer provided over the substrate, an active layer provided over the first mirror layer, and a second mirror layer provided over the active layer, in a plan view, the laminated body includes a first portion having a first width, a second portion having a second width, and a third portion which is provided between the first portion and the second portion and has a third width wider than the first width or the second width, and a resin layer which covers at least one portion of the first portion is provided.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: October 16, 2018
    Inventors: Tsuyoshi Kaneko, Tetsuo Nishida, Yuji Kurachi
  • Patent number: 10074787
    Abstract: A light emitting diode is disclosed. The light emitting diode includes: a plurality of light emitting cells including a first light emitting cell and a second light emitting cell spaced apart from each other on a single substrate; a continuous passivation layer formed over the upper surface and one facet of the first light emitting cell, the upper surface and the other facet of the second light emitting cell, and the substrate; and an interconnection layer formed on the passivation layer to electrically connect the first light emitting cell to the second light emitting cell. The interconnection layer includes an edge lump portion formed around a first edge where the upper surface and the one facet of the first light emitting cell meet each other or a second edge where the upper surface and the other facet of the second light emitting cell meet each other.
    Type: Grant
    Filed: April 16, 2017
    Date of Patent: September 11, 2018
    Assignee: LUMENS CO., LTD.
    Inventor: Dae Won Kim
  • Patent number: 10069054
    Abstract: A wiring substrate includes ceramic layers and a conductive member. The ceramic layers have an uppermost ceramic layer and a lowermost ceramic layer. The conductive member includes an upper conductive layer, an internal conductive layer, a lower conductive layer, vias, and a covering layer. The upper conductive layer is disposed on an upper surface of the uppermost ceramic layer. The internal conductive layer is interposed between the ceramic layers. The lower conductive layer is disposed on a lower surface of the lowermost ceramic layer. The vias connect the upper conductive layer, the internal conductive layer, and the lower connective layer. The covering layer covers a portion of the upper conductive layer. The upper conductive layer includes a covered region covered with the covering layer and an element mount region. An upper surface of the element mount region is higher than an upper surface of the covered portion.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: September 4, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Takuya Nakabayashi, Hiroto Tamaki
  • Patent number: 10062806
    Abstract: We propose a method of producing a III nitride semiconductor light-emitting device including a p-type semiconductor layer, in which the p-type semiconductor layer is formed by the steps comprising: an electron blocking layer formation step for forming an electron blocking layer made of AlyGa1-yN (b<y?1) on a light emitting layer; and a p-type contact formation step for forming a p-type contact layer which is AlxGa1-xN (0?x?0.1), directly on the electron blocking layer, and in which the electron blocking layer formation step is performed using a carrier gas containing hydrogen as a main component, and the p-type contact formation step is performed using a carrier gas containing nitrogen as a main component.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: August 28, 2018
    Assignee: DOWA Electronics Materials Co., Ltd.
    Inventors: Takehiko Fujita, Yasuhiro Watanabe
  • Patent number: 10056357
    Abstract: A semiconductor light emitting device includes an LED chip, which includes an n-type semiconductor layer, active layer, and p-type semiconductor layer stacked on a substrate. The LED chip further includes an anode electrode connected to the p-type semiconductor, and a cathode connected to the n-type semiconductor. The anode and cathode electrodes face a case with the LED chip mounted thereon. The case includes a base member including front and rear surfaces, and wirings including a front surface layer having anode and cathode pads formed at the front surface, a rear surface layer having anode and cathode mounting electrodes formed at the rear surface, an anode through wiring connecting the anode pad and the anode mounting electrode and passing through a portion of the base member, and a cathode through wirings connecting the cathode pad and the cathode mounting electrode and passing through a portion of the base member.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: August 21, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Tomoichiro Toyama
  • Patent number: 10043961
    Abstract: A LED device includes a substrate; a plurality of LED units on the substrate, wherein each LED unit includes: a first semiconductor layer; a second semiconductor layer; a first sidewall; a second sidewall opposite to the first sidewall; and a third sidewall connecting the first and second sidewalls; a first group of conductive connecting structure including n (n is an integer, and n>1) first conductive connecting structures formed on the first sidewall of one of the LED units and electrically connecting the LED units; and a second group of conductive connecting structure including m (m is an integer, m?1, and n?m) second conductive connecting structures formed on the second sidewall of the same one of the LED unit and electrically connecting the LED units; wherein each of the first and the second conductive connecting structures includes a middle part, a first and a second extending parts; wherein the first and the second extending parts have different length.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: August 7, 2018
    Assignee: EPISTAR CORPORATION
    Inventor: Hui-chun Yeh
  • Patent number: 9905734
    Abstract: The structure intended to emit electromagnetic radiation, comprises first and second electrodes configured so as to allow carriers to be injected into at least one semiconductor-based stack with a view to making them recombine in an active zone of the stack in order to form all or some of the electromagnetic radiation to be emitted. The first electrode has at least one first face for injecting carriers into the stack, said face being oriented in a different direction to the direction in which the stack is formed. The second electrode comprise a second face for injecting carriers into the stack, wherein said second injection face comprises a first portion facing the first electrode and a second portion for which the first electrode is not facing, and a dielectric element, making contact with the first electrode, is interposed between at least one part of the first electrode and at least one part of the first portion.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: February 27, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: David Vaufrey
  • Patent number: 9905656
    Abstract: Provided is a semiconductor substrate including a seed layer disposed on a substrate, a buffer layer disposed on the seed layer, a plurality of nitride semiconductor layers disposed on the buffer layer, and at least one stress control layer between the plurality of nitride semiconductor layers. The buffer layer includes a plurality of step regions and at least one heterogeneous region. The plurality of step regions includes the same nitride semiconductor material. The heterogeneous region includes a different nitride semiconductor material from the step regions.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: February 27, 2018
    Assignee: SK Siltron Co., Ltd.
    Inventors: Kye-Jin Lee, Ho-Jun Lee, Young-Jae Choi, Jung-Hyun Eum, Chung-Hyun Lee
  • Patent number: 9905809
    Abstract: It is an object of the invention to provide a light emitting device which can display a superior image in which luminescent color from each light emitting layer is beautifully displayed and power consumption is lowered in a light emitting element in which light emitting layers are stacked. One feature of the invention is that, in a light emitting element which comprises light emitting layers stacked between electrodes, each distance between each light emitting layer and an electrode is approximately oddly multiplied ¼ wavelength by controlling a thickness of a layer provided therebetween to enhance luminous output efficiency. Another feature of the invention is that a drive voltage is lowered using a high conductive material for the layer compared with a conventional element.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: February 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Takeshi Noda, Shunpei Yamazaki
  • Patent number: 9871178
    Abstract: A light-emitting diode device is disclosed, which comprises a substrate including a first surface; a plurality of light-emitting diode units formed on the first surface, each of the light-emitting diode units including a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; and a plurality of conductive connecting structures, spatially separated from each other, wherein one end of one of the plurality of conductive connecting structure is arranged on the second semiconductor layer, directly contacted with the second semiconductor layer, and electrically connected with each other through the second semiconductor layer; wherein another end of the one of the conductive connecting structures is arranged on another light-emitting diode unit, and directly contacted with one of the semiconductor layers of the another light-emitting diode unit.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: January 16, 2018
    Assignee: EPISTAR CORPORATION
    Inventor: Hui-chun Yeh
  • Patent number: 9865775
    Abstract: The light emitting element is provided to comprise: a first conductive type semiconductor layer; a mesa; a current blocking layer; a transparent electrode; a first electrode pad and a first electrode extension; a second electrode pad and a second electrode extension; and an insulation layer partially located on the lower portion of the first electrode, wherein the mesa includes at least one groove formed on a side thereof, the first conductive type semiconductor layer is partially exposed through the groove, the insulation layer includes an opening through which the exposed first conductive type semiconductor layer is at least partially exposed, the first electrode extension includes extension contact portions in contact with the first conductive type semiconductor layer through an opening, and the second electrode extension includes an end with a width different from the average width of the second electrode extension.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 9, 2018
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Duk Il Suh, Ye Seul Kim, Kyoung Wan Kim, Sang Won Woo, Ji Hye Kim
  • Patent number: 9818871
    Abstract: In one embodiment, a semiconductor device comprises one or more defense layers, the one or more defense layers each characterized by at least two lattice constants that are mismatched, wherein a mismatch in the lattice constants causes a destabilizing force that comprises at least one of a tensile force or a compressive force; and a plurality of other layers, wherein at least a sufficient part of the destabilizing force is restrained for the one or more defense layers to remain intact unless reduction in thickness of at least a section of one or more of the plurality of other layers, causes at least some of the destabilizing force that was restrained to no longer be restrained, and consequently at least part of at least one of the one or more defense layers to break.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: November 14, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: Elad Peer, Uri Bear
  • Patent number: 9806230
    Abstract: Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods are disclosed. A method in accordance with a particular embodiment includes forming an SSL (solid state lighting) formation structure having a formation structure coefficient of thermal expansion (CTE), selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material of the interlayer structure based at least in part on the second material having a second material CTE less than the first material CTE. The method can further include forming the interlayer structure over the SSL formation structure by disposing (at least) a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: October 31, 2017
    Assignee: QROMIS, Inc.
    Inventor: Ji-Soo Park
  • Patent number: 9728523
    Abstract: A semiconductor light emitting device includes an LED chip, which includes an n-type semiconductor layer, active layer, and p-type semiconductor layer stacked on a substrate. The LED chip further includes an anode electrode connected to the p-type semiconductor, and a cathode connected to the n-type semiconductor. The anode and cathode electrodes face a case with the LED chip mounted thereon. The case includes a base member including front and rear surfaces, and wirings including a front surface layer having anode and cathode pads formed at the front surface, a rear surface layer having anode and cathode mounting electrodes formed at the rear surface, an anode through wiring connecting the anode pad and the anode mounting electrode and passing through a portion of the base member, and a cathode through wirings connecting the cathode pad and the cathode mounting electrode and passing through a portion of the base member.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: August 8, 2017
    Assignee: Rohm Co., Ltd.
    Inventor: Tomoichiro Toyama
  • Patent number: 9705038
    Abstract: Engineered substrates having epitaxial templates for forming epitaxial semiconductor materials and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming a first semiconductor material at a front surface of a donor substrate. The first semiconductor material is transferred to first handle substrate to define a first formation structure. A second formation structure is formed to further include a second semiconductor material homoepitaxial to the first formation structure. The method can further include transferring the first portion of the second formation structure to a second handle substrate such that a second portion of the second formation structure remains at the first handle substrate.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: July 11, 2017
    Assignee: Quora Technology, Inc.
    Inventors: Vladimir Odnoblyudov, Martin F. Schubert
  • Patent number: 9680062
    Abstract: The invention provides an optoelectronic device adapted to emit ultraviolet light, including an aluminum nitride single crystalline substrate, wherein the dislocation density of the substrate is less than about 105 cm?2 and the Full Width Half Maximum (FWHM) of the double axis rocking curve for the (002) and (102) crystallographic planes is less than about 200 arcsec; and an ultraviolet light-emitting diode structure overlying the aluminum nitride single crystalline substrate, the diode structure including a first electrode electrically connected to an n-type semiconductor layer and a second electrode electrically connected to a p-type semiconductor layer. In certain embodiments, the optoelectronic devices of the invention exhibit a reverse leakage current less than about 10?5 A/cm2 at ?10 V and/or an L80 of at least about 5000 hours at an injection current density of 28 A/cm2.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: June 13, 2017
    Assignee: HexaTech, Inc.
    Inventors: Jinqiao Xie, Baxter Moody, Seiji Mita
  • Patent number: 9680048
    Abstract: A method for producing a radiation-emitting semiconductor component is provided, comprising the following steps: —providing a growth substrate (1), —depositing a nucleation layer (2) on the growth substrate (1), —applying a structured dielectric layer (3) to the nucleation layer (2), —applying an epitaxial layer (4) by means of a FACELO process to the structured dielectric layer (3), —epitaxial growth of an epitaxial layer sequence (5) on the epitaxial layer (4), wherein the epitaxial layer sequence (5) comprises an active zone (6) that is suitable for producing electromagnetic radiation.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: June 13, 2017
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Joachim Hertkorn, Lorenzo Zini
  • Patent number: 9634061
    Abstract: A light emitting diode including a first light emitting cell and a second light emitting cell disposed on a substrate and spaced apart from each other to expose a surface of the substrate, a first transparent layer disposed on and electrically connected to the first light emitting cell, first connection section disposed on a portion of the first light emitting cell, a second connection section disposed on a portion of the second light emitting cell, a first interconnection and a second interconnection electrically connecting the first light emitting cell and the second light emitting cell, and an insulation layer disposed between the first and second interconnections and a side surface of the first light emitting cell.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: April 25, 2017
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Seom Geun Lee, Jong Kyu Kim, Yeo Jin Yoon, Jae Kwon Kim, Mae Yi Kim
  • Patent number: 9590088
    Abstract: A current aperture vertical electron transistor (CAVET) with ammonia (NH3) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: March 7, 2017
    Assignee: The Regents of the University of California
    Inventors: Srabanti Chowdhury, Ramya Yeluri, Christophe Hurni, Umesh K. Mishra, Ilan Ben-Yaacov
  • Patent number: 9553240
    Abstract: A semiconductor light-emitting element includes a first semiconductor layer of a first conductive type, a second semiconductor layer of a second conductive type, a light-emitting layer formed between the first semiconductor layer and the second semiconductor layer, a first electrode connected to the first semiconductor layer, and a second electrode connected to the second semiconductor layer. The second electrode includes an ohmic electrode contacting the second semiconductor layer, and a semiconductor electrode made of a semiconductor layer contacting the ohmic electrode.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: January 24, 2017
    Assignee: NICHIA CORPORATION
    Inventor: Masahiko Sano
  • Patent number: 9520536
    Abstract: Disclosed herein is an LED chip including electrode pads. The LED chip includes a semiconductor stack including a first conductive type semiconductor layer, a second conductive type semiconductor layer on the first conductive type semiconductor layer, and an active layer interposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer; a first electrode pad located on the second conductive type semiconductor layer opposite to the first conductive type semiconductor layer; a first electrode extension extending from the first electrode pad and connected to the first conductive type semiconductor layer; a second electrode pad electrically connected to the second conductive type semiconductor layer; and an insulation layer interposed between the first electrode pad and the second conductive type semiconductor layer. The LED chip includes the first electrode pad on the second conductive type semiconductor layer, thereby increasing a light emitting area.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: December 13, 2016
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Ye Seul Kim, Kyoung Wan Kim, Yeo Jin Yoon, Sang Hyun Oh, Keum Ju Lee, Jin Woong Lee, Da Yeon Jeong, Sang Won Woo
  • Patent number: 9515063
    Abstract: An electrode (109) insulated from a compound semiconductor layer (102) and being in contact with an electrode (101) and a compound semiconductor layer (103) is provided. A lattice constant of the compound semiconductor layer (103) is smaller than both of a lattice constant of the compound semiconductor layer (102) and a lattice constant of a compound semiconductor layer (104), and a lattice constant of a compound semiconductor layer (107) is smaller than both of the lattice constants of the compound semiconductor layer (102) and the lattice constants of the compound semiconductor layer (104). A conduction band energy of the compound semiconductor layer (103) is higher than a conduction band energy of the compound semiconductor layer (104).
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: December 6, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Tadahiro Imada
  • Patent number: 9508902
    Abstract: An optoelectronic semiconductor device in accordance with an embodiment of present invention includes a conversion unit having a first side; an electrical connector; a contact layer having an outer perimeter; and at least three successive discontinuous-regions formed along the outer perimeter and having at least one different factor; wherein the electrical connector, the contact layer, and the discontinuous-regions are formed on the first side of the conversion unit.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: November 29, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Tsun-Kai Ko, Schang-Jing Hon, Chien-Kai Chung, Hui-Chun Yeh, An-Ju Lin, Chien-Fu Shen, Chen Ou
  • Patent number: 9464782
    Abstract: Light panels, and methods of providing the light panels, are described. The described light panels are substantially transparent and can operate as an illumination device or as a solar panel. An example light panel includes a first optic layer for transmitting light; a second optic layer with a reflective surface configured for one of directing light from the first optic layer and directing light to the first optic layer; and a receiving assembly disposed between the first optic layer and the second optic layer. The receiving assembly includes a first receiving layer adjacent to the first optic layer; a second receiving layer adjacent to the second optic layer and separated from the first receiving layer; and a light device coupled to the first receiving layer. The light device can be configured to receive light from the reflective surface or to provide light to the reflective surface.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: October 11, 2016
    Assignee: Morgan Solar Inc.
    Inventors: John Paul Morgan, Stefan Myrskog, Brett Barnes, Michael Sinclair, Nigel Morris
  • Patent number: RE46444
    Abstract: An nitride semiconductor device for the improvement of lower operational voltage or increased emitting output, comprises an active layer comprising quantum well layer or layers and barrier layer or layers between n-type nitride. semiconductor layers and p-type nitride semiconductor layers, wherein said quantum layer in said active layer comprises InxGa1?xN (0<x<1) having a peak wavelength of 450 to 540 nm and said active layer comprises laminating layers of 9 to 13, in which at most 3 layers from the side of said n-type nitride semiconductor layers are doped with an n-type impurity selected from the group consisting of Si, Ge and Sn in a range of 5×1016 to 2×1018/cm3.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: June 20, 2017
    Assignee: NICHIA CORPORATION
    Inventor: Koji Tanizawa