With Heterojunction Patents (Class 257/94)
  • Patent number: 11322648
    Abstract: A method for using a photon source, which includes a semiconductor structure having a first light emitting diode region, a second region including a quantum dot, a first voltage source, and a second voltage source, is provided. The method includes steps of applying an electric field across said first light emitting diode region to cause light emission by spontaneous emission, wherein the light emitted from said first light emitting diode region is absorbed in said second region and produces carriers to populate said quantum dot; and applying a tuneable electric field across said second region to control the emission energy of said quantum dot, wherein the light emitted from the second region exits said photon source.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: May 3, 2022
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: David Julian Peter Ellis, James Lee, Anthony John Bennett, Andrew James Shields
  • Patent number: 11276800
    Abstract: A method for manufacturing light emitting diodes and a light emitting diode are disclosed. In an embodiment a method includes growing an n-conductive n-layer, growing an active zone for generating ultraviolet radiation, growing a p-conductive p-layer, producing a p-type semiconductor contact layer having a varying thickness and having a plurality of thickness maxima directly on the p-type layer and applying an ohmic-conductive electrode layer directly on the semiconductor contact layer, wherein each the n-layer and the active zone is based on AlGaN, the p-layer is based on AlGaN or InGaN and the semiconductor contact layer is a GaN layer, wherein the thickness maxima have an area concentration of at least 104 cm?2 in a top view, and wherein the p-layer is only partially covered by the semiconductor contact layer in the top view.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: March 15, 2022
    Assignee: OSRAM OLED GMBH
    Inventors: Bastian Galler, Jürgen Off
  • Patent number: 11251865
    Abstract: Disclosed herein are methods, devices, and system for beam forming and beam steering within ultra-wideband, wireless optical communication devices and systems. According to one embodiment, a free space optical (FSO) communication apparatus is disclosed. The FSO communication apparatus includes an array of optical sources wherein each optical source of the array of optical sources is individually controllable and each optical source configured to have a transient response time of less than 500 picoseconds (ps).
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 15, 2022
    Assignee: LUMEOVA, INC.
    Inventors: Mohammad Ali Khatibzadeh, Arunesh Goswami, Morteza Abbasi
  • Patent number: 11251336
    Abstract: A semiconductor device includes a semiconductor stack having a first-type semiconductor structure, an active structure, and a second-type semiconductor structure disposed on the first-type semiconductor structure. The second-type semiconductor structure has a doping concentration. A first portion includes a part of the first-type semiconductor structure, the active structure, and the second-type semiconductor structure, and has a current confining region. A second portion includes a part of the first-type semiconductor structure, the active structure, and the second-type semiconductor structure, and includes a first-type heavily doped region in the second-type semiconductor structure. The first-type heavily doped region includes a doping concentration higher than that of the second-type semiconductor structure.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 15, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Hsin-Kang Chen, Jung-Jen Li
  • Patent number: 11217727
    Abstract: The present disclosure relates to a light emitting diode. The light emitting diode comprises a first semiconductor layer, a second semiconductor layer, an active layer, a first electrode, and a second electrode. The active layer is located between the first semiconductor layer and the second semiconductor layer. The first electrode is a first carbon nanotube, the second electrode is a second carbon nanotube. A first extending direction of the first carbon nanotube and a second extending direction of the second carbon nanotube are crossed with each other. A vertical p-n junction or a vertical p-i-n junction is formed by the first semiconductor layer and the second semiconductor layer in a direction perpendicular to the first semiconductor layer.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: January 4, 2022
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jin Zhang, Yang Wei, Shou-Shan Fan
  • Patent number: 11212424
    Abstract: A display driver comprises drop amount calculation circuitry and digital gamma correction circuitry. The drop amount calculation circuitry is configured to calculate a drop amount of a power source voltage supplied to a display panel from a setting value. The digital gamma correction circuitry is configured to perform digital gamma correction on an input image data based on the drop amount.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 28, 2021
    Assignee: Synaptics Incorporated
    Inventors: Satoshi Saito, Kei Miyazawa, Hidefumi Odate, Jiro Shimbo, Kazuyuki Tanimoto
  • Patent number: 11189751
    Abstract: Disclosed is a multi-quantum well structure including a stress relief layer, an electron-collecting layer disposed on the stress relief layer, and an active layer including a first active layer unit that is disposed on the electron-collecting layer. The first active layer unit includes potential barrier sub-layers and potential well sub-layers being alternately stacked, in which at least one of the potential barrier sub-layers has a GaN/Alx1Iny1Ga(1-x1-y1)N/GaN stack, where 0<x1?1 and 0?y1<1, and for the remainder of the potential barrier sub-layers, each of the potential barrier sub-layers is a GaN layer. An LED device including the multi-quantum well structure is also disclosed.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: November 30, 2021
    Assignee: Xiamen San'An Optoelectronics Co., Ltd.
    Inventors: Han Jiang, Yung-Ling Lan, Wen-Pin Huang, Changwei Song, Li-Cheng Huang, Feilin Xun, Chan-Chan Ling, Chi-Ming Tsai, Chia-Hung Chang
  • Patent number: 11183215
    Abstract: A thin film structure (e.g., a near-field transducer), includes a first surface parallel to a substrate on which the thin film structure is deposited and two other surfaces orthogonal to the first surface. The first surface and the two other surfaces have respective first, second, and third selected plane orientations with respective first, second, and third atomic packing factors. The first, second, and third selected plane orientations are selected to maximize an average of the first, second, and third atomic packing factors.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: November 23, 2021
    Assignee: Seagate Technology LLC
    Inventors: Tong Zhao, Li Wan, Michael Christopher Kautzky
  • Patent number: 11152764
    Abstract: An optical device is provided that includes a waveguide layer and at least one grating structure. A coupling coefficient of the at least one grating structure to a fundamental optical mode supported by the waveguide layer is greater than a coupling coefficient of the at least one grating structure to at least one higher order transverse optical mode supported by the waveguide layer.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: October 19, 2021
    Assignee: Freedom Photonics LLC
    Inventors: Gordon Barbour Morrison, Bob Benjamin Buckley
  • Patent number: 11139342
    Abstract: A UV-LED is disclosed. The UV-LED includes a sapphire substrate, a u-GaN buffer layer formed on the sapphire substrate, an n-GaN contact layer formed on the u-GaN buffer layer, an InGaN light emitting layer formed on the n-GaN contact layer, and a p-GaN layer formed on the InGaN light emitting layer. The UV-LED has a quadrate planar shape with at least one side having a chip size of 50 ?m or less.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: October 5, 2021
    Assignee: NITRIDE SEMICONDUCTORS CO., LTD.
    Inventor: Yoshihiko Muramoto
  • Patent number: 11121120
    Abstract: An interposer includes a polycrystalline ceramic core disposed between a first surface and a second surface of the interposer, an adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the adhesion layer, and one or more electrically conductive vias extending from the first surface to the second surface through the polycrystalline ceramic core, the adhesion layer, and the barrier layer.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: September 14, 2021
    Assignee: QROMIS, INC.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens
  • Patent number: 11114586
    Abstract: According to one embodiment, a semiconductor light emitting device includes a substrate, and a multi quantum well layer provided on the substrate, and including a plurality of barrier layers sandwiched between three or more InGaAs well layers and two InGaAs well layers. The barrier layers include at least two regions having different mixed crystal ratios or at least two regions having different thicknesses.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: September 7, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Hideto Sugawara
  • Patent number: 11114596
    Abstract: A light-emitting device includes: a light-emitting element; a coating member that covers the light-emitting element; and two external connection electrodes exposed form a first surface of the coating member. Each of the external connection electrodes includes an electrode buried in the coating member; and a metal layer formed on the electrode. A surface of each of the metal layers is exposed from the first surface of the coating member. The first surface of the coating member includes a plurality of grooves between the external connection electrodes.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: September 7, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Yoshikazu Matsuda, Ryo Suzuki
  • Patent number: 11094888
    Abstract: An organic electroluminescent device including: an anode, a cathode, an emitting layer formed of an organic compound and interposed between the cathode and the anode, and two or more layers provided in a hole-injecting/hole-transporting region between the anode and the emitting layer; of the layers which are provided in the hole-injecting/hole-transporting region, a layer which is in contact with the emitting layer containing a compound represented by the formula (1); and of the layers which are provided in the hole-injecting/hole-transporting region, a layer which is interposed between the anode and the layer which is in contact with the emitting layer containing an amine derivative represented by the formula (2).
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: August 17, 2021
    Assignees: Idemitsu Kosan Co., Ltd., JOLED Inc.
    Inventors: Masahiro Kawamura, Emiko Kambe, Akifumi Nakamura, Yasunori Kijima, Tadahiko Yoshinaga, Shigeyuki Matsunami
  • Patent number: 11081346
    Abstract: A semiconductor structure (100) comprising: a substrate (102), a first layer (106) of AlxGayIn(1-x-y)N disposed on the substrate, stacks (107, 109) of several second and third layers (108, 110) alternating against each other, between the substrate and the first layer, a fourth layer (112) of AlxGayIn(1-x-y)N, between the stacks, a relaxation layer of AIN disposed between the fourth layer and one of the stacks, and, in each of the stacks: the level of Ga of the second layers increases from one layer to the next in a direction from the substrate to the first layer, the level of Ga of the third layers is constant or decreasing from one layer to the next in said direction, the average mesh parameter of each group of adjacent second and third layers increasing from one group to the next in said direction, the thickness of the second and third layers is less than 5 nm.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: August 3, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Matthew Charles
  • Patent number: 11075192
    Abstract: A diode including: first and second doped semi-conductor portions forming a p-n junction, a first part of the first portion being arranged between a second part of the first portion and the second portion; dielectric portions covering side walls of the second portion and the first part of the first portion; a first electrode arranged against outer side walls of the dielectric portions and against side walls of the second part of the first portion, electrically connected to the first portion only by contact with said side walls, and passing through the entire thickness of the first portion; a second optically reflecting electrode electrically connected to the second portion such that the second portion is arranged between the second electrode and the first portion.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: July 27, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Hubert Bono, Jonathan Garcia, Ivan-Christophe Robin
  • Patent number: 11056669
    Abstract: A method of manufacturing a flip-chip light emitting diode includes: providing a transparent substrate and a temporary substrate, and bonding the transparent substrate with the temporary substrate; grinding and thinning the transparent substrate; providing a light-emitting epitaxial laminated layer having a first surface and a second surface opposite to each other, and including a first semiconductor layer, an active layer and a second semiconductor layer; forming a transparent bonding medium layer over the first surface of the light-emitting epitaxial laminated layer, and bonding the transparent bonding medium layer with the transparent substrate; defining a first electrode region and a second electrode region over the second surface of the light-emitting epitaxial laminated layer, and manufacturing a first electrode and a second electrode; and removing the temporary substrate.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 6, 2021
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Shu-Fan Yang, Chun-Yi Wu, Chaoyu Wu
  • Patent number: 11037911
    Abstract: A light emitting device includes a wiring substrate, light emitting elements, light-reflecting films, and a light diffusing member. The light emitting elements are mounted in a matrix on the wiring substrate. Each of the light emitting elements includes a sapphire substrate having a lower surface, first lateral surfaces inclined to the lower surface, and second lateral surfaces perpendicular to the lower surface, and a semiconductor layered structure disposed on the lower surface. The light-reflecting films are respectively disposed on the light emitting elements. The light diffusing member is disposed above the light emitting elements. At least a group of the light emitting elements is arranged such that, in every adjacent ones of the light emitting elements in at least one of a row direction and a column direction, the first lateral surface of the light emitting element faces the second lateral surface of the adjacent light emitting element.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 15, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Motokazu Yamada
  • Patent number: 11011373
    Abstract: A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial III-V layers by epitaxial growth on the epitaxial silicon layer.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: May 18, 2021
    Assignee: QROMIS, INC.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens
  • Patent number: 11004966
    Abstract: A semiconductor device is described. In one embodiment, the device includes a Group-III nitride channel layer and a Group-III nitride barrier layer on the Group-III nitride channel layer, wherein the Group-III nitride barrier layer includes a first portion and a second portion, the first portion having a thickness less than the second portion. A p-doped Group-III nitride gate layer section is arranged at least on the first portion of the Group-III nitride barrier layer and a gate contact formed on the p-doped Group-III nitride gate layer.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: May 11, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Walter Rieger
  • Patent number: 10982823
    Abstract: A lighting system that is part of a headlight module of a motor vehicle includes an array of LED light sources that include no organic materials. Each light source includes a glass lens attached to a phosphor glass converter plate, which itself is attached to an LED die that is flip-chip mounted on a mounting substrate. The converter plate includes phosphor particles embedded in glass. Each lens is disposed laterally over a single LED die. The converter plate is attached to the LED die by a first bonding layer, and the lens is attached to the converter plate by a second bonding layer. Both bonding layers are made of a metal oxide and are thinner than the converter plate. Either each lens does not extend horizontally outside the lateral boundary of each converter plate, or the lens portions centered on each LED die are part of a unitary lens array.
    Type: Grant
    Filed: February 3, 2019
    Date of Patent: April 20, 2021
    Assignee: Bridgelux, Inc.
    Inventor: Tao Xu
  • Patent number: 10985306
    Abstract: A semiconductor chip includes an electrically insulating layer including a first opening and a second opening, an electrically conductive first connection point, and an electrically conductive second connection point, wherein a carrier mechanically connects to a semiconductor body, the active region electrically connects to a first conductor body and a second conductor body, the electrically insulating layer covers the carrier on a side thereof facing away from the semiconductor body, the first connection point electrically connects to the first conductor body through the first opening, the second connection point electrically connects to the second conductor body through the second opening, the first conductor body is at a first distance from a second conductor body, the first connection point is at a second distance from the second connection point, and the first distance is less than the second distance.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: April 20, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Korbinian Perzlmaier, Christian Leirer
  • Patent number: 10978569
    Abstract: A process of forming a nitride semiconductor device is disclosed. The process first deposits a silicon nitride (SiN) film on a semiconductor layer by the lower pressure chemical vapor deposition (LPCVD) technique at a temperature, then, forming an opening in the SiN film for an ohmic electrode. Preparing a photoresist on the SiN film, where the photoresist provides an opening that fully covers the opening in the SiN film, the process exposes a peripheral area around the opening of the SiN film to chlorine (Cl) plasma that may etch the semiconductor layer to form a recess therein. Metals for the ohmic electrode are filled within the recess in the semiconductor layer and the peripheral area of the SiN film. Finally, the metals are alloyed at a temperature lower than the deposition temperature of the SiN film.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: April 13, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Takuma Nakano
  • Patent number: 10971475
    Abstract: A semiconductor package structure includes a plurality of first dies spaced from each other, a molding layer between the first dies, a second die over the plurality of first dies and the molding layer, and an adhesive layer between the plurality of first dies and the second die, and between the molding layer and the second die. A first interface between the adhesive layer and the molding layer and a second interface between the adhesive layer and the plurality of first dies are at different levels.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jeng-Nan Hung, Chun-Hui Yu, Kuo-Chung Yee, Yi-Da Tsai, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh
  • Patent number: 10950781
    Abstract: Disclosed are a method of manufacturing a piezoelectric thin film and a piezoelectric sensor manufactured using the piezoelectric thin film. A piezoelectric sensor according to an embodiment of the present disclosure includes a substrate; a lower electrode formed on the substrate; a two-dimensional perovskite nanosheet seed layer formed on the lower electrode; a ceramic piezoelectric thin film formed on the two-dimensional perovskite nanosheet seed layer; and an upper electrode formed on the ceramic piezoelectric thin film, wherein each of the two-dimensional perovskite nanosheet seed layer and the ceramic piezoelectric thin film has a crystal structure.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: March 16, 2021
    Assignee: Korea University Research and Business Foundation
    Inventors: Sahn Nahm, Jong Hyun Kim, Sang Hyo Kweon, Woong Hee Lee
  • Patent number: 10937928
    Abstract: To provide a nitride semiconductor element having a better contact resistance reduction effect also in the case of a light emitting element containing AlGaN having a high Al composition. The nitride semiconductor element has a substrate 1, a first conductivity type first nitride semiconductor layer 2 formed on the substrate 1, and a first electrode layer 4 formed on the first nitride semiconductor layer 2. The first electrode layer 4 contains aluminum and nickel, and both aluminum and an alloy containing aluminum and nickel are present in a contact surface to the first nitride semiconductor layer 2 or in the vicinity of the contact surface.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: March 2, 2021
    Assignee: ASAHI KASEI KABUSHIKI KAISHA
    Inventors: Aya Yokoyama, Yoshihito Hagihara, Ryosuke Hasegawa, Akira Yoshikawa, Ziyi Zhang, Tomohiro Morishita
  • Patent number: 10931083
    Abstract: An optical apparatus includes a cooling device with a lower clad disposed thereon; a waveguide disposed on the lower clad and including an active waveguide to define a gain section and a passive waveguide to define a wavelength-tunable section; gratings disposed in the lower clad of the wavelength-tunable section; an upper clad disposed on the waveguide; a first upper electrode disposed on the upper clad of the gain section; and a second upper electrode disposed on the upper clad of the wavelength-tunable section. The lower clad of the wavelength-tunable section has a recess region to expose an upper surface of the cooling device, the recess region forming an air gap-having a height of 10 ?m to 80 ?m from the upper surface of the cooling device. The gratings are formed in a depth of at least 5 ?m from a bottom surface of the lower clad of the recess region.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 23, 2021
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Oh Kee Kwon, Su Hwan Oh, Chul-Wook Lee, Kisoo Kim
  • Patent number: 10910518
    Abstract: A semiconductor device is provided. The semiconductor device includes a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; an active region between the second semiconductor layer and the first semiconductor layer; an electron blocking structure between the active region and the second semiconductor layer; a first In-containing layer between the active region and the electron blocking structure; and a second In-containing layer between the electron blocking structure and the second semiconductor layer; wherein the first In-containing layer and the second In-containing layer each includes indium, aluminum and gallium, the first In-containing layer has a first aluminum content, the second In-containing layer has a second aluminum content, and the second aluminum content is less than the first aluminum content.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: February 2, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Huan-Yu Lai, Li-Chi Peng
  • Patent number: 10895800
    Abstract: A segmented light or optical power emitting device and an illumination device are described. The segmented device includes a die having a light or optical power emitting semiconductor structure that includes an active layer disposed between an n-layer and a p-layer. Trenches are formed in at least the semiconductor structure and separate the die into individually addressable segments. The active layer emits light or optical power having a first color point or spectrum. At least one wavelength converting layer is adjacent the die and converts the light or optical power to light or optical power having at least one second color point or spectrum and limits an energy ratio of the pump light or optical power that passes through the at least one wavelength converting layer unconverted to total light or optical power emitted by the light or optical power emitting device to less than 10%.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: January 19, 2021
    Assignee: Lumileds LLC
    Inventors: Arjen Gerben Van Der Sijde, Quint Van Voorst Vader, Nicola Pfeffer
  • Patent number: 10825993
    Abstract: An organic light-emitting device includes a first electrode, a second electrode, and an organic layer between the first and second electrodes and including an emission layer, wherein the emission layer comprises a first host represented by Formula 1 and a second host represented by Formula 2:
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: November 3, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-Jee Park, Ji-Hyun Seo
  • Patent number: 10818825
    Abstract: Provided are a method for manufacturing wavelength conversion members that enables manufacturing of wavelength conversion members having a high light extraction efficiency and suppression of material loss, a wavelength conversion member obtained by the method, and a light-emitting device.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: October 27, 2020
    Assignee: NIPPON ELECTRIC GLASS CO., LTD.
    Inventors: Tomomichi Kunimoto, Hideki Asano
  • Patent number: 10811255
    Abstract: Methods of forming semiconductor devices are provided. One of the methods includes following steps. A plurality of hard mask patterns is formed around a region of a substrate, wherein an imaginary connecting line is formed between corners of two of the plurality of hard mask patterns at the same side of the region, and the imaginary connecting line is substantially parallel to or perpendicular to a horizontal direction. A semiconductor layer is formed on the substrate by a selective epitaxial growth process.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Wei Lee, Pang-Yen Tsai, Tsung-Yu Hung
  • Patent number: 10797198
    Abstract: Provided is an infrared light emitting device with high emission intensity. The infrared light emitting device includes: a semiconductor substrate; a first compound semiconductor layer; a light emitting layer containing at least In and Sb and having a predetermined range(s) of Al or Al and Ga proportion(s); a third compound semiconductor layer; and a second compound semiconductor layer containing at least In, Al, and Sb and having a predetermined range(s) of Al or Al and Ga proportion(s), in which the first compound semiconductor layer includes, in the stated order, a first A layer, a first B layer, and a first C layer, each containing at least In and Sb and having a predetermined range(s) of Al or Al and Ga proportion(s), and the proportion(s) of the Al composition or the Al composition and the Ga composition of each layer satisfy a predetermined relation(s).
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: October 6, 2020
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Yoshiki Sakurai, Osamu Morohara, Hiromi Fujita
  • Patent number: 10790412
    Abstract: A manufacturing method of a light-emitting device includes steps of: providing a substrate with a top surface, wherein the top surface comprises a plurality of concavo-convex structures; forming a semiconductor stack on the top surface; forming a trench in the semiconductor stack to define a plurality of second semiconductor stacks and expose a first upper surface; forming a scribing region which extends from the first upper surface into the semiconductor stack and exposes a side surface of the semiconductor stack to define a plurality of first semiconductor stacks; removing a portion of the plurality of first semiconductor stacks and a portion of the concavo-convex structures trough the region to form a first side wall of each of the first semiconductor stack; and dividing the substrate along the region; wherein the first side wall and the top surface form an acute angle ? between thereof, 30°???80°.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: September 29, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Yen-Tai Chao, Sen-Jung Hsu, Tao-Chi Chang, Wei-Chih Wen, Ou Chen, Chun-Hsiang Tu, Yu-Shou Wang, Jing-Feng Huang
  • Patent number: 10784398
    Abstract: A vertical current mode solid state device comprising a connection pad and side walls comprising a metal-insulator-semiconductor (MIS) structure, wherein leakage current effect of the vertical device is limited through the side walls by biasing the MIS structure.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: September 22, 2020
    Assignee: VUEREAL INC.
    Inventors: Gholamreza Chaji, Ehsanollah Fathi, Hossein Zamani Siboni
  • Patent number: 10746926
    Abstract: An optical waveguide substrate 1 includes an optical waveguide 9 composed of a multi-layered film 4 of a plurality of optical material films 5, 6 and having end faces onto which a light is made incident or from which the light is emitted. The end face is an etched surface, and it is provided, on the end face, an unevenness 7 corresponding to a difference of etching rates of the optical material films.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: August 18, 2020
    Assignee: NGK INSULATORS, LTD.
    Inventors: Keiichiro Asai, Shoichiro Yamaguchi
  • Patent number: 10734225
    Abstract: A nitride semiconductor substrate includes a sapphire substrate and a nitride semiconductor layer formed thereon and containing a group III element including Al and nitrogen as a main component. A surface of the sapphire substrate where the nitride semiconductor layer is formed includes recesses having a maximum opening size of from 2 nm to 60 nm in an amount of from 1×109 pieces to 1×1011 pieces per cm2. The recesses and surfaces immediately above the recesses form spaces. Of a surface of the nitride semiconductor layer on the sapphire substrate side, a height difference ?H between a surface immediately above of each recess and a surface in contact with a flat surface is 10 nm or less. A portion of the nitride semiconductor layer above each recess has a crystalline structure produced by growth along a polar plane of the group III element.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: August 4, 2020
    Assignee: ASAHI KASEI KABUSHIKI KAISHA
    Inventors: Akira Yoshikawa, Tomohiro Morishita, Motoaki Iwaya
  • Patent number: 10714655
    Abstract: LED structures are disclosed to reduce non-radiative sidewall recombination along sidewalls of vertical LEDs including p-n diode sidewalls that span a top current spreading layer, bottom current spreading layer, and active layer between the top current spreading layer and bottom current spreading layer.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: July 14, 2020
    Assignee: Apple Inc.
    Inventors: David P. Bour, Kelly McGroddy, Daniel Arthur Haeger, James Michael Perkins, Arpan Chakraborty, Jean-Jacques P. Drolet, Dmitry S. Sizov
  • Patent number: 10707379
    Abstract: An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include an n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary, which has a shape including a plurality of interconnected fingers. The n-type semiconductor layer can have a shape at least partially defined by the mesa boundary. A first n-type contact layer can be located adjacent to another portion of the n-type semiconductor contact layer, where the first n-type contact layer forms an ohmic contact with the n-type semiconductor layer. A second contact layer can be located over a second portion of the n-type semiconductor contact layer, where the second contact layer is formed of a reflective material.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: July 7, 2020
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexander Dobrinsky, Maxim S. Shatalov, Mikhail Gaevski, Michael Shur
  • Patent number: 10670941
    Abstract: Provided are an optical modulation device and a method of operating the same. The optical modulation device may include a nano-antenna, a conductor, and an active layer located between the nano-antenna and the conductor. The optical modulation device may further include a first dielectric layer located between the active layer and the conductor and a second dielectric layer located between the active layer and the nano-antenna. The optical modulation device may further include a signal applying unit configured to independently apply an electrical signal to at least two of the nano-antenna, the active layer, and the conductor.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghyun Park, Jisoo Kyoung, Sunil Kim, Changgyun Shin, Byunggil Jeong, Byounglyong Choi
  • Patent number: 10665755
    Abstract: A method for manufacturing a light emitting device is provided. The method includes: preparing a growth substrate with at least one dislocation-controlling feature thereon; sequentially growing a second type semiconductor layer, an active layer, and a first type semiconductor layer on the dislocation-controlling feature, wherein the active layer has a first region and at least one second region, and the dislocation-controlling feature causes a threading dislocation density of the first region to be greater than a threading dislocation density of the second region; and modifying a resistivity of the first type semiconductor layer, so that the resistivity of the first type semiconductor layer increases from a plurality of low resistance portions toward a high resistance portion of the first type semiconductor layer.
    Type: Grant
    Filed: May 19, 2019
    Date of Patent: May 26, 2020
    Assignee: MIKRO MESA TECHNOLOGY CO., LTD.
    Inventor: Li-Yi Chen
  • Patent number: 10644194
    Abstract: Disclosed in an embodiment are a light emitting device, and a light emitting device package and a light emitting module having the same. According to an embodiment, the light emitting device comprises: a first superlattice layer arranged on an AlN template layer, and a first semiconductor layer, a second superlattice layer, and a first conductive semiconductor layer; an active layer having a quantum well layer and a quantum wall layer arranged on the first conductive semiconductor layer; and an electron blocking layer arranged on the active layer and a second conductive semiconductor layer. A first and second layers of the first superlattice layer, the first semiconductor layer, and third and fourth layers of the second superlattice layer include AlGaN-based semiconductors, and an aluminum composition of the third layer is higher than an aluminum composition of the fourth layer and has the same composition range as that of an aluminum composition of the first semiconductor layer.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: May 5, 2020
    Assignee: LG Innotek Co., Ltd.
    Inventors: Myung Hee Kim, Jung Yeop Hong
  • Patent number: 10636663
    Abstract: A technique that recovers from degradation in crystalline nature in an ion-implanted region is provided. A method of manufacturing a semiconductor device, includes: an ion implantation step of ion-implanting p-type impurities by a cumulative dose D into an n-type semiconductor layer containing n-type impurities; and a thermal annealing step of annealing an ion-implanted region of the n-type semiconductor layer where the p-type impurities are ion-implanted, in an atmosphere containing nitrogen, at a temperature T for a time t, wherein the cumulative dose D, the temperature T, and the time t satisfy a predetermined relationship.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: April 28, 2020
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Takahiro Fujii, Masayoshi Kosaki, Takaki Niwa
  • Patent number: 10612161
    Abstract: A disk-shaped GaN substrate has a diameter of 2 inches or more has a front surface tilted with a tilt angle of 45° or more and 135° or less relative to the (0001) plane in a tilt direction within a range of ±5° around the <10-10> direction, and a back surface which is a main surface opposite to the front surface. The GaN substrate has a first point positioned in a direction perpendicular to the c-axis when viewed from the center thereof, on the side surface thereof. A single diffraction peak appears in an X-ray diffraction pattern obtained by ? scan in which an X-ray (CuK?1: wavelength: 0.1542 nm) is incident to the first point and the incident angle ? of the incident X-ray is varied while the 2? angle of the diffracted X-ray is fixed to twice the Bragg angle of 28.99° of the {11-20} plane.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: April 7, 2020
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Tetsuharu Kajimoto, Yusuke Tsukada, Masayuki Tashiro
  • Patent number: 10593901
    Abstract: A process for improving the external quantum efficiency of a light emitting diode (LED) is provided by exposing one or more components of an LED, a partially assembled LED, or a completely assembled LED to an amount of hydrogen or hydrogen gas, or to an atmosphere containing higher quantities of hydrogen or hydrogen gas for a period of exposure time. Kits and processes for constructing a light emitting diode having an improved external quantum efficiency is further provided, which includes exposing one or more components of an LED, a partially assembled LED, or a completely assembled LED to an amount of hydrogen or hydrogen gas, or to an atmosphere containing higher quantities of hydrogen or hydrogen gas for a period of exposure time.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: March 17, 2020
    Assignee: NanoPhotonica, Inc.
    Inventors: Paul H. Holloway, Jake Hyvonen, Jesse R. Manders, Alexandre Titov, Jean Tokarz, Krishna Acharya
  • Patent number: 10587096
    Abstract: A solid-state light source with built-in access resistance modulation is described. The light source can include an active region configured to emit electromagnetic radiation during operation of the light source. The active region can be formed at a p-n junction of a p-type side with a p-type contact and a n-type side with a n-type contact. The light source includes a control electrode configured to modulate an access resistance of an access region located on the p-type side and/or an access resistance of an access region located on the n-type side of the active region. The solid-state light source can be implemented in a circuit, which includes a voltage source that supplies a modulation voltage to the control electrode to modulate the access resistance(s).
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 10, 2020
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Grigory Simin
  • Patent number: 10586902
    Abstract: A light-emitting device includes a light-emitting structure with a side surface, and a reflective layer covering the side surface. The light-emitting structure has a first light-emitting angle and a second light-emitting angle. The difference between the first light-emitting angle and the second light-emitting angle is larger than 15°.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 10, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chien-Liang Liu, Ming-Chi Hsu, Shih-An Liao, Chun-Hung Liu, Zhi-Ting Ye, Cheng-Teng Ye, Po-Chang Chen, Sheng-Che Chiou
  • Patent number: 10573626
    Abstract: The present disclosure can provide a display device, including a substrate, semiconductor light emitting devices having a first conductive electrode disposed on the substrate and formed in a ring shape on an upper edge thereof and a second conductive electrode formed on an upper central portion of the semiconductor light emitting device and surrounded by the first conductive electrode, a passivation layer formed to cover a side surface of the semiconductor light emitting device, and cover part of an upper surface of the semiconductor light emitting device, a first wiring electrode electrically connected to the first conductive electrode, and a second wiring electrode extended from an edge of the semiconductor light emitting device in a central direction of the semiconductor light emitting device to be electrically connected to the second conductive electrode, wherein part of the second wiring electrode overlaps with part of the first conductive electrode with the passivation layer interposed therebetween.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: February 25, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Junghoon Kim, Byoungkwon Cho
  • Patent number: 10534204
    Abstract: Aspects of the present disclosure are directed to a photorefractive layer stack. A plurality of layers are stacked along in a stacking direction and designed so as to enable a photorefractive response. That is, a refractive index of the plurality of layers modulates in response to illuminating the plurality of layers with an optical pattern of modulated intensity. A plurality of electrically insulated areas are arranged in a plane perpendicular to the stacking direction. The plurality of electrically insulated areas are optically homogenous and prevent lateral diffusion between any two electrically insulated areas of the plurality of electrically insulated areas.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventor: Folkert Horst
  • Patent number: 10535717
    Abstract: A plurality of light emitters emitting different colors of light in a light-emitting device is provided on a surface of a substrate along two dimensions. Each light emitter includes a first electrode, a first charge injection/transport layer, a light-emitting layer, an intermediate layer, a second charge injection/transport layer, and a second electrode. The intermediate layer includes a fluoride of an alkali metal or an alkaline earth metal. Among the first electrode and the second electrode, one electrode is light reflective and another electrode is light transmissive. Among the first charge injection/transport layer and the second charge injection/transport layer, one charge injection/transport layer is disposed between the light-emitting layer and the light reflective electrode, and thickness of the one charge injection/transport layer included in the first light emitter is different from thickness of the one charge injection/transport layer included in the second light emitter.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: January 14, 2020
    Assignee: JOLED INC.
    Inventor: Takahiro Komatsu