More Than Two Heterojunctions In Same Device Patents (Class 257/97)
  • Patent number: 12157115
    Abstract: Monodisperse polystyrene microspheres are self-assembled on a conductive surface of FTO glass by vertical deposition method to prepare three-dimensional ordered photonic crystal opal template; the three-dimensional ordered photonic crystal opal template is immersed in a solution containing rhodium source, titanium source and strontium source, and is then calcined to prepare a rhodium doped strontium titanate inverse opal material; and the rhodium doped strontium titanate inverse opal material is added to water containing pollutants, and is then subjected to illumination and/or ultrasonic treatment to complete the removal of the pollutants in the water. The three-dimensional ordered macroporous rhodium doped strontium titanate inverse opal material may be applied in the field of photocatalysis.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: December 3, 2024
    Assignee: SOOCHOW UNIVERSITY
    Inventors: Jianmei Lu, Najun Li
  • Patent number: 12155172
    Abstract: Provided here are: a mounting member having a front surface on which a diffusion bonding layer is formed; an optical semiconductor element provided with a light emitting part therein, and having a rear surface on which a diffusion bonding layer is formed; and an electrode layer formed from the diffusion bonding layer and the diffusion bonding layer by diffusion bonding therebetween; wherein, in the optical semiconductor element, the light emitting part is provided near a side of the optical semiconductor element so as to be displaced toward the mounting member. This configuration not only makes unnecessary the use of a solder, an Ag paste and the like to thereby prevent the light emitting part in the optical semiconductor element from being contaminated by the solder, but also allows the light emitting part to be closer to the mounting member-side to thereby achieve improvement in heat-dissipation capability.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: November 26, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masato Negishi
  • Patent number: 12140278
    Abstract: Optical filters are used to compensate for changes in LED and pcLED performance resulting from technological advances in device design or manufacturing, with for example the filtered optical output from later generation devices matching or substantially matching the optical performance of earlier generation legacy devices. This can allow the advanced generation devices to be substituted in applications previously supported by the legacy devices, even if the optical performance of the unfiltered advanced generation devices does not satisfy the optical performance specifications required by the application. Somewhat paradoxically, the advantages of using the filters in combination with the advanced generation devices may arise from the filters making the optical performance of the devices worse according to one or more figures of merit.
    Type: Grant
    Filed: May 31, 2024
    Date of Patent: November 12, 2024
    Assignee: Lumileds LLC
    Inventors: Antonio Lopez-Julia, Thomas Diederich, Rémi Guillebot, Aimi Abass, Niels Jeroen van der Veen
  • Patent number: 12136685
    Abstract: A process for mounting a light component on a carrier. The light component includes a generally planar substrate, on a first face of which submillimetre-sized electroluminescent semiconductor elements are epitaxied in the form of a matrix. The process is noteworthy in that it eliminates the need for a layer of filler material between the component and the carrier, while providing good thermal and electrical conductivity between the component and the carrier and high mechanical strength.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: November 5, 2024
    Assignee: VALEO VISION
    Inventors: Nicolas Lefaudex, Antoine De Lamberterie, Guillaume Thin, Samira Mbata, Thomas Canonne, Van Thai Hoang, Vincent Dubois, Francois-Xavier Amiel
  • Patent number: 12132146
    Abstract: A GaN based LED, with an active region of the LED containing one or more quantum wells (QWs), with the QWs separated by higher energy barriers, with some of the barriers doped and some of the barriers not doped, may be driven at high data rates with low drive current densities. Preferably the barriers that are not doped are the barriers closest to one side of a p region or an n region of the LED. With Mg doping, preferably the barriers that are not doped are the barriers closest to the p region of the LED.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: October 29, 2024
    Assignee: AvicenaTech, Corp.
    Inventors: Bardia Pezeshki, Cameron Danesh
  • Patent number: 12100935
    Abstract: A method of fabricating at least one radiation emitter including fabricating a layer stack that includes a first reflector, an active region, an oxidizable layer, and a second reflector; and locally removing the layer stack, and thereby forming at least one mesa. The mesa includes the first reflector, the active region, the oxidizable layer and the second reflector. Before or after locally removing the layer stack and forming the mesa the following steps are carried out: vertically etching at least three blind holes inside the layer stack, wherein the blind holes vertically extend to and expose the oxidizable layer; and oxidizing the oxidizable layer via the sidewalls of the blind holes in lateral direction. An oxidation front radially moves outwards from each hole. The etching is terminated before the entire oxidizable layer is oxidized, thereby forming at least one unoxidized aperture that is limited by at least three oxidation fronts.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: September 24, 2024
    Assignee: Changchun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of Sciences
    Inventors: Gunter Larisch, Sicong Tian, Dieter Bimberg
  • Patent number: 12057535
    Abstract: An array of light emitting devices is mounted on a support surface with the transparent growth substrate (e.g., sapphire) facing up. A photoresist layer is then deposited over the top surface of the growth substrate, followed by depositing a reflective material over the top and side surfaces of the light emitting devices to encapsulate the light emitting devices. The top surfaces of the light emitting devices are then ground down to remove the reflective material over the top surface of the photoresist. The photoresist is then dissolved to leave a cavity over the growth substrate having reflective walls. The cavity is then filled with a phosphor. The phosphor-converted light emitting devices are then singulated to form packaged light emitting devices. All side light is reflected back into the light emitting device by the reflective material and eventually exits the light emitting device toward the phosphor. The packaged light emitting devices, when energized, appear as a white dot with no side emission (e.g.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: August 6, 2024
    Assignee: Lumileds LLC
    Inventors: Iwan-Wahyu Saputra, Yeow-Meng Teo
  • Patent number: 12021171
    Abstract: A micro light emitting diode including an epitaxy layer, a first pad, a second pad, a first ohmic contact metal, a second ohmic contact metal and at least one etch protection conductive layer is provided. The first pad and the second pad are electrically connected to a first type semiconductor layer and a second type semiconductor layer of the epitaxy layer, respectively. The first ohmic contact metal is disposed between the first type semiconductor layer and the first pad. The second ohmic contact metal is disposed between the second type semiconductor layer and the second pad. The at least one etch protection conductive layer is disposed between the first ohmic contact metal and the first pad and/or between the second ohmic contact metal and the second pad. A display panel is also provided.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: June 25, 2024
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Tzu-Yang Lin, Yen-Chun Tseng, Yun-Syuan Chou, Fei-Hong Chen, Pai-Yang Tsai, Jian-Zhi Chen
  • Patent number: 12015110
    Abstract: An array of light emitting devices is mounted on a support surface with the transparent growth substrate (e.g., sapphire) facing up. A photoresist layer is then deposited over the top surface of the growth substrate, followed by depositing a reflective material over the top and side surfaces of the light emitting devices to encapsulate the light emitting devices. The top surfaces of the light emitting devices are then ground down to remove the reflective material over the top surface of the photoresist. The photoresist is then dissolved to leave a cavity over the growth substrate having reflective walls. The cavity is then filled with a phosphor. The phosphor-converted light emitting devices are then singulated to form packaged light emitting devices. All side light is reflected back into the light emitting device by the reflective material and eventually exits the light emitting device toward the phosphor. The packaged light emitting devices, when energized, appear as a white dot with no side emission (e.g.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: June 18, 2024
    Assignee: Lumileds LLC
    Inventors: Iwan-Wahyu Saputra, Yeow-Meng Teo
  • Patent number: 12002906
    Abstract: The present disclosure provides a semiconductor device and a semiconductor component. The semiconductor device includes an active structure, a ring-shaped semiconductor contact layer, a first electrode, and an insulating layer. The active structure has a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer located between the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer. The ring-shaped semiconductor contact layer is located on the second-conductivity-type semiconductor layer and having a first inner sidewall and a first outer sidewall. The first electrode has an upper surface and covers the ring-shaped semiconductor contact layer. The insulating layer covers the first electrode and the active structure and has a second inner sidewall and a second outer sidewall. The first inner sidewall is not flush with the second inner sidewall in a vertical direction.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: June 4, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Hao-Chun Liang, Wei-Shan Yeoh, Yao-Ning Chan, Yi-Ming Chen, Shih-Chang Lee
  • Patent number: 11923454
    Abstract: An epitaxial structure includes a substrate, a lower super-lattice laminate, a middle super-lattice laminate, an upper super-lattice laminate and a channel layer. The lower super-lattice laminate includes a plurality of first lower film layers and a plurality of second lower film layers stacked alternately. The first lower film layer includes aluminum nitride. The second lower film layer includes aluminum gallium nitride. The middle super-lattice laminate includes a plurality of first middle film layers and a plurality of second middle film layers stacked alternately. The first middle film layer includes aluminum nitride. The second middle film layer includes gallium nitride doped with a doping material. The upper super-lattice laminate includes a plurality of first upper film layers and a plurality of second upper film layers stacked alternately. The first upper film layer includes gallium nitride doped with the doping material. The second upper film layer includes gallium nitride.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 5, 2024
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Wei-Jie Sie, Jia-Zhe Liu, Ying-Ru Shih
  • Patent number: 11921298
    Abstract: A spot-size converter includes first and second waveguide structures. The first waveguide structure extends longitudinally along a waveguide axis from a first end to a second end and is configured to support a first optical mode at the first end. The second waveguide structure is formed within the first waveguide structure. The second waveguide structure extends longitudinally between the first end and the second end. The second waveguide structure is configured to support a second optical mode at the second end. The second optical mode has a different diameter than the first optical mode. The second waveguide structure includes a waveguide core that has a first cross-sectional area in a first plane normal to the waveguide axis at the first end and a second cross-sectional area in a second plane normal to the waveguide axis at the second end. The second cross-sectional area is larger than the first cross-sectional area.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 5, 2024
    Assignee: II-VI DELAWARE, INC.
    Inventors: Yasuhiro Matsui, Shiyun Lin, David Adams
  • Patent number: 11901483
    Abstract: An optoelectronic semiconductor structure (SC) comprises an active InGaN-based layer disposed between an n-type injection layer and a p-type injection layer, the active p-type injection layer comprising a first InGaN layer and, disposed on the first layer, a second layer composed of a plurality of AlGaInN elemental layers, each elemental layer having a thickness less than its critical relaxation thickness, two successive elemental layers having different aluminum and/or indium and/or gallium compositions.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: February 13, 2024
    Assignee: Soitec
    Inventor: Mariia Rozhavskaia
  • Patent number: 11817521
    Abstract: In one aspect, a method includes forming an electrical path between p-type mercury cadmium telluride and a metal layer. The forming of the electrical path includes depositing a layer of polycrystalline p-type silicon directly on to the p-type mercury cadmium telluride and forming the metal layer on the layer of polycrystalline p-type silicon. In another aspect, an apparatus includes an electrical path. The electrical path includes a p-type mercury cadmium telluride layer, a polycrystalline p-type silicon layer in direct contact with the p-type mercury cadmium telluride layer, a metal silicide in direct contact with the polycrystalline p-type silicon layer, and an electrically conductive metal on the metal silicide. In operation, holes, indicative of electrical current on the electrical path, flow from the p-type mercury cadmium telluride layer to the electrically conductive metal.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: November 14, 2023
    Assignee: Raytheon Company
    Inventors: Andrew Clarke, David R. Rhiger, Chad W. Fulk, Stuart B. Farrell, James Pattison, Jeffrey M. Peterson, Chad M. Althouse
  • Patent number: 11817527
    Abstract: An optical device includes a multilayered GaAs structure including a plurality of sublayers and an optical structure layer on the multilayered GaAs structure, the optical structure layer including a Group III-V compound semiconductor material. The optical structure layer may be, for example, a light-emitting layer having a multi-quantum well structure.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: November 14, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changyoung Park, Sanghun Lee
  • Patent number: 11777275
    Abstract: A device and a method to produce an augmented-laser (ATLAS) comprising a bi-stable resistive system (BRS) integrated in series with a semiconductor laser. The laser exhibits reduction/inhibition of the Spontaneous Emission (SE) below lasing threshold by leveraging the abrupt resistance switch of the BRS. The laser system comprises a semiconductor laser and a BRS operating as a reversible switch. The BRS operates in a high resistive state in which a semiconductor laser is below a lasing threshold and emitting in a reduced spontaneous emission regime, and a low resistive state in which a semiconductor laser is above or equal to a lasing threshold and emitting in a stimulated emission regime. The BRS operating as a reversible switch is electrically connected in series across two independent chips or on a single wafer. The BRS is formed using insulator-to-metal transition (IMT) materials or is formed using threshold-switching selectors (TSS).
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: October 3, 2023
    Assignee: International Business Machines Corporation
    Inventors: Julien Frougier, Kangguo Cheng, Ruilong Xie, Chanro Park
  • Patent number: 11764544
    Abstract: A vertical-cavity surface-emitting laser (VCSEL) including a lower mirror, an upper mirror, an active layer interposed between the lower mirror and the upper mirror, an aperture forming layer interposed between the upper mirror and the active layer, and including an oxidation layer and a window layer surrounded by the oxidation layer, a ring-shaped trench passing through the upper mirror, the aperture forming layer, and the active layer to define an isolation region therein, and a plurality of oxidation holes disposed in the isolation region surrounded by the trench, and passing through the upper mirror and the aperture forming layer.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: September 19, 2023
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Ki Hwang Lee, Byueng Su Yoo, Jeong Rae Ro
  • Patent number: 11744069
    Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks that individually comprise a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises alternating first insulating tiers and second insulating tiers. The lower portion comprises a lowest insulator tier directly above conductor material of a conductor tier. The lowest insulator tier comprises solid carbon and nitrogen-containing material. An immediately-adjacent tier is directly above the solid carbon and nitrogen-containing material of the lowest insulator tier.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Alyssa N. Scarbrough
  • Patent number: 11721954
    Abstract: Provided is a vertical cavity surface emitting laser diode (VCSEL) with low compressive strain DBR layer, including a GaAs substrate, a lower DBR layer, a lower spacer layer, an active region, an upper spacer layer and an upper DBR layer. The lower or the upper DBR layer includes multiple low refractive index layers and multiple high refractive index layers. The lower DBR layer, the lower spacer layer, the upper spacer layer or the upper DBR layer contains AlxGa1-xAs1-yPy, where the lattice constant of AlxGa1-xAs1-yPy is greater than that of the GaAs substrate. This can moderately reduce excessive compressive strain due to lattice mismatch or avoid tensile strain during the epitaxial growth, thereby reducing the chance of deformation and bowing of the VCSEL epitaxial wafer or cracking during manufacturing. Additionally, the VCSEL epitaxial layer can be prevented from generating excessive compressive strain or tensile strain during the epitaxial growth.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: August 8, 2023
    Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.
    Inventors: Chao-Hsing Huang, Yu-Chung Chin, Van-Truong Dai
  • Patent number: 11709314
    Abstract: Photonic devices having a quantum well structure that includes a Group III-N material, and a Al1-xScxN cladding layer disposed on the quantum well structure, where 0<x?0.45, the Al1-xScxN cladding layer having a lower refractive index than the index of refraction of the quantum well structure.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: July 25, 2023
    Assignees: Raytheon BBN Technologies Corp., Raytheon Company
    Inventors: Mohammad Soltani, Eduardo M. Chumbes
  • Patent number: 11703637
    Abstract: A Group III-Nitride quantum well laser including a distributed Bragg reflector (DBR). In some embodiments, the DBR includes Scandium. In some embodiments, the DBR includes Al1-xScxN, which may have 0<x?0.45.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: July 18, 2023
    Assignees: Raytheon BBN Technologies Corp., Raytheon Company
    Inventors: Mohammad Soltani, Eduardo M. Chumbes
  • Patent number: 11658264
    Abstract: A light emitting device includes a substrate; a pattern of a plurality of protrusions protruding from the substrate; a first semiconductor layer provided on the substrate; an active layer provided on the first semiconductor layer; and a second semiconductor layer provided on the active layer, in which each of the protrusions includes a first layer formed integrally with the substrate and protruding from an upper surface of the base substrate; and a second layer provided on the first layer and formed of a material different from that of the first layer.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: May 23, 2023
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Dae Hong Min, Jun Ho Yoon, Woo Cheol Gwak, Jin Woo Huh, Yong Hyun Baek
  • Patent number: 11600969
    Abstract: In order to provide a QCL element operating in the near-infrared wavelength range, the present disclosure provides a quantum cascade laser element 1000 having a semiconductor superlattice structure (QCL structure 100) sandwiched between a pair of conductive sections 20 and 30. The semiconductor superlattice structure serves as an active region that emits electromagnetic waves. The active region has a plurality of unit structures 10U that are stacked on top of each other. Each unit structure includes four well layers 10W1-10W4 of a composition of AlxGa1?xN, separated from each other by barrier layers 10B1-10B5 of a composition of AlyGa1?yN with 0?x<y?1. Both of the conductive sections in the pair of conductive sections have a refractive index lower than that of the active region in which doped TCO inserted as a key role.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: March 7, 2023
    Assignee: RIKEN
    Inventors: Li Wang, Hideki Hirayama
  • Patent number: 11600704
    Abstract: A nitride semiconductor laminate includes: a substrate comprising a group III nitride semiconductor and including a surface and a reverse surface, the surface being formed from a nitrogen-polar surface, the reverse surface being formed from a group III element-polar surface and being provided on the reverse side from the surface; a protective layer provided at least on the reverse surface side of the substrate and having higher heat resistance than the reverse surface of the substrate; and a semiconductor layer provided on the surface side of the substrate and comprising a group III nitride semiconductor. The concentration of O in the semiconductor layer is lower than 1×1017 at/cm3.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: March 7, 2023
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Hajime Fujikura
  • Patent number: 11581269
    Abstract: A semiconductor thin film structure may include a substrate, a buffer layer on the substrate, and a semiconductor layer on the buffer layer, such that the buffer layer is between the semiconductor layer and the substrate. The buffer layer may include a plurality of unit layers. Each unit layer of the plurality of unit layers may include a first layer having first bandgap energy and a first thickness, a second layer having second bandgap energy and a second thickness, and a third layer having third bandgap energy and a third thickness. One layer having a lowest bandgap energy of the first, second, and third layers of the unit layer may be between another two layers of the first, second, and third layers of the unit layer.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: February 14, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Younghwan Park, Jongseob Kim, Joonyong Kim, Junhyuk Park, Dongchul Shin, Jaejoon Oh, Soogine Chong, Sunkyu Hwang, Injun Hwang
  • Patent number: 11482645
    Abstract: A semiconductor light-emitting device includes first and second semiconductor layers and a light-emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer includes a compound semiconductor represented by a compositional formula AlXGa1-XAs (0<X<1). The first semiconductor layer has an n-type conductivity and includes a first impurity of the n-type. The first layer further includes carbon with a lower concentration than a concentration of the first impurity, and oxygen with a lower concentration than the concentration of the first impurity. The second semiconductor layer includes a compound semiconductor represented by a compositional formula AlYGa1-YAs (0<Y<1). The second semiconductor layer has a p-type conductivity and including a second impurity of the p-type. The second semiconductor layer further includes carbon with a concentration substantially equal to the carbon concentration in the first semiconductor layer.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: October 25, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hideto Sugawara, Takanobu Kamakura
  • Patent number: 11404848
    Abstract: A vertical-cavity surface-emitting laser (VCSEL) including a lower mirror, an upper mirror having an insulation region including implanted ions and an isolation region surrounded by the insulation region, an active layer interposed between the lower mirror and the upper mirror, an aperture forming layer interposed between the upper mirror and the active layer, and including an oxidation layer and a window layer surrounded by the oxidation layer, and a plurality of oxidation holes disposed in the isolation region and passing through the upper mirror and the aperture forming layer.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 2, 2022
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Ki Hwang Lee, Jeong Rae Ro, Byueng Su Yoo, Yoon Sang Jeon, Gong Hee Choi
  • Patent number: 11313036
    Abstract: Process for manufacturing a printhead for a 3D manufacturing system that uses metal electrodeposition to construct parts. The printhead may be constructed by depositing layers on top of a backplane that contains control and power circuits. Deposited layers may include insulating layers and an anode layer that contain deposition anodes that are in contact with the electrolyte to drive electrodeposition. Insulating layers may for example be constructed of silicon nitride or silicon dioxide; the anode layer may contain an insoluble conductive material such as platinum group metals and their associated oxides, highly doped semiconducting materials, and carbon based conductors. The anode layer may be deposited using chemical vapor deposition or physical vapor deposition. Alternatively in one or more embodiments the printhead may be constructed by manufacturing a separate anode plane component, and then bonding the anode plane to the backplane.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: April 26, 2022
    Assignee: FABRIC8LABS, INC.
    Inventors: David Pain, Andrew Edmonds, Jeffrey Herman, Charles Pateros, Edward White
  • Patent number: 11313035
    Abstract: Process for manufacturing a printhead for a 3D manufacturing system that uses metal electrodeposition to construct parts. The printhead may be constructed by depositing layers on top of a backplane that contains control and power circuits. Deposited layers may include insulating layers and an anode layer that contain deposition anodes that are in contact with the electrolyte to drive electrodeposition. Insulating layers may for example be constructed of silicon nitride or silicon dioxide; the anode layer may contain an insoluble conductive material such as platinum group metals and their associated oxides, highly doped semiconducting materials, and carbon based conductors. The anode layer may be deposited using chemical vapor deposition or physical vapor deposition. Alternatively in one or more embodiments the printhead may be constructed by manufacturing a separate anode plane component, and then bonding the anode plane to the backplane.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: April 26, 2022
    Assignee: FABRIC8LABS, INC.
    Inventors: David Pain, Andrew Edmonds, Jeffrey Herman, Charles Pateros, David Wirth
  • Patent number: 11049718
    Abstract: The invention relates to a method to reduce the contact resistance of ohmic contact in group III-nitride high-electron mobility transistor (HEMT). A heavily n-type doped nitride layer with modulation doping is epitaxially grown on selected contact regions for use as ohmic contact layer. The method for producing the n++ ohmic contact layer includes at least the following: deposition of nitride HEMT epitaxial structure on substrates (such as SiC, silicon, sapphire, GaN etc), deposition in-situ or ex-situ mask for selective growth of n-contact, selective etching to create of openings within the mask layer, deposition of modulation doped n++ nitride ohmic contact layer followed by ohmic metal deposition. The modulation doping involves alternating epitaxy of high and low doped nitride layers with common n-type dopant such as Ge, Si etc. The modulation doping significantly increases the range of n-type doping without detrimental effect on the material quality of the contact layer.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: June 29, 2021
    Assignee: SUZHOU HAN HUA SEMICONDUCTOR CO., LTD.
    Inventors: Xian-Feng Ni, Qian Fan, Wei He
  • Patent number: 10938177
    Abstract: To provide a two-dimensional photonic crystal surface emitting laser capable of improving characteristics of light to be emitted, in particular, optical output power. The two-dimensional photonic crystal surface emitting laser includes: a two-dimensional photonic crystal including a plate-shaped base member and modified refractive index regions where the modified refractive index regions have a refractive index different from that of the plate-shaped base member and are two-dimensionally and periodically arranged in the base member; an active layer provided on one side of the two-dimensional photonic crystal; and a first electrode and a second electrode provided sandwiching the two-dimensional photonic crystal and the active layer for supplying current to the active layer, where the second electrode covers a region equal to or wider than the first electrode.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 2, 2021
    Assignees: KYOTO UNIVERSITY, ROHM CO., LTD., HAMAMATSU PHOTONICS K.K., MITSUBISHI ELECTRIC CORPORATION
    Inventors: Susumu Noda, Hitoshi Kitagawa, Yong Liang, Akiyoshi Watanabe, Kazuyoshi Hirose
  • Patent number: 10816166
    Abstract: A light source apparatus includes a base substrate made of a metal material, a plurality of light emitting devices provided on a first surface of the base substrate, a frame so provided on the first surface of the base substrate as to surround the plurality of light emitting devices, and a light transmissive member that is provided on a surface of the frame that is opposite the surface thereof on which the base substrate is provided and transmits light emitted from the plurality of light emitting devices, and the frame is so dimensioned that the section modulus corresponding to the cross-sectional shape of the frame is greater than or equal to 0.5 mm3 but smaller than or equal to 7.0 mm3.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: October 27, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Chigusa Takagi
  • Patent number: 10593831
    Abstract: Achieving resistance reduction of a nitride semiconductor multilayer film reflector. In the nitride semiconductor multilayer film reflector, a first semiconductor layer has a higher Al composition than a second semiconductor layer. A first composition-graded layer is interposed between the first and second semiconductor layers so as to be located at a group III element face side of the first semiconductor layer, the first composition-graded layer being adjusted so that its Al composition becomes lower as coming close to the second semiconductor layer. A second composition-graded layer is interposed between the first and second semiconductor layers so as to be located at a nitride face side of the first semiconductor layer. The second composition-graded layer is adjusted so that its Al composition becomes lower as coming close to the second semiconductor layer.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: March 17, 2020
    Assignee: MEIJO UNIVERSITY
    Inventors: Tetsuya Takeuchi, Motoaki Iwaya, Isamu Akasaki
  • Patent number: 10312404
    Abstract: In accordance with embodiments of the invention, at least partial strain relief in a light emitting layer of a III-nitride light emitting device is provided by configuring the surface on which at least one layer of the device grows such that the layer expands laterally and thus at least partially relaxes. This layer is referred to as the strain-relieved layer. In some embodiments, the light emitting layer itself is the strain-relieved layer, meaning that the light emitting layer is grown on a surface that allows the light emitting layer to expand laterally to relieve strain. In some embodiments, a layer grown before the light emitting layer is the strain-relieved layer. In a first group of embodiments, the strain-relieved layer is grown on a textured surface.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 4, 2019
    Assignee: LUMILEDS LLC
    Inventors: Sungsoo Yi, Nathan F. Gardner, Michael R. Krames, Linda T. Romano
  • Patent number: 10193015
    Abstract: Embodiments of the invention include a III-nitride light emitting layer disposed between an n-type region and a p-type region, a III-nitride layer including a nanopipe defect, and a nanopipe terminating layer disposed between the III-nitride light emitting layer and the III-nitride layer comprising a nanopipe defect. The nanopipe terminates in the nanopipe terminating layer.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 29, 2019
    Assignee: LUMILEDS LLC
    Inventors: Patrick Nolan Grillot, Isaac Harshman Wildeson, Tigran Nshanian, Parijat Pramil Deb
  • Patent number: 10026872
    Abstract: A solution for fabricating a device is described. The solution can include fabricating a heterostructure for the device, which includes at least one stress controlling layer. The stress controlling layer can include one or more attributes varies as a function of a lateral position based on a target variation of stresses in a semiconductor layer located directly under the stress controlling layer. Embodiments are further directed to a heterostructure including at least one stress controlling layer and a device including the heterostructure.
    Type: Grant
    Filed: June 5, 2016
    Date of Patent: July 17, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Alexander Dobrinsky
  • Patent number: 9997667
    Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: June 12, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Remigijus Gaska, Jinwei Yang, Michael Shur, Alexander Dobrinsky
  • Patent number: 9853182
    Abstract: Disclosed herein is a light emitting diode (LED) including: a gallium nitride substrate; a gallium nitride-based first contact layer disposed on the gallium nitride substrate; a gallium nitride-based second contact layer; an active layer having a multi-quantum well structure and disposed between the first and second contact layers; and a super-lattice layer having a multilayer structure and disposed between the first contact layer and the active layer. By employing the gallium nitride substrate, the crystallinity of the semiconductor layers can be improved, and in addition, by disposing the super-lattice layer between the first contact layer and the active layer, a crystal defect that may be generated in the active layer can be prevented.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: December 26, 2017
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Seung Kyu Choi, Chae Hon Kim, Jung Whan Jung, Ki Bum Nam, Kenji Shimoyama, Kaori Kurihara
  • Patent number: 9786827
    Abstract: A light-emitting diode package includes a package body. The package body includes an upper insulation substrate including upper conductive patterns, a lower insulation substrate including lower conductive patterns, and middle conductive patterns disposed between the upper insulation substrate and the lower insulation substrate. The package body also includes an upper via disposed in the upper insulation substrate, a lower via disposed in the lower insulation substrate, the upper via and the lower via not overlaid with each other.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 10, 2017
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Jung Hwa Jung, Hee Tak Oh, Do Hyung Kim, You Jin Kwon, Oh Sug Kim
  • Patent number: 9762033
    Abstract: Laser device characterized in that it comprises, as gain medium, a film of colloidal nanocrystals of semiconductor material, wherein said nanocrystals are two-dimensional nanocrystals suitable for forming quantum wells for confinement of the charge carriers in the nanocrystals and having a biexciton gain mechanism.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: September 12, 2017
    Assignee: FONDAZIONE INSTITUTO ITALIANO DI TECHNOLOGIA
    Inventors: Iwan Philemon Wilhelmus Remy Roger Moreels, Joel Quedar Ge Tian Chi Grim, Sotirios Christodoulou, Francesco Di Stasio, Roman Mark Krahne, Liberato Manna, Roberto Cingolani
  • Patent number: 9620671
    Abstract: A nitride semiconductor light emitting element is provided with: a substrate; a buffer layer that is provided on the substrate; a base layer that is provided on the buffer layer; an n-side nitride semiconductor layer that is provided on the base layer; an MQW light emitting layer that is provided on the n-side nitride semiconductor layer; and a p-side nitride semiconductor layer that is provided on the MQW light emitting layer. An x-ray rocking curve half-value width ? (004) with respect to a (004) plane, i.e., the crystal plane of the nitride semiconductor, is 40 arcsec or less, or the x-ray rocking curve half-value width ? (102) with respect to a (102) plane is 130 arcsec or less, and the rate P (80)/P (25) between light output P (25) at 25° C. and light output P (80) at 80° C. with a same operating current is 95% or more.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: April 11, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hiroshi Nakatsu, Tomoya Inoue, Kentaro Nonaka, Toshiaki Asai, Tadashi Takeoka, Yoshihiko Tani
  • Patent number: 9515220
    Abstract: A light emitting diode based on GaN including an active zone located between an n-doped layer and a p-doped layer that together form a p-n junction, wherein the active zone includes at least one n-doped emissive layer.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: December 6, 2016
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventor: Ivan-Christophe Robin
  • Patent number: 9502296
    Abstract: In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: November 22, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Michael A. Briere
  • Patent number: 9490172
    Abstract: In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: November 8, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Michael A. Briere
  • Patent number: 9472719
    Abstract: A light-emitting diode, comprises an active layer for emitting a light with a phase and a peak wavelength ? in air, a reflector, a lower semiconductor stack between the active layer and the reflector, wherein the lower semiconductor stack comprises multiple semiconductor layers, and each of the multiple semiconductor layers has a refractive index ni, a thickness di and two sides each contacting adjacent layers to form two interfaces, wherein each interface has a phase shift when the light passes through the interface.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: October 18, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Yu-Ren Peng, Tzu-Chieh Hsu, Shih-I Chen, Rong-Ren Lee, Hsin-Chan Chung, Wen-Luh Liao, Yi-Chieh Lin
  • Patent number: 9466765
    Abstract: A method of manufacturing a semiconductor light emitting device includes stacking a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer on a substrate; forming a first electrode and a second electrode on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively; forming an insulating layer covering the first and second electrodes and having first and second openings partially exposing surfaces of the first and second electrodes, respectively; and performing a plasma treatment on a surface of the insulating layer and the partially exposed surfaces of the first and second electrodes to form an unevenness portion on the surface of the insulating layer and form an oxygen-depleted layer on the partially exposed surfaces of the first and second electrodes.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: October 11, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju Heon Yoon, Yeon Ji Kim, Yong Seok Kim, Tae Kang Kim, Tae Hun Kim
  • Patent number: 9431575
    Abstract: The embodiment relates to a light-emitting device, a method of manufacturing the same, a light-emitting device package, and a lighting system. A light-emitting device according to the embodiment may include: a first conductive semiconductor layer; a gallium nitride-based superlattice layer on the first conductive semiconductor layer; an active layer on the gallium nitride-based superlattice layer; a second conductive gallium nitride-based layer on the active layer; and a second conductive semiconductor layer on the second conductive gallium nitride-based layer. The second conductive gallium nitride-based layer may include a second conductive GaN layer having a first concentration, a second conductive InxAlyGa(1-x-y)N (0<x<1, 0<y<1) layer having a second concentration and a second conductive AlzGa(1-z)N (0<z<1) layer having a third concentration on the active layer.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: August 30, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Dae Seob Han, Yong Tae Moon, Kwang Sun Baek, A Ra Cho
  • Patent number: 9431477
    Abstract: A method of depositing a high quality low defect single crystalline Group III-Nitride film. A patterned substrate having a plurality of features with inclined sidewalls separated by spaces is provided. A Group III-Nitride film is deposited by a hydride vapor phase epitaxy (HVPE) process over the patterned substrate. The HVPE deposition process forms a Group III-Nitride film having a first crystal orientation in the spaces between features and a second different crystal orientation on the inclined sidewalls. The first crystal orientation in the spaces subsequently overgrows the second crystal orientation on the sidewalls and in the process turns over and terminates treading dislocations formed in the first crystal orientation.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: August 30, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Olga Kryliouk, Yuriy Melnik, Hidehiro Kojiri, Tetsuya Ishikawa
  • Patent number: 9379288
    Abstract: There is provided a semiconductor light emitting device comprising a semiconductor stack having first and second main surfaces opposing each other, and comprising first and second conductivity-type semiconductor layers respectively defining the first and second main surfaces, and an active layer interposed between the first and second conductivity-type semiconductor layers; a plurality of contact holes penetrating the second conductivity-type semiconductor layer and the active layer, and one region of the first conductivity-type semiconductor layer; a first electrode layer disposed on the second main surface of the semiconductor stack, the first electrode layer extending and being connected to the one region of the first conductivity-type semiconductor layer through the contact holes; a second electrode layer disposed between the semiconductor stack and the first electrode layer and connected to the second conductivity-type semiconductor layer; and first and second interconnected bumps.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: June 28, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pun Jae Choi, Jae In Sim, Seok Min Hwang, Jin Hyun Lee, Myong Soo Cho, Ki Yeol Park
  • Patent number: 9269871
    Abstract: Disclosed is a light emitting diode (LED) comprising a light emitting stacked structure and an electrode structure formed to have a pattern on the light emitting stacked structure. The electrode structure of the LED includes a cluster of reflectors disposed along the pattern on the light emitting stacked structure, and a pad material layer formed to entirely cover the reflectors.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: February 23, 2016
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Ye Seul Kim, Da Yeon Jeong, Kyoung Wan Kim, Yeo Jin Yoon, Sang Hyun Oh