More Than Two Heterojunctions In Same Device Patents (Class 257/97)
  • Patent number: 10312404
    Abstract: In accordance with embodiments of the invention, at least partial strain relief in a light emitting layer of a III-nitride light emitting device is provided by configuring the surface on which at least one layer of the device grows such that the layer expands laterally and thus at least partially relaxes. This layer is referred to as the strain-relieved layer. In some embodiments, the light emitting layer itself is the strain-relieved layer, meaning that the light emitting layer is grown on a surface that allows the light emitting layer to expand laterally to relieve strain. In some embodiments, a layer grown before the light emitting layer is the strain-relieved layer. In a first group of embodiments, the strain-relieved layer is grown on a textured surface.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 4, 2019
    Assignee: LUMILEDS LLC
    Inventors: Sungsoo Yi, Nathan F. Gardner, Michael R. Krames, Linda T. Romano
  • Patent number: 10193015
    Abstract: Embodiments of the invention include a III-nitride light emitting layer disposed between an n-type region and a p-type region, a III-nitride layer including a nanopipe defect, and a nanopipe terminating layer disposed between the III-nitride light emitting layer and the III-nitride layer comprising a nanopipe defect. The nanopipe terminates in the nanopipe terminating layer.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 29, 2019
    Assignee: LUMILEDS LLC
    Inventors: Patrick Nolan Grillot, Isaac Harshman Wildeson, Tigran Nshanian, Parijat Pramil Deb
  • Patent number: 10026872
    Abstract: A solution for fabricating a device is described. The solution can include fabricating a heterostructure for the device, which includes at least one stress controlling layer. The stress controlling layer can include one or more attributes varies as a function of a lateral position based on a target variation of stresses in a semiconductor layer located directly under the stress controlling layer. Embodiments are further directed to a heterostructure including at least one stress controlling layer and a device including the heterostructure.
    Type: Grant
    Filed: June 5, 2016
    Date of Patent: July 17, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Alexander Dobrinsky
  • Patent number: 9997667
    Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: June 12, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Remigijus Gaska, Jinwei Yang, Michael Shur, Alexander Dobrinsky
  • Patent number: 9853182
    Abstract: Disclosed herein is a light emitting diode (LED) including: a gallium nitride substrate; a gallium nitride-based first contact layer disposed on the gallium nitride substrate; a gallium nitride-based second contact layer; an active layer having a multi-quantum well structure and disposed between the first and second contact layers; and a super-lattice layer having a multilayer structure and disposed between the first contact layer and the active layer. By employing the gallium nitride substrate, the crystallinity of the semiconductor layers can be improved, and in addition, by disposing the super-lattice layer between the first contact layer and the active layer, a crystal defect that may be generated in the active layer can be prevented.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: December 26, 2017
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Seung Kyu Choi, Chae Hon Kim, Jung Whan Jung, Ki Bum Nam, Kenji Shimoyama, Kaori Kurihara
  • Patent number: 9786827
    Abstract: A light-emitting diode package includes a package body. The package body includes an upper insulation substrate including upper conductive patterns, a lower insulation substrate including lower conductive patterns, and middle conductive patterns disposed between the upper insulation substrate and the lower insulation substrate. The package body also includes an upper via disposed in the upper insulation substrate, a lower via disposed in the lower insulation substrate, the upper via and the lower via not overlaid with each other.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 10, 2017
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Jung Hwa Jung, Hee Tak Oh, Do Hyung Kim, You Jin Kwon, Oh Sug Kim
  • Patent number: 9762033
    Abstract: Laser device characterized in that it comprises, as gain medium, a film of colloidal nanocrystals of semiconductor material, wherein said nanocrystals are two-dimensional nanocrystals suitable for forming quantum wells for confinement of the charge carriers in the nanocrystals and having a biexciton gain mechanism.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: September 12, 2017
    Assignee: FONDAZIONE INSTITUTO ITALIANO DI TECHNOLOGIA
    Inventors: Iwan Philemon Wilhelmus Remy Roger Moreels, Joel Quedar Ge Tian Chi Grim, Sotirios Christodoulou, Francesco Di Stasio, Roman Mark Krahne, Liberato Manna, Roberto Cingolani
  • Patent number: 9620671
    Abstract: A nitride semiconductor light emitting element is provided with: a substrate; a buffer layer that is provided on the substrate; a base layer that is provided on the buffer layer; an n-side nitride semiconductor layer that is provided on the base layer; an MQW light emitting layer that is provided on the n-side nitride semiconductor layer; and a p-side nitride semiconductor layer that is provided on the MQW light emitting layer. An x-ray rocking curve half-value width ? (004) with respect to a (004) plane, i.e., the crystal plane of the nitride semiconductor, is 40 arcsec or less, or the x-ray rocking curve half-value width ? (102) with respect to a (102) plane is 130 arcsec or less, and the rate P (80)/P (25) between light output P (25) at 25° C. and light output P (80) at 80° C. with a same operating current is 95% or more.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: April 11, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hiroshi Nakatsu, Tomoya Inoue, Kentaro Nonaka, Toshiaki Asai, Tadashi Takeoka, Yoshihiko Tani
  • Patent number: 9515220
    Abstract: A light emitting diode based on GaN including an active zone located between an n-doped layer and a p-doped layer that together form a p-n junction, wherein the active zone includes at least one n-doped emissive layer.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: December 6, 2016
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventor: Ivan-Christophe Robin
  • Patent number: 9502296
    Abstract: In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: November 22, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Michael A. Briere
  • Patent number: 9490172
    Abstract: In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: November 8, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Michael A. Briere
  • Patent number: 9472719
    Abstract: A light-emitting diode, comprises an active layer for emitting a light with a phase and a peak wavelength ? in air, a reflector, a lower semiconductor stack between the active layer and the reflector, wherein the lower semiconductor stack comprises multiple semiconductor layers, and each of the multiple semiconductor layers has a refractive index ni, a thickness di and two sides each contacting adjacent layers to form two interfaces, wherein each interface has a phase shift when the light passes through the interface.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: October 18, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Yu-Ren Peng, Tzu-Chieh Hsu, Shih-I Chen, Rong-Ren Lee, Hsin-Chan Chung, Wen-Luh Liao, Yi-Chieh Lin
  • Patent number: 9466765
    Abstract: A method of manufacturing a semiconductor light emitting device includes stacking a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer on a substrate; forming a first electrode and a second electrode on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively; forming an insulating layer covering the first and second electrodes and having first and second openings partially exposing surfaces of the first and second electrodes, respectively; and performing a plasma treatment on a surface of the insulating layer and the partially exposed surfaces of the first and second electrodes to form an unevenness portion on the surface of the insulating layer and form an oxygen-depleted layer on the partially exposed surfaces of the first and second electrodes.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: October 11, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju Heon Yoon, Yeon Ji Kim, Yong Seok Kim, Tae Kang Kim, Tae Hun Kim
  • Patent number: 9431575
    Abstract: The embodiment relates to a light-emitting device, a method of manufacturing the same, a light-emitting device package, and a lighting system. A light-emitting device according to the embodiment may include: a first conductive semiconductor layer; a gallium nitride-based superlattice layer on the first conductive semiconductor layer; an active layer on the gallium nitride-based superlattice layer; a second conductive gallium nitride-based layer on the active layer; and a second conductive semiconductor layer on the second conductive gallium nitride-based layer. The second conductive gallium nitride-based layer may include a second conductive GaN layer having a first concentration, a second conductive InxAlyGa(1-x-y)N (0<x<1, 0<y<1) layer having a second concentration and a second conductive AlzGa(1-z)N (0<z<1) layer having a third concentration on the active layer.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: August 30, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Dae Seob Han, Yong Tae Moon, Kwang Sun Baek, A Ra Cho
  • Patent number: 9431477
    Abstract: A method of depositing a high quality low defect single crystalline Group III-Nitride film. A patterned substrate having a plurality of features with inclined sidewalls separated by spaces is provided. A Group III-Nitride film is deposited by a hydride vapor phase epitaxy (HVPE) process over the patterned substrate. The HVPE deposition process forms a Group III-Nitride film having a first crystal orientation in the spaces between features and a second different crystal orientation on the inclined sidewalls. The first crystal orientation in the spaces subsequently overgrows the second crystal orientation on the sidewalls and in the process turns over and terminates treading dislocations formed in the first crystal orientation.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: August 30, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Olga Kryliouk, Yuriy Melnik, Hidehiro Kojiri, Tetsuya Ishikawa
  • Patent number: 9379288
    Abstract: There is provided a semiconductor light emitting device comprising a semiconductor stack having first and second main surfaces opposing each other, and comprising first and second conductivity-type semiconductor layers respectively defining the first and second main surfaces, and an active layer interposed between the first and second conductivity-type semiconductor layers; a plurality of contact holes penetrating the second conductivity-type semiconductor layer and the active layer, and one region of the first conductivity-type semiconductor layer; a first electrode layer disposed on the second main surface of the semiconductor stack, the first electrode layer extending and being connected to the one region of the first conductivity-type semiconductor layer through the contact holes; a second electrode layer disposed between the semiconductor stack and the first electrode layer and connected to the second conductivity-type semiconductor layer; and first and second interconnected bumps.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: June 28, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pun Jae Choi, Jae In Sim, Seok Min Hwang, Jin Hyun Lee, Myong Soo Cho, Ki Yeol Park
  • Patent number: 9269871
    Abstract: Disclosed is a light emitting diode (LED) comprising a light emitting stacked structure and an electrode structure formed to have a pattern on the light emitting stacked structure. The electrode structure of the LED includes a cluster of reflectors disposed along the pattern on the light emitting stacked structure, and a pad material layer formed to entirely cover the reflectors.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: February 23, 2016
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Ye Seul Kim, Da Yeon Jeong, Kyoung Wan Kim, Yeo Jin Yoon, Sang Hyun Oh
  • Patent number: 9257624
    Abstract: A light emitting diode package includes a package body having a cavity, a light emitting diode chip having a plurality of light emitting cells connected in series to one another, a phosphor converting a frequency of light emitted from the light emitting diode chip, and a pair of lead electrodes. The light emitting cells are connected in series between the pair of lead electrodes.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: February 9, 2016
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Jung Hwa Jung, Hee Tak Oh, Do Hyung Kim, You Jin Kwon, Oh Sug Kim
  • Patent number: 9231073
    Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9196688
    Abstract: In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: November 24, 2015
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Michael A. Briere
  • Patent number: 9190559
    Abstract: According to an embodiment, a semiconductor light emitting device includes a foundation layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer. The foundation layer has an unevenness having recesses, side portions, and protrusions. A first major surface of the foundation layer has an overlay-region. The foundation layer has a plurality of dislocations including first dislocations whose one ends reaching the recess and second dislocations whose one ends reaching the protrusion. A proportion of a number of the second dislocations reaching the first major surface to a number of all of the second dislocations is smaller than a proportion of a number of the first dislocations reaching the first major surface to a number of all of the first dislocations. A number of the dislocations reaching the overlay-region of the first major surface is smaller than a number of all of the first dislocations.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: November 17, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiki Hikosaka, Yoshiyuki Harada, Maki Sugai, Shinya Nunoue
  • Patent number: 9105810
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting unit, a second semiconductor layer, a reflecting electrode, an oxide layer and a nitrogen-containing layer. The first semiconductor layer is of a first conductivity type. The light emitting unit is provided on the first semiconductor layer. The second semiconductor layer is provided on the light emitting unit and is of a second conductivity type. The reflecting electrode is provided on the second semiconductor layer and includes Ag. The oxide layer is provided on the reflecting electrode. The oxide layer is insulative and has a first opening. The nitrogen-containing layer is provided on the oxide layer. The nitrogen-containing layer is insulative and has a second opening communicating with the first opening.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: August 11, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihide Ito, Hiroshi Katsuno, Shinya Nunoue
  • Patent number: 9093609
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting part, and a p-side electrode. The light emitting part is provided between the n-type and the p-type semiconductor layers, and includes a plurality of barrier layers and a plurality of well layers. The p-side electrode contacts the p-type semiconductor layer. The p-type semiconductor layer includes first, second, third, and fourth p-type layers. The first p-type layer contacts the p-side electrode. The second p-type layer contacts the light emitting part. The third p-type layer is provided between the first p-type layer and the second p-type layer. The fourth p-type layer is provided between the second p-type layer and the third p-type layer. The second p-type layer contains Al and contains a p-type impurity in a lower concentration lower than that in the first concentration.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: July 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
  • Patent number: 9059359
    Abstract: Exemplary embodiments of the present invention relate to a photo detection device including a substrate, a first light absorption layer disposed on the substrate, a second light absorption layer disposed in a first region on the first light absorption layer, a third light absorption layer disposed in a second region on the second light absorption layer, and a first electrode layer disposed on each of the first, the second, and the third light absorption layers.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: June 16, 2015
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Ki Yon Park, Hwa Mok Kim, Young Hwan Son, Daewoong Suh
  • Patent number: 9040331
    Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9034207
    Abstract: A phosphor is represented by a general Formula: EuxMyL3?x?ySi6?zAlzN11?(z+y+z)O(z+y+z) and satisfies 0.00001?x?2.9999, 0.0001?y?2.99999 and 0?z?6.0. L is at least one element selected from La, Y, Gd and Lu. M is at least one element selected from Ca, Sr, Ba and Mn.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: May 19, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyong Sik Won, Chan Suk Min, Seong Min Kim, Sung Hak Jo, Youn Gon Park, Chul Soo Yoon
  • Patent number: 9024332
    Abstract: A semiconductor light emitting element has a cross-sectional structure comprising a support substrate, a semiconductor lamination located over the support substrate, and a joint layer located between the semiconductor lamination and the support substrate, containing a first jointing layer located on the semiconductor lamination side and a second jointing layer located on the support substrate side. In the plan view, the semiconductor lamination has corner portions and side portions along the periphery, the first jointing layer is encompassed by the second jointing layer, the second jointing layer is encompassed by the semiconductor lamination, and an annular region defined between outlines of the semiconductor lamination and of the first jointing layer has first portions corresponding to the corner portions of the semiconductor lamination and second portions corresponding to the side portions of the semiconductor lamination, widths of the first portions being narrower than widths of the second portions.
    Type: Grant
    Filed: March 17, 2013
    Date of Patent: May 5, 2015
    Assignee: Stanley Electronic Co., Ltd.
    Inventors: Mamoru Miyachi, Tatsuma Saito, Takako Chinone, Takanobu Akagi
  • Patent number: 9018653
    Abstract: A light emitting device includes a light emitting element and a package. The package is made up of a molded article and a lead that is embedded in the molded article. The lead includes a mounting part on which the light emitting element is mounted, a terminal part that is linked to the mounting part, and an exposed part. The package has a front face that is a light emitting face, a rear face opposite the front face, and a bottom face contiguous with the front face and the rear face. The light emitting element is mounted on the front face side of the mounting part. The exposed part is linked to the rear face side of the mounting part, and is exposed from the molded article at the bottom face and the rear face. The terminal part is exposed from the molded article at the bottom face.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: April 28, 2015
    Assignee: Nichia Corporation
    Inventor: Ryohei Yamashita
  • Patent number: 9012886
    Abstract: According to one embodiment, a semiconductor light emitting device includes: a first semiconductor layer; a second semiconductor layer; and a light emitting layer provided between the first and the second semiconductor layers. The first semiconductor layer includes a nitride semiconductor, and is of an n-type. The second semiconductor layer includes a nitride semiconductor, and is of a p-type. The light emitting layer includes: a first well layer; a second well layer provided between the first well layer and the second semiconductor layer; a first barrier layer provided between the first and the second well layers; and a first Al containing layer contacting the second well layer between the first barrier layer and the second well layer and containing layer containing Alx1Ga1-x1N (0.1?x1?0.35).
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jongil Hwang, Shinji Saito, Rei Hashimoto, Shinya Nunoue
  • Patent number: 9006713
    Abstract: In one aspect, an organic light-emitting display apparatus is provided including a first sub-pixel, a second sub-pixel, and a third sub-pixel that are each a different color, the apparatus including: a substrate; a first electrode disposed on the substrate; a second electrode disposed on the first electrode so as to face the first electrode; an organic emission layer disposed between the first electrode and the second electrode and comprising a first organic emission layer, a second organic emission layer, and a third organic emission layer; a hole transport layer disposed between the first electrode and the organic emission layer; and an electron accepting layer disposed between the first electrode and the second electrode. The organic light-emitting display apparatus has improved image quality and lifetime.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: April 14, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin-Woo Park, Myung-Jong Jung, Sung-Woo Cho, Sang-Woo Pyo, Hyo-Yeon Kim
  • Patent number: 9006779
    Abstract: Disclosed are a nitride semiconductor light-emitting element and a method for manufacturing the same. The nitride semiconductor light-emitting element according to the present invention comprises: a current blocking part disposed between a substrate and an n-type nitride layer; an activation layer disposed on the top surface of the n-type nitride layer; and a p-type nitride layer disposed on the top surface of the activation layer, wherein the current blocking part is an AlxGa(1-x)N layer, and the Al content x times layer thickness (?m) is in the range of 0.01-0.06. Accordingly, the nitride semiconductor light-emitting element can increase the luminous efficiency by having a current blocking part which prevents current leakage from occurring.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: April 14, 2015
    Assignee: Iljin Led Co., Ltd.
    Inventors: Won-Jin Choi, Jung-Won Park
  • Patent number: 9000462
    Abstract: Disclosed is a light emitting device. A light emitting device comprises a plurality of N-type semiconductor layers including a first N-type semiconductor layer and a second N-type semiconductor layer on the first N-type semiconductor layer, an active layer on the second N-type semiconductor layer, and a P-type semiconductor layer on the active layer, wherein the first N-type semiconductor layer comprises a Si doped Nitride layer and the second N-type semiconductor layer comprises a Si doped Nitride layer, and wherein the first and second N-type semiconductor layers have a Si impurity concentration different from each other.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 7, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Tae Yun Kim
  • Patent number: 8994064
    Abstract: A strain release layer adjoining the active layer in a blue LED is bounded on the bottom by a first relatively-highly silicon-doped region and is also bounded on the top by a second relatively-highly silicon-doped region. The second relatively-highly silicon-doped region is a sublayer of the active layer of the LED. The first relatively-highly silicon-doped region is a sublayer of the N-type layer of the LED. The first relatively-highly silicon-doped region is also separated from the remainder of the N-type layer by an intervening sublayer that is only lightly doped with silicon. The silicon doping profile promotes current spreading and high output power (lumens/watt). The LED has a low reverse leakage current and a high ESD breakdown voltage. The strain release layer has a concentration of indium that is between 5×1019 atoms/cm3 and 5×1020 atoms/cm3, and the first and second relatively-highly silicon-doped regions have silicon concentrations that exceed 1×1018 atoms/cm3.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Zhen Chen, Yi Fu
  • Patent number: 8994001
    Abstract: A light emitting device, a method of manufacturing the same, a light emitting device package, and a lighting system are disclosed. The light emitting device may include a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first and second conductive semiconductor layers. The first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer may include Al. The second conductive semiconductor layer may have Al content higher than Al content of the first conductive semiconductor layer. The first conductive semiconductor layer may have Al content higher than Al content of the active layer.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: March 31, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyo Kun Son
  • Patent number: 8993992
    Abstract: A GaN based semiconductor light-emitting device is provided. The light-emitting device includes a first GaN based compound semiconductor layer of an n-conductivity type; an active layer; a second GaN based compound semiconductor layer; an underlying layer composed of a GaN based compound semiconductor, the underlying layer being disposed between the first GaN based compound semiconductor layer and the active layer; and a superlattice layer composed of a GaN based compound semiconductor doped with a p-type dopant, the superlattice layer being disposed between the active layer and the second GaN based compound semiconductor layer.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: March 31, 2015
    Assignee: Sony Corporation
    Inventors: Goshi Biwa, Hiroyuki Okuyama
  • Patent number: 8981340
    Abstract: A nitride semiconductor device according to the present invention includes a p-type nitride semiconductor layer, an n-type nitride semiconductor layer, and an active layer interposed between the p-type nitride semiconductor layer and the n-type nitride semiconductor layer. The p-type nitride semiconductor layer includes: a first p-type nitride semiconductor layer containing Al and Mg; and a second p-type nitride semiconductor layer containing Mg. The first p-type nitride semiconductor layer is located between the active layer and the second p-type nitride semiconductor layer, and the second p-type nitride semiconductor layer has a greater band gap than a band gap of the first p-type nitride semiconductor layer.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: March 17, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yasutoshi Kawaguchi, Toshitaka Shimamoto, Akihiko Ishibashi, Isao Kidoguchi, Toshiya Yokogawa
  • Patent number: 8969849
    Abstract: Provided is a nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed above the first nitride semiconductor layer; and a delta doped second nitride semiconductor layer formed above the active layer. According to the present invention, the optical power of the nitride semiconductor light emitting device is enhanced, optical power down phenomenon is improved and reliability against ESD (electro static discharge) is enhanced.
    Type: Grant
    Filed: March 9, 2014
    Date of Patent: March 3, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Suk Hun Lee
  • Patent number: 8963185
    Abstract: A superstrate, such as a sheet of polymer film, is used as a transport during metallization of solar cells. The back sides of the solar cells are attached to the sheet of polymer film. Contact holes are formed through the sheet of polymer film to expose doped regions of the solar cells. Metals are formed in the contact holes to electrically connect to the exposed doped regions of the solar cells. The metals are electroplated to form metal contacts of the solar cell. Subsequently, the solar cells are separated from other solar cells that were metallized while supported by the same sheet of polymer film to form strings of solar cells or individual solar cells.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: February 24, 2015
    Assignee: SunPower Corporation
    Inventor: Peter John Cousins
  • Patent number: 8952401
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting layer, a second semiconductor layer, and a low refractive index layer. The first semiconductor layer has a first major surface and a second major surface being opposite to the first major surface. The light emitting layer has an active layer provided on the second major surface. The second semiconductor layer is provided on the light emitting layer. The low refractive index layer covers partially the first major surface and has a refractive index lower than the refractive index of the first semiconductor layer.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoharu Sugiyama, Taisuke Sato, Hiroshi Ono, Satoshi Mitsugi, Tomonari Shioda, Jongil Hwang, Hung Hung, Shinya Nunoue
  • Patent number: 8952349
    Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 10, 2015
    Assignee: Crossbar, Inc.
    Inventors: Wei Lu, Sung Hyun Jo
  • Patent number: 8940622
    Abstract: A method for manufacturing a compound semiconductor device, the method includes: forming a compound semiconductor laminated structure; removing a part of the compound semiconductor laminated structure, so as to form a concave portion; and cleaning the inside of the concave portion by using a detergent, wherein the detergent contains a base resin compatible with residues present in the concave portion and a solvent.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: January 27, 2015
    Assignee: Fujitsu Limited
    Inventor: Junichi Kon
  • Patent number: 8937325
    Abstract: According to one embodiment, a semiconductor device includes a first layer of n-type including a nitride semiconductor, a second layer of p-type including a nitride semiconductor, a light emitting unit, and a first stacked body. The light emitting unit is provided between the first and second layers. The first stacked body is provided between the first layer and the light emitting unit. The first stacked body includes a plurality of third layers including AlGaInN, and a plurality of fourth layers alternately stacked with the third layers and including GaInN. The first stacked body has a first surface facing the light emitting unit. The first stacked body has a depression provided in the first surface. A part of the light emitting unit is embedded in a part of the depression. A part of the second layer is disposed on the part of the light emitting unit.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: January 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Kushibe, Yasuo Ohba, Hiroshi Katsuno, Kei Kaneko, Shinji Yamada
  • Patent number: 8928017
    Abstract: Example embodiments are directed to light-emitting devices (LEDs) and methods of manufacturing the same. The LED includes a first semiconductor layer; a second semiconductor layer; an active layer formed between the first and second semiconductor layers; and an emission pattern layer including a plurality of layers on the first semiconductor layer, the emission pattern including an emission pattern for externally emitting light generated from the active layer.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Su-hee Chae, Young-soo Park, Bok-ki Min, Jun-youn Kim, Hyun-gi Hong
  • Patent number: 8916857
    Abstract: A light-emitting element disclosed in the present invention includes a light-emitting layer and a first layer between a first electrode and a second electrode, in which the first layer is provided between the light-emitting layer and the first electrode. The present invention is characterized by the device structure in which the first layer comprising a hole-transporting material is doped with a hole-blocking material or an organic compound having a large dipole moment. This structure allows the formation of a high performance light-emitting element with high luminous efficiency and long lifetime. The device structure of the present invention facilitates the control of the rate of the carrier transport, and thus, leads to the formation of a light-emitting element with a well-controlled carrier balance, which contributes to the excellent characteristics of the light-emitting element of the present invention.
    Type: Grant
    Filed: November 24, 2012
    Date of Patent: December 23, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoko Shitagaki, Satoshi Seo, Ryoji Nomura
  • Patent number: 8906264
    Abstract: The invention relates to compounds of the general formula (I) EA2-xEuxSiO4.aM2B4O7 (I) where EA stands for two or more elements selected from Ca, Sr, Zn and Ba, M stands for Li, Na or K, and a stands for a value from the range 0.01?a?0.08, and x stands for a value from the range 0.01?x?0.25.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: December 9, 2014
    Assignee: Merck Patent GmbH
    Inventors: Tim Vosgroene, Daniela Degenring, Stefan Schlueter, Sascha Hess, Andrea Opolka, Eric Heiden
  • Patent number: 8901612
    Abstract: Embodiments of a thin-film heterostructure thermoelectric material and methods of fabrication thereof are disclosed. In general, the thermoelectric material is formed in a Group IIa and IV-VI materials system. The thermoelectric material includes an epitaxial heterostructure and exhibits high heat pumping and figure-of-merit performance in terms of Seebeck coefficient, electrical conductivity, and thermal conductivity over broad temperature ranges through appropriate engineering and judicious optimization of the epitaxial heterostructure.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: December 2, 2014
    Assignees: Phononic Devices, Inc., The Board of Regents of the University of Oklahoma
    Inventors: Allen L. Gray, Robert Joseph Therrien, Patrick John McCann
  • Patent number: 8895958
    Abstract: Disclosed is a light emitting element, which emits light with small power consumption and high luminance. The light emitting element has: a IV semiconductor substrate; two or more core multi-shell nanowires disposed on the IV semiconductor substrate; a first electrode connected to the IV semiconductor substrate; and a second electrode, which covers the side surfaces of the core multi-shell nanowires, and which is connected to the side surfaces of the core multi-shell nanowires. Each of the core multi-shell nanowires has: a center nanowire composed of a first conductivity type III-V compound semiconductor; a first barrier layer composed of the first conductivity type III-V compound semiconductor; a quantum well layer composed of a III-V compound semiconductor; a second barrier layer composed of a second conductivity type III-V compound semiconductor; and a capping layer composed of a second conductivity type III-V compound semiconductor.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: November 25, 2014
    Assignees: National University Corporation Hokkaido University, Sharp Kabushiki Kaisha
    Inventors: Takashi Fukui, Katsuhiro Tomioka
  • Publication number: 20140332833
    Abstract: Provided is a hetero-substrate that may include a base substrate, a buffer layer disposed on the base substrate, and a first semiconductor layer disposed on the buffer layer, the first semiconductor layer including a nitride semiconductor. A defect blocking layer is disposed on the first semiconductor layer. The defect blocking layer may include a plurality of metal droplets. A second semiconductor layer may be disposed on the defect blocking layer, the second semiconductor layer including a nitride semiconductor.
    Type: Application
    Filed: December 6, 2013
    Publication date: November 13, 2014
    Inventor: Chisun KIM
  • Patent number: 8882935
    Abstract: A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet light emitting diodes and laser diodes.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: November 11, 2014
    Assignees: The Regents of the University of California, The Japan Science and Technology Agency
    Inventors: Arpan Chakraborty, Benjamin A. Haskell, Stacia Keller, James S. Speck, Steven P. DenBaars, Shuji Nakamura, Umesh K. Mishra
  • Patent number: RE45517
    Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: May 19, 2015
    Assignee: Cree, Inc.
    Inventors: Kathleen Marie Doverspike, John Adam Edmond, Hua-shuang Kong, Heidi Marie Dieringer, David B. Slater, Jr.