Dielectric Having Perovskite Structure (epo) Patents (Class 257/E21.009)
  • Patent number: 10504920
    Abstract: An area occupied by a circuit element having at least a capacitor and a transistor is reduced in a semiconductor device. In a semiconductor device including a first transistor, a second transistor, and a capacitor, the first transistor and the capacitor are provided over the second transistor. Then, a common electrode, which serves as one of a source and a drain of the first transistor and one electrode of the capacitor, is provided. In addition, the other electrode of the capacitor is provided over the common electrode.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: December 10, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideki Matsukura
  • Patent number: 10475903
    Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ling Wang, Ping-Hung Chiang, Chang-Po Hsiung, Chia-Wen Lu, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 10453751
    Abstract: A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer. The patterning layer is etched to define a first pattern of raised structures and a complementary recessed pattern that is filled with a layer of image reverse material. The first pattern of raised structures is then removed to define a second pattern of structures comprising the image reverse material. A selective etching step is used to transfer the second pattern into a dielectric layer disposed between the layer of amorphous carbon and the substrate.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: October 22, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiaofeng Qiu, Michael V. Aquilino, Patrick D. Carpenter, Jessica Dechene, Ming Hao Tang, Haigou Huang, Huy Cao
  • Patent number: 10453938
    Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 22, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ling Wang, Ping-Hung Chiang, Chang-Po Hsiung, Chia-Wen Lu, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 10396034
    Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug. An interval between the first contact plug and the second contact plug may be about 10 nm or less.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Kong Siew, Wei Hsiung Tseng, Changhwa Kim
  • Patent number: 10361208
    Abstract: A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Choong-rae Cho
  • Patent number: 10347829
    Abstract: A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device with a reduced number of masking and etching steps is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate to expose a portion of the surface, and forming first spacers on sidewalls of the opening. A conductive layer is formed on the portion of the surface exposed in the opening and separated from the first spacers on the sidewalls of the opening by a gap therebetween. A bottom electrode of a ferroelectric capacitor is formed over the conductive layer and in the gap laterally of the conductive layer, a ferroelectric dielectric formed on the bottom electrode between the first spacers, and a top electrode formed on the ferroelectric dielectric.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: July 9, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, John Cronin, Tom E. Davenport
  • Patent number: 10340330
    Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Kirk Peterson, John Sheets, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang
  • Patent number: 10297600
    Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-hyoung Ahn, Youn-soo Kim, Jae-hyoung Choi, Jae-wan Chang, Sun-min Moon, Jin-sun Lee
  • Patent number: 10290422
    Abstract: Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container portion has an inner surface and an outer surface. Dielectric material lines the inner and outer surfaces of the upper container portion, and lines the outer surface of the lower pillar portion. A second electrode extends along the inner and outer surfaces of the upper container portion, and along the outer surface of the lower pillar portion. The second electrode is spaced from the first electrode by the dielectric material. Some embodiments include assemblies (e.g., memory arrays) which have capacitors. Some embodiments include methods of forming capacitors.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: May 14, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Hiroshi Amaike, Kota Hattori
  • Patent number: 10249637
    Abstract: A manufacturing method of a semiconductor device includes: forming a tunnel oxide layer and a charge-storage layer in a region of a flash memory transistor; forming a first oxide film; removing the first oxide film in regions of a first transistor and a second transistor; forming a third oxide film by adding a first oxide layer between a first oxide film and a semiconductor substrate in a region of a third transistor while forming a second oxide film in the regions of the first transistor and the second transistor by oxidation; removing the second oxide film in the region of the first transistor; and forming a fifth oxide film by adding a second oxide layer between the second oxide film and the semiconductor substrate in the region of the second transistor while forming a fourth oxide film in the region of the first transistor by oxidation, and forming a sixth oxide film by adding a third oxide layer between the first oxide layer and the semiconductor substrate in the region of the third transistor.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: April 2, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Satoshi Torii, Hideaki Matsumura, Shu Ishihara
  • Patent number: 10236390
    Abstract: A semiconductor device having stable electrical characteristics is provided. Alternatively, a highly reliable semiconductor device suitable for miniaturization or high integration is provided. The semiconductor device includes a first barrier layer, a second barrier layer, a third barrier layer, a transistor including an oxide, an insulator, and a conductor. The insulator includes an oxygen-excess region. The insulator and the oxide are between the first barrier layer and the second barrier layer. The conductor is in an opening of the first barrier layer, an opening of the second barrier layer, and an opening of the insulator with the third barrier layer positioned therebetween.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasumasa Yamane, Motomu Kurata, Ryota Hodo, Takahisa Ishiyama
  • Patent number: 10210921
    Abstract: The present invention relates to a non-volatile ferroelectric memory device including a semiconductor active layer, a plurality of memory cells connected in series on the semiconductor active layer, and a control circuit for performing a read operation and a program operation on the selected memory cell among the plurality of memory cells, each of the memory cells comprising a para-dielectric layer on the semiconductor active layer; a dielectric stack including a ferroelectric layer stacked on the para-dielectric layer and a charge trap site for generating a negative capacitance effect of the ferroelectric layer by charges disposed and trapped at an interface between the ferroelectric layer and the para-dielectric layer; and a control gate electrode on the ferroelectric layer.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: February 19, 2019
    Assignee: Seoul National University RDB foundation
    Inventor: Cheol Seong Hwang
  • Patent number: 10173421
    Abstract: Provided is a piezoelectric element including: a first electrode; a piezoelectric layer which is provided over the first electrode; and a second electrode provided on a side of the piezoelectric layer opposite to the first electrode, in which the second electrode includes a first layer which is provided on the piezoelectric layer side, and a second layer which is provided on a side of the first layer opposite to the piezoelectric layer, and the second layer does not contain platinum and covers an end portion of the first layer.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: January 8, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Masao Nakayama, Eiju Hirai, Naoto Yokoyama, Motoki Takabe, Toshihiro Shimizu
  • Patent number: 10177215
    Abstract: A microelectronic device includes a capacitor having a lower plate of interconnect metal, a capacitor dielectric layer with a lower silicon dioxide layer, a silicon oxy-nitride layer, and an upper silicon dioxide layer, and an upper plate over the capacitor dielectric layer. The silicon oxy-nitride layer has an average index of refraction of 1.85 to 1.95 at a wavelength of 248 nanometers. To form the microelectronic device, the lower silicon dioxide layer, the silicon oxy-nitride layer, and the upper silicon dioxide layer are formed in sequence over an interconnect metal layer. The upper plate is formed, leaving the lower silicon dioxide layer, the silicon oxy-nitride layer, and at least a portion of the upper silicon dioxide layer over the interconnect metal layer. An interconnect mask is formed of photoresist over the upper plate and the silicon oxy-nitride layer, using the silicon oxy-nitride layer as an anti-reflection layer.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: January 8, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bhaskar Srinivasan, Guru Mathur, Stephen Arlon Meisner, Shih Chang Chang, Corinne Ann Gagnet
  • Patent number: 10157915
    Abstract: A microelectronic device includes a capacitor having a lower plate of interconnect metal, a capacitor dielectric layer with a lower silicon dioxide layer, a silicon oxy-nitride layer, and an upper silicon dioxide layer, and an upper plate over the upper silicon dioxide layer. The silicon oxy-nitride layer has an average index of refraction of 1.60 to 1.75 at a wavelength of 248 nanometers. To form the microelectronic device, the lower silicon dioxide layer, the silicon oxy-nitride layer, and the upper silicon dioxide layer are formed in sequence over an interconnect metal layer. An upper plate layer is patterned to form the upper plate, leaving the lower silicon dioxide layer and at least half of the silicon oxy-nitride layer over the interconnect metal layer. An interconnect mask is formed of photoresist over the upper plate and the silicon oxy-nitride layer, using the silicon oxy-nitride layer as an anti-reflection layer.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: December 18, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Bhaskar Srinivasan, Shih Chang Chang, Poornika Gayathri Fernandes, Haowen Bu, Guru Mathur
  • Patent number: 10141353
    Abstract: The present disclosure provides integrated circuit apparatuses and methods for manufacturing integrated circuit apparatuses. An integrated circuit apparatus may include a first insulator, the first insulator being substantially planar and having a first top surface and a first bottom surface opposite the first top surface, a first conductor disposed on the first insulator, a second insulator, the second insulator being substantially planar and having a second top surface and a second bottom surface opposite the second top surface, a second conductor disposed on the second insulator, and a dielectric layer disposed between the first bottom conductor of the first insulator and the second top conductor of the second insulator.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: November 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Daeik Daniel Kim, Jonghae Kim, Mario Francisco Velez, Chengjie Zuo, David Francis Berdy
  • Patent number: 10121780
    Abstract: Disclosed are structures and methods related to a barrier layer for metallization of a selected semiconductor such as indium gallium phosphide (InGaP). In some embodiments, the barrier layer can include tantalum nitride (TaN). Such a barrier layer can provide desirable features such as barrier functionality, improved adhesion of a metal layer, reduced diffusion, reduced reactivity between the metal and InGaP, and stability during the fabrication process. In some embodiments, structures formed in such a manner can be configured as an emitter of a gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) or an on-die high-value capacitance element.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: November 6, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: Cristian Cismaru, Peter J. Zampardi, Jr.
  • Patent number: 10098230
    Abstract: A memory module and a method of manufacturing the same are disclosed. The memory module includes a substrate, at least one memory, a mask film and at least one light emitting diode. The substrate includes electrical circuit and golden fingers, and a notch is provided at the upper rim of the substrate. The mask film is formed of opaque copper foil, and has a notch and at least one hole close to the upper rim of the substrate. The light emitting diodes are configured on the substrate and connected to the electrical connection circuit, and each light emitting diode is provided at the corresponding hole of the mask film. Thus, light generated by the light emitting diodes passes through the hole and travels outwards along the upper rim of the substrate to form a specific bright pattern, text or strip, thereby enhancing a sense of vision.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: October 9, 2018
    Assignee: V-COLOR TECHNOLOGY INC.
    Inventor: Con-Ning Hung
  • Patent number: 10066163
    Abstract: Monodisperse particles having: a single pure crystalline phase of a rare earth-containing lattice, a uniform three-dimensional size, and a uniform polyhedral morphology are disclosed. Due to their uniform size and shape, the monodisperse particles self assemble into superlattices. The particles may be luminescent particles such as down-converting phosphor particles and up-converting phosphors. The monodisperse particles of the invention have a rare earth-containing lattice which in one embodiment may be an yttrium-containing lattice or in another may be a lanthanide-containing lattice. The monodisperse particles may have different optical properties based on their composition, their size, and/or their morphology (or shape).
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: September 4, 2018
    Assignees: Intelligent Material Solutions, Inc., The Trustees of the University of Pennsylvannia
    Inventors: Joshua E. Collins, Howard Y. Bell, Xingchen Ye, Christopher Bruce Murray
  • Patent number: 10068184
    Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jared Barney Hertzberg, Werner A. Rausch, Sami Rosenblatt, Rasit O. Topaloglu
  • Patent number: 10032674
    Abstract: A method for forming contacts on a semiconductor device includes forming trenches by etching an etch stop layer formed on an interlayer dielectric and etching the interlayer dielectric to expose source and drain regions between gate structures and depositing conductive material in the trenches and over the etch stop layer to a height above the etch stop layer. A resist is patterned on the conductive material with shapes over selected source and drain regions. The conductive material is subtractively etched to remove the conductive material from over the etch stop layer and to recess the conductive material into the trenches without the shapes to form self-aligned contacts below the shapes and lines in the trenches.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joshua M. Rubin, Balasubramanian Pranatharthiharan
  • Patent number: 10003022
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming Chyi Liu, Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 9991270
    Abstract: A semiconductor device and a manufacturing method for the same are provided in such a manner that the oxygen barrier film and the conductive plug in the base of a capacitor are prevented from being abnormally oxidized. A capacitor is formed by layering a lower electrode, a dielectric film including a ferroelectric substance or a high dielectric substance, and an upper electrode in this order on top of an interlayer insulation film with at least a conductive oxygen barrier film in between, and at least a portion of a side of the conductive oxygen barrier film is covered with an oxygen entering portion or an insulating oxygen barrier film.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: June 5, 2018
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Wensheng Wang
  • Patent number: 9985020
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. An epitaxial region is formed in a semiconductor substrate. A dielectric layer is formed on the epitaxial region, and a contact hole is formed in the dielectric layer. The contact hole exposes a part of the epitaxial region, and an oxide-containing layer is formed on the epitaxial region exposed by the contact hole. A contact structure is formed in the contact hole and on the oxide-containing layer. The oxide-containing layer is located between the contact structure and the epitaxial region. A semiconductor structure includes the semiconductor substrate, at least one epitaxial region, the contact structure, the oxide-containing layer, and a silicide layer. The contact structure is disposed on the epitaxial region. The oxide-containing layer is disposed between the epitaxial region and the contact structure. The silicide layer is disposed between the oxide-containing layer and the contact structure.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: May 29, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Yi-Kuan Wu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang, Yi-Wei Chen
  • Patent number: 9922982
    Abstract: An electric fuse structure is disclosed. The electric fuse preferably includes a substrate and a stacked capacitor on the substrate. Preferably, the stacked capacitor further includes: two or more bottom electrodes on the substrate; a capacitor dielectric layer on the two or more bottom electrodes; and a top electrode on the capacitor dielectric layer.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: March 20, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Yukihiro Nagai
  • Patent number: 9911847
    Abstract: A non-volatile memory device includes a substrate, a gate stack structure, an erase gate structure, and a ferroelectric layer. The gate stack structure is disposed on the substrate. The erase gate structure is disposed on the substrate and disposed at a first side of the gate stack structure. The ferroelectric layer is disposed on a sidewall of the gate stack structure, and the ferroelectric layer is disposed between the gate stack structure and the erase gate structure. The ferroelectric layer disposed between the gate stack structure and the erase gate structure may be used to forma negative capacitance effect for amplifying the voltage applied to the erase gate structure. The purpose of reducing power consumption may be achieved accordingly.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: March 6, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hock Chun Chin, Lanxiang Wang, Hong Liao, Chao Jiang, Chow Yee Lim
  • Patent number: 9899516
    Abstract: Coupling of switchable ferroelectric polarization with the carrier transport in an adjacent semiconductor enables a robust, non-volatile manipulation of the conductance in a host of low-dimensional systems, including the two-dimensional electron liquid that forms at the LaAlO3—SrTiO3 interface. However, the strength of the gate-channel coupling is relatively weak, limited in part by the electrostatic potential difference across a ferroelectric gate. Compositionally grading of PbZr1-xTixO3 ferroelectric gates enables a more than twenty-five-fold increase in the LAO/STO channel conductance on/off ratios. Incorporation of polarization gradients in ferroelectric gates can enable significantly enhanced performance of ferroelectric non-volatile memories.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 20, 2018
    Assignee: DREXEL UNIVERSITY
    Inventors: Zongquan Gu, Mohammad Anwarul Islam, Jonathan Eli Spanier
  • Patent number: 9893120
    Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a bottom electrode via (BEVA), a recap layer on the BEVA, and a magnetic tunneling junction (MTJ) layer over the recap layer. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA, and electroplated copper over the lining layer, filling the trench of the BEVA. The recap layer overlaps a top surface of the lining layer and a top surface of the electroplated copper.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Kuei-Hung Shen, Hsun-Chung Kuang, Cheng-Yuan Tsai, Ru-Liang Lee
  • Patent number: 9837605
    Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Pei Hsieh, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 9831255
    Abstract: A semiconductor device includes a lower electrode, a ferroelectric film on the lower electrode, an upper electrode on the ferroelectric film, and a first insulating film covering a surface and a side of the upper electrode, a side of the ferroelectric film, and a side of the lower electrode. The first insulating film includes a first opening that exposes a portion of the surface of the upper electrode. A second insulating film covers the first insulating film and includes a second opening that exposes the portion of the surface of the upper electrode through a second opening. A barrier metal is formed in the first opening and the second opening, and is connected to the upper electrode. A connection region in which a material of the barrier metal interacts with a material of the upper electrode extends below an upper-most surface of the upper electrode.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: November 28, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Yuichi Nakao
  • Patent number: 9741817
    Abstract: A method for manufacturing a metal insulator metal (MIM) trench capacitor, the method may include forming a cavity in an Intermetal Dielectric stack, wherein a bottom of the cavity exposes a lower metal layer; wherein the Intermetal Dielectric stack comprises a top dielectric layer; depositing a first metal layer on a bottom of a cavity and on sidewalls of the cavity; depositing a sacrificial layer over the first metal layer; filling the cavity with a filling material; removing, by a planarization process, a portion of the sacrificial layer positioned above the top dielectric layer and a portion of the first metal layer positioned above the top dielectric layer to expose an upper portion of the sacrificial layer and an upper portion of the first metal layer; forming a recess by removing the upper portion of the sacrificial layer and the upper portion the first metal layer while using the filling material as a mask; removing the filling material by a first removal process that is selective to the sacrificial l
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: August 22, 2017
    Assignee: TOWER SEMICONDUCTOR LTD.
    Inventors: Michael Lisiansky, Amos Fenigstein, Yakov Roizin, Hironori Matsuyoshi, Toshiaki Ohmi
  • Patent number: 9716063
    Abstract: A pattern is provided in a dielectric layer in which a set of features are patterned for a set of metal conductor structures. An adhesion promoting layer is created disposed over the patterned dielectric. A metal layer is deposited to fill a first portion of the set of features disposed the adhesion promoting layer. A ruthenium layer is deposited disposed over the metal layer. Using a physical vapor deposition process, a cobalt layer is deposited disposed over the ruthenium layer. A thermal anneal reflows the cobalt layer to fill a second portion of the set of features. In another aspect of the invention, a device created by the method is described.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: July 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 9711715
    Abstract: Read-only (“RO”) data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as heat, over-voltage, over-current and/or mechanical stress are then applied to the memory array or to individual storage cells within the memory array. The over-stress condition(s) act upon one or more state-determining elements of the storage cells to imprint the RO data. The over-stress condition permanently alters a value of a state-determining property of the state-determining element without incapacitating normal operation of the storage cell. The altered value of the state-determining property biases the cell according to the state of the RO data bit. The bias is detectable in the cell read-out signal. A pre-written ferroelectric random-access memory (“FRAM”) array is baked. Baking traps electric dipoles oriented in a direction corresponding to a state of the pre-written data and forms am RO data imprint.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: July 18, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chiraag Juvekar, Joyce Kwong, Clive Bittlestone, Srinath Ramaswamy, Stephen Heinrich-Barna
  • Patent number: 9698213
    Abstract: Vertical metal-insulator-metal (MIM) capacitors include a metal conductor including a sidewall; a high k dielectric layer on the sidewall of the metal conductor; and a vertically oriented metal layer on the high k dielectric layer. Also disclosed are methods for fabricating the vertical MIM capacitor, wherein a single patterning/mask process can used to fabricate the vertical MIM capacitor structure.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chih-Chao Yang
  • Patent number: 9673203
    Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: June 6, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita A. Chavan
  • Patent number: 9673270
    Abstract: A semiconductor device includes one or more metal-insulator-metal (MiM) capacitors. The semiconductor device includes a bottom electrode, a dielectric layer located above, and in physical contact with, the bottom electrode, a top electrode located above, and in physical contact with, the dielectric layer, a first top contact contacting the top electrode, a first bottom contact contacting the bottom electrode from a top electrode direction, a first metal bump connecting to the top contact, and a second metal bump connecting to the bottom contact. The top electrode has a smaller area than the bottom electrode. The bottom electrode, the dielectric layer, and the top electrode is a MiM capacitor. Top electrodes of a number of MiM capacitors and bottom electrodes of a number of MiM capacitors are daisy chained to allow testing of the conductivity of the electrodes.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Tung-Liang Shao, Ching-Jung Yang
  • Patent number: 9620601
    Abstract: Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Patent number: 9613861
    Abstract: Damascene wires with top via structures and methods of manufacture are provided. The semiconductor structure includes a damascene wiring structure with an integrally formed top via structure in self-alignment with the damascene wiring structure which is underneath the integrally formed top via structure.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: April 4, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 9548300
    Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region; a first planar type capacitor including a gate electrode which is positioned in any one region of the first region and the second region; a non-planar type capacitor including a plurality of non-planar type electrodes which are positioned in the other region of the first region and the second region; a second planar type capacitor including a planar type electrode which is positioned over the first planar type capacitor to overlap with the first planar type capacitor; and a common node under the non-planar type capacitor.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: January 17, 2017
    Assignee: SK Hynix Inc.
    Inventor: Jung-Sam Kim
  • Patent number: 9543375
    Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes a lower metal capacitor electrode, an upper metal capacitor electrode, and a capacitor dielectric separating the lower metal capacitor electrode from the upper metal capacitor electrode. The capacitor dielectric is made up of an amorphous oxide/nitride matrix and a plurality of metal or metal oxide/nitride nano-particles that are randomly distributed over the volume of amorphous oxide/nitride matrix.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Shiou Huang, Yao-Wen Chang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai
  • Patent number: 9524879
    Abstract: Semiconductor devices, and methods for fabricating a semiconductor device, include forming a contact hole penetrating an interlayer insulating layer and exposing a conductor defining a bottom surface of the contact hole, forming a sacrificial layer filling the contact hole, forming a first trench overlapping a part of the contact hole by removing at least a part of the sacrificial layer, forming a spacer filling the first trench, forming a second trench by removing a remainder of the sacrificial layer, and forming a metal electrode filling the contact hole and the second trench using electroless plating.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: December 20, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Su Lee, Young-Wook Park, Hee-Sook Park, Dong-Bok Lee, Jong-Myeong Lee
  • Patent number: 9520353
    Abstract: A metal-insulation-metal (MIM) device including a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer is provided. The first insulation layer is disposed on the first metal layer. The second metal layer is disposed on a part of the first insulation layer. The second insulation layer is disposed on a side wall of the second metal layer and on another part of the first insulation layer. A width of the first insulation layer under the second metal layer and the second insulation layer parallel to the first metal layer is greater than a with of the second metal layer parallel to the first metal layer.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: December 13, 2016
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Hung-Sui Lin, Mao-Hsiung Lin
  • Patent number: 9466662
    Abstract: In one embodiment, an energy storage device (e.g., capacitor) may include a porous silicon layer formed within a substrate. The porous silicon layer includes pores with a mean pore diameter less than approximately 100 nanometers. A first conductive layer is formed on the porous silicon layer and a first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer to form the capacitor.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: October 11, 2016
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Larry E. Mosley
  • Patent number: 9461239
    Abstract: A method of heating includes a process of forming a layer to be heated on one surface of a light absorption layer; and a process of heating the light absorption layer by irradiating light onto the other surface of the light absorption layer. The other surface of the light absorption layer is a surface opposite to the one surface of the light absorption layer.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: October 4, 2016
    Assignee: Ricoh Company, Ltd.
    Inventor: Xianfeng Chen
  • Patent number: 9450042
    Abstract: Integrated circuits with metal-insulator-metal (MIM) capacitors and methods for fabricating such integrated circuits are provided. In an embodiment, an integrated circuit includes a dielectric material layer overlying a semiconductor substrate. A surface conditioning layer overlies the dielectric material layer. Further, a metal layer is formed directly on the surface conditioning layer. A MIM capacitor is positioned on the metal layer. The MIM capacitor includes a first conductive layer formed directly on the metal layer with a smooth upper surface, an insulator layer formed directly on the smooth upper surface of the first conductive layer, and a second conductive layer formed directly on the insulator layer with a smooth lower surface.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: September 20, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventor: Matthias Lehr
  • Patent number: 9437592
    Abstract: A switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an SiC semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the SiC semiconductor layer, and a second electrode arranged to be in contact with the SiC semiconductor layer for conducting with the first electrode due to the formation of the current path, while the first electrode has a variable resistance portion made of a material whose resistance value increases under a prescribed high-temperature condition for limiting current density of overcurrent to not more than a prescribed value when the overcurrent flows to the current path.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: September 6, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Hiroyuki Sakairi
  • Patent number: 9384959
    Abstract: A purge ring for providing a gas to a wafer processing chamber includes an inlet ring wall defining a ring hole space. An outer perimeter of the inlet ring wall is elliptical. An outer perimeter of the ring hole space is circular. The inlet ring wall is a continuous structure surrounding the ring hole space. An inlet baffle formed within the inlet ring wall surrounds at least 180 degrees of the outer perimeter of the ring hole space. An inlet plenum arranged in a first end of the inlet ring wall provides the gas to the ring hole space through the inlet baffle. An exhaust channel is formed within the inlet ring wall in a second end of the inlet ring wall. An exhaust outlet hole arranged in the second end of the inlet ring wall exhausts the gas out of the ring hole space via the exhaust channel.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: July 5, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Eugene Smargiassi, Stephen Yu-Hong Lau, George D. Kamian, Ming Xi
  • Patent number: 9336879
    Abstract: A device includes first and second pluralities of memory cells with memory elements and first and second capping materials on the first and second pluralities of memory cells. First and second capping materials can comprise lower and higher density silicon nitrides. The memory elements can include a programmable resistance memory material, and the capping materials can contact the memory elements. The first and second pluralities of memory cells can have a common cell structure. The first memory cells in the can comprise a top and bottom electrodes with a memory material therebetween and the first capping material contacting the memory material. Control circuits can apply different write algorithms to the first and second pluralities of memory cells. The first and second sets of memory cells can have different operational memory characteristics by forming the first and second capping layers using different capping materials but with the same cell structure.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: May 10, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hsiang-Lan Lung, Chao-I Wu, Wei-Chih Chien
  • Patent number: 9269621
    Abstract: A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: February 23, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang