Abstract: Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, and a ferroelectric layer disposed between the first electrode and the second electrode. An edge region exposed by the first electrode and the second electrode is covered by at least one of a healing layer or a block layer.

Abstract: A method of manufacturing a semiconductor structure includes providing a substrate and an interlayer dielectric (ILD) over the substrate; disposing a first dielectric layer over the ILD and the substrate; forming a conductive member surrounded by the first dielectric layer; disposing a second dielectric layer over the first dielectric layer and the conductive member; forming a capacitor over the second dielectric layer; disposing a third dielectric layer over the capacitor and the second dielectric layer; forming a conductive via extending through the second dielectric layer, the capacitor and the third dielectric layer; forming a conductive pad over the conductive via; and forming a conductive bump over the conductive pad, wherein the disposing of the third dielectric layer includes disposing an oxide layer over the capacitor and disposing a nitride layer over the capacitor.

Abstract: A method for fabricating a capacitor includes forming a first electrode, forming a dielectric layer stack on the first electrode, the dielectric layer stack including an initial hafnium oxide layer and a seed layer having a doping layer embedded therein, forming a thermal source layer on the dielectric layer stack to crystallize the initial hafnium oxide into tetragonal hafnium oxide, and forming a second electrode on the thermal source layer.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region with an etch stop layer interposed therebetween, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug.

Abstract: A display device including an emitting element. A first transistor includes a first electrode electrically connected to a first supply voltage line, a second electrode electrically connected to the emitting element, and a gate electrode receiving a data signal, the first transistor being configured to transfer a driving current to the emitting element based on the data signal. A capacitor is connected between the gate electrode of the first transistor and the first supply voltage line. An electric field generating element is connected between the second electrode of the first transistor and the gate electrode of the first transistor and includes ferroelectrics.

Abstract: A semiconductor device includes a lower intermetal dielectric (IMD) layer, a middle conductive line, and a ferroelectric random access memory (FRAM) structure. The middle conductive line is embedded in the lower IMD layer. The FRAM structure is over the lower IMD layer and the middle conductive line. The FRAM structure includes a bottom electrode, a ferroelectric layer, and a top electrode. The bottom electrode is over the middle conductive line and in contact with the lower IMD layer. The ferroelectric layer is over the bottom electrode. The top electrode is over the ferroelectric layer.

Abstract: An MIM capacitor includes a semiconductor substrate having a conductor layer thereon, a dielectric layer overlying the semiconductor substrate and the conductor layer, and a first capacitor electrode disposed on the dielectric layer. The first capacitor electrode partially overlaps with the conductor layer when viewed from above. A capacitor dielectric layer is disposed on the first capacitor electrode. A second capacitor electrode is disposed on the capacitor dielectric layer. At least one via is disposed in the dielectric layer and electrically connecting the first capacitor electrode with the conductor layer.

Abstract: A semiconductor device includes a base structure of a memory device including a first electrode, first dielectric material having a non-uniform etch rate disposed on the base structure, a via within the first dielectric material, and a ring heater within the via on the first electrode. The ring heater has a geometry based on a shape of the via that produces a resistance gradient.

Abstract: A process is provided in which a hard mask material comprising ruthenium is used. Ruthenium provides a hard mask material that is etch resistant to many of the plasma chemistries typically used for processing substrate patterning layers, including layers such as, for example, nitrides, oxides, anti-reflective coating (ARC) materials, etc. Further, ruthenium may be removed by plasma chemistries that do not remove nitrides, oxides, ARC materials, etc. For example, ruthenium may be easily removed through the use of an oxygen (O2) plasma. Further, ruthenium may be deposited as a thin planar 10 nm order film over oxides and nitrides and may be deposited as a planar layer.

Abstract: A method of forming a ferroelectric/anti-ferroelectric (FE/AFE) dielectric layer is provided. The method includes forming a metal electrode layer on a substrate, wherein the metal electrode layer has an exposed surface with at least 80% {111} crystal face, and forming an FE/AFE dielectric layer on the exposed surface of the metal electrode layer, wherein the FE/AFE dielectric layer is a group 4 transition metal oxide.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor on a semiconductor substrate is presented. The method includes forming a first electrode defining columnar grains, forming a dielectric layer over the first electrode, and forming a second electrode over the dielectric layer. The first and second electrodes can be titanium nitride (TiN) electrodes. The dielectric layer can include one of hafnium oxide and zirconium oxide deposited by atomic layer deposition (ALD). The ALD results in deposition of high-k films in grain boundaries of the first electrode.

Abstract: A process of forming a metal-insulator-metal (MIM) capacitor may be incorporated into a process of forming metal bond pads connected directly to a top metal interconnect layer (e.g., Cu MTOP). The MIM capacitor may include a dielectric layer formed between a bottom plate defined by the Cu MTOP and a top plate comprising an extension of, or connected directly to, a metal bond pad formed above the Cu MTOP. The process of forming the MIM capacitor may include etching an opening in a passivation layer formed over the Cu MTOP to expose a top surface of the Cu MTOP, forming a dielectric layer extending into the passivation layer opening and onto the exposed Cu MTOP surface, removing portions of the dielectric layer to define a capacitor dielectric, and depositing bond pad metal extending into the passivation layer opening and onto the capacitor dielectric, to define the MIM capacitor top plate.

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device including a semiconductor substrate including a first region and a second region; an interlayer insulating layer on the semiconductor substrate, the interlayer insulating layer including a first opening on the first region and having a first width; and a second opening on the second region and having a second width, the second width being greater than the first width; at least one first metal pattern filling the first opening; a second metal pattern in the second opening; and a filling pattern on the second metal pattern in the second opening, wherein the at least one first metal pattern and the second metal pattern each include a same first metal material, and the filling pattern is formed of a non-metal material.

Abstract: A redistribution substrate includes a first conductive pattern including a first lower pad and a second lower pad, the first and second lower pads being within a first insulating layer, a second conductive pattern including a first upper pad and a second upper pad, the first and second upper pads being on the first insulating layer, a first via connecting the first lower pad and the first upper pad to each other in the first insulating layer, a second via connecting the second lower pad and the second upper pad to each other in the first insulating layer, and a capacitor between the first lower pad and the first via.

Abstract: An integrated circuit (IC) includes a substrate having functional circuitry for realizing at least one circuit function configured together with at least one high voltage isolation component including a top metal feature above the substrate. A crack suppressing dielectric structure including at least a crack resistant dielectric layer is on at least a top of the top metal feature. At least one dielectric passivation overcoat (PO) layer is on an outer portion of the top metal feature.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first conductive pattern and a conductive mask disposed over the first conductive pattern. The semiconductor device further includes a second conductive pattern disposed over the conductive mask, and electrically connecting with the first conductive pattern through the conductive mask. The conductive mask has a lower etch rate to a predetermined etchant than the second conductive pattern. A method for forming the semiconductor device is also provided.

Abstract: Described is a low power, high-density non-volatile differential memory bit-cell. The transistors of the differential memory bit-cell can be planar or non-planer and can be fabricated in the frontend or backend of a die. A bit-cell of the non-volatile differential memory bit-cell comprises first transistor first non-volatile structure that are controlled to store data of a first value. Another bit-cell of the non-volatile differential memory bit-cell comprises second transistor and second non-volatile structure that are controlled to store data of a second value, wherein the first value is an inverse of the second value. The first and second volatile structures comprise ferroelectric material (e.g., perovskite, hexagonal ferroelectric, improper ferroelectric).

Abstract: A semiconductor storage device includes a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a barrier metal layer provided on the insulating layer; an aluminum compound layer provided on the barrier metal layer; an amorphous layer provided on the aluminum compound layer and including a material that vaporizes upon its chemical reaction with fluorine; and a metal layer provided on the amorphous layer.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor on a semiconductor substrate is presented. The method includes forming a first electrode defining columnar grains, forming a dielectric layer over the first electrode, and forming a second electrode over the dielectric layer. The first and second electrodes can be titanium nitride (TiN) electrodes. The dielectric layer can include one of hafnium oxide and zirconium oxide deposited by atomic layer deposition (ALD). The ALD results in deposition of high-k films in grain boundaries of the first electrode.

Abstract: A semiconductor structure includes a substrate and a first trench including a dielectric material disposed in the substrate. The first trench includes a transferred pattern of a first polymer of a directed self-assembly stack including the first polymer and a second polymer. The semiconductor structure also includes a second trench including a first vertical metal plate disposed in the substrate adjacent a first sidewall of the first trench, and a third trench including a second vertical metal plate disposed in the substrate adjacent a second sidewall of the first trench. The first vertical metal plate in the second trench, the dielectric material in the first trench, and the second vertical metal plate in the third trench provide a metal-insulator-metal vertical plate capacitor.

Abstract: A thin film capacitor comprises a first electrode, a second electrode, and a dielectric substance disposed between the first electrode 10 and the second electrode. The second electrode has a first metallic layer, an intermediate layer, and a second metallic layer in sequence in this order from the side of the dielectric substance. The first metallic layer contains a metal element M1 as a main component, and the second metallic layer contains a metal element M2 different from the metal element M1 as a main component. The intermediate layer has one or more laminate structures each having a second metal sublayer containing the metal element M2 as a main component and a first metal sublayer containing the metal element M1 as a main component in sequence from the side of the first metallic layer toward the side of the second metallic layer.

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.

Abstract: A method for testing a semiconductor structure includes forming a dielectric layer over a test region of a substrate. A cap layer is formed over the dielectric layer. The dielectric layer and the cap layer are annealed. The annealed cap layer is removed. A ferroelectricity of the annealed dielectric layer is in-line tested.

Abstract: Described are doped TaN films, as well as methods for providing the doped TaN films. Doping TaN films with Ru, Cu, Co, Mn, Al, Mg, Cr, Nb, Ti and/or V allows for enhanced copper barrier properties of the TaN films. Also described are methods of providing films with a first layer comprising doped TaN and a second layer comprising one or more of Ru and Co, with optional doping of the second layer.

Abstract: Semiconductor structures are provided that include a memory device buried within interconnect dielectric materials and in which a combination of a compressive metal-containing layer and a tensile metal-containing layer have been used to minimize wafer bow and litho overlay shift as well as a method of forming such semiconductor structures.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure having an active region, a gate insulating layer, a charge storage layer, a gate dielectric layer, and a gate layer sequentially formed on the active region. The method also includes forming a patterned metal layer on the substrate structure, removing a respective portion of the gate layer, the gate dielectric layer, the charge storage layer using the patterned metal gate layer as a mask to form multiple gate structures separated from each other by a space. The gate structures each include a stack containing a second portion of the charge storage layer, the gate dielectric layer, the gate layer, and one of the gate lines. The method further includes forming an interlayer dielectric layer on a surface of the gate structures stretching over the space while forming an air gap in the space.

Abstract: Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.

Abstract: A method for fabricating semiconductor device includes: forming a bottom electrode of a high aspect ratio; forming an interface layer by sequentially performing a first plasma process and a second plasma process onto a surface of the bottom electrode; forming a dielectric layer over the interface layer; and forming a top electrode over the dielectric layer.

Abstract: Capacitors include a stack that has a first metallic layer formed over a substrate with at least one high domain and at least one low domain, an insulator formed over the first metallic layer, and a second metallic layer formed over the insulator. A bottom contact is formed in the substrate having a top surface that is even with a top surface of the substrate in the at least one high domain. A cap layer is formed directly on the substrate in the high domains, under the stack.

Abstract: A method of forming a package includes providing a die, which includes a substrate having a circuit, a first passivation layer on the substrate, a plurality of pads on the first passivation layer, and a second passivation layer disposed on the first passivation layer and covering the plurality of pads. The method also includes forming one or more trenches by etching the second passivation layer that overlies a portion of the first passivation layer on the outside of the plurality of pads, and forming an organic polymer overlying the die after the one or more trenches are formed, thereby forming the package.

Abstract: A magnetoresistance device is disclosed, comprising a bottom electrode, a magnetic tunneling junction (MTJ) disposed on the bottom electrode, a top electrode disposed on the magnetic tunneling junction, a first spacer disposed on the magnetic tunneling junction and covering a sidewall of the top electrode, and a second spacer disposed on the first spacer and conformally covering along a sidewall of the first spacer, a sidewall of the magnetic tunneling junction and a sidewall of the bottom electrode.

Abstract: An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.

Abstract: A selected ferroelectric memory cell of a ferroelectric memory is electrically connected to a first bit line, a second bit line, a first word line, a second word line and a plate line. The selected ferroelectric memory cell includes a first field effect transistor (“FET”), a second FET and a ferroelectric capacitor. A control terminal and a first access terminal of the first FET are electrically connected to the first word line and the first bit line, respectively. A control terminal and a first access terminal of the second FET are electrically connected to the second word line and the second bit line, respectively. A second access terminal of the first FET is electrically connected to a first capacitor electrode of the ferroelectric capacitor and a second access terminal of the second FET. A second capacitor electrode of the ferroelectric capacitor is electrically connected to the plate line.

Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.

Abstract: Some embodiments include constructions which have platinum-containing structures. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures and across metal oxide. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures, across a first material retaining the platinum-containing structures, and across metal oxide liners along sidewalls of the platinum-containing structures and directly between the platinum-containing structures and the first material. Some embodiments include methods of forming platinum-containing structures. In some embodiments, first material is formed across electrically conductive structures, and metal oxide is formed across the first material. Openings are formed to extend through the metal oxide and the first material to the electrically conductive structures. Platinum-containing material is formed within the openings and over the metal oxide.

Abstract: Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container portion has an inner surface and an outer surface. Dielectric material lines the inner and outer surfaces of the upper container portion, and lines the outer surface of the lower pillar portion. A second electrode extends along the inner and outer surfaces of the upper container portion, and along the outer surface of the lower pillar portion. The second electrode is spaced from the first electrode by the dielectric material. Some embodiments include assemblies (e.g., memory arrays) which have capacitors. Some embodiments include methods of forming capacitors.

Abstract: An area occupied by a circuit element having at least a capacitor and a transistor is reduced in a semiconductor device. In a semiconductor device including a first transistor, a second transistor, and a capacitor, the first transistor and the capacitor are provided over the second transistor. Then, a common electrode, which serves as one of a source and a drain of the first transistor and one electrode of the capacitor, is provided. In addition, the other electrode of the capacitor is provided over the common electrode.

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Abstract: A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer. The patterning layer is etched to define a first pattern of raised structures and a complementary recessed pattern that is filled with a layer of image reverse material. The first pattern of raised structures is then removed to define a second pattern of structures comprising the image reverse material. A selective etching step is used to transfer the second pattern into a dielectric layer disposed between the layer of amorphous carbon and the substrate.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug. An interval between the first contact plug and the second contact plug may be about 10 nm or less.

Abstract: A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided.

Abstract: A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device with a reduced number of masking and etching steps is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate to expose a portion of the surface, and forming first spacers on sidewalls of the opening. A conductive layer is formed on the portion of the surface exposed in the opening and separated from the first spacers on the sidewalls of the opening by a gap therebetween. A bottom electrode of a ferroelectric capacitor is formed over the conductive layer and in the gap laterally of the conductive layer, a ferroelectric dielectric formed on the bottom electrode between the first spacers, and a top electrode formed on the ferroelectric dielectric.

Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.

Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.

Abstract: Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container portion has an inner surface and an outer surface. Dielectric material lines the inner and outer surfaces of the upper container portion, and lines the outer surface of the lower pillar portion. A second electrode extends along the inner and outer surfaces of the upper container portion, and along the outer surface of the lower pillar portion. The second electrode is spaced from the first electrode by the dielectric material. Some embodiments include assemblies (e.g., memory arrays) which have capacitors. Some embodiments include methods of forming capacitors.

Abstract: A manufacturing method of a semiconductor device includes: forming a tunnel oxide layer and a charge-storage layer in a region of a flash memory transistor; forming a first oxide film; removing the first oxide film in regions of a first transistor and a second transistor; forming a third oxide film by adding a first oxide layer between a first oxide film and a semiconductor substrate in a region of a third transistor while forming a second oxide film in the regions of the first transistor and the second transistor by oxidation; removing the second oxide film in the region of the first transistor; and forming a fifth oxide film by adding a second oxide layer between the second oxide film and the semiconductor substrate in the region of the second transistor while forming a fourth oxide film in the region of the first transistor by oxidation, and forming a sixth oxide film by adding a third oxide layer between the first oxide layer and the semiconductor substrate in the region of the third transistor.

Abstract: A semiconductor device having stable electrical characteristics is provided. Alternatively, a highly reliable semiconductor device suitable for miniaturization or high integration is provided. The semiconductor device includes a first barrier layer, a second barrier layer, a third barrier layer, a transistor including an oxide, an insulator, and a conductor. The insulator includes an oxygen-excess region. The insulator and the oxide are between the first barrier layer and the second barrier layer. The conductor is in an opening of the first barrier layer, an opening of the second barrier layer, and an opening of the insulator with the third barrier layer positioned therebetween.

Abstract: The present invention relates to a non-volatile ferroelectric memory device including a semiconductor active layer, a plurality of memory cells connected in series on the semiconductor active layer, and a control circuit for performing a read operation and a program operation on the selected memory cell among the plurality of memory cells, each of the memory cells comprising a para-dielectric layer on the semiconductor active layer; a dielectric stack including a ferroelectric layer stacked on the para-dielectric layer and a charge trap site for generating a negative capacitance effect of the ferroelectric layer by charges disposed and trapped at an interface between the ferroelectric layer and the para-dielectric layer; and a control gate electrode on the ferroelectric layer.

Abstract: Provided is a piezoelectric element including: a first electrode; a piezoelectric layer which is provided over the first electrode; and a second electrode provided on a side of the piezoelectric layer opposite to the first electrode, in which the second electrode includes a first layer which is provided on the piezoelectric layer side, and a second layer which is provided on a side of the first layer opposite to the piezoelectric layer, and the second layer does not contain platinum and covers an end portion of the first layer.