Dielectric Having Perovskite Structure (epo) Patents (Class 257/E21.009)
  • Patent number: 11031284
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first conductive pattern and a conductive mask disposed over the first conductive pattern. The semiconductor device further includes a second conductive pattern disposed over the conductive mask, and electrically connecting with the first conductive pattern through the conductive mask. The conductive mask has a lower etch rate to a predetermined etchant than the second conductive pattern. A method for forming the semiconductor device is also provided.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pin-Ren Dai, Hsi-Wen Tien, Wei-Hao Liao, Chih Wei Lu, Chung-Ju Lee
  • Patent number: 10998025
    Abstract: Described is a low power, high-density non-volatile differential memory bit-cell. The transistors of the differential memory bit-cell can be planar or non-planer and can be fabricated in the frontend or backend of a die. A bit-cell of the non-volatile differential memory bit-cell comprises first transistor first non-volatile structure that are controlled to store data of a first value. Another bit-cell of the non-volatile differential memory bit-cell comprises second transistor and second non-volatile structure that are controlled to store data of a second value, wherein the first value is an inverse of the second value. The first and second volatile structures comprise ferroelectric material (e.g., perovskite, hexagonal ferroelectric, improper ferroelectric).
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: May 4, 2021
    Assignee: Kepler Computing, Inc.
    Inventors: Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh
  • Patent number: 10978551
    Abstract: A method for forming a metal-insulator-metal (MIM) capacitor on a semiconductor substrate is presented. The method includes forming a first electrode defining columnar grains, forming a dielectric layer over the first electrode, and forming a second electrode over the dielectric layer. The first and second electrodes can be titanium nitride (TiN) electrodes. The dielectric layer can include one of hafnium oxide and zirconium oxide deposited by atomic layer deposition (ALD). The ALD results in deposition of high-k films in grain boundaries of the first electrode.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Eduard A. Cartier, Hemanth Jagannathan, Paul C. Jamison, Vijay Narayanan
  • Patent number: 10978469
    Abstract: A semiconductor storage device includes a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a barrier metal layer provided on the insulating layer; an aluminum compound layer provided on the barrier metal layer; an amorphous layer provided on the aluminum compound layer and including a material that vaporizes upon its chemical reaction with fluorine; and a metal layer provided on the amorphous layer.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 13, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kensei Takahashi, Takashi Asano, Satoshi Wakatsuki
  • Patent number: 10964779
    Abstract: A semiconductor structure includes a substrate and a first trench including a dielectric material disposed in the substrate. The first trench includes a transferred pattern of a first polymer of a directed self-assembly stack including the first polymer and a second polymer. The semiconductor structure also includes a second trench including a first vertical metal plate disposed in the substrate adjacent a first sidewall of the first trench, and a third trench including a second vertical metal plate disposed in the substrate adjacent a second sidewall of the first trench. The first vertical metal plate in the second trench, the dielectric material in the first trench, and the second vertical metal plate in the third trench provide a metal-insulator-metal vertical plate capacitor.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kafai Lai, Rasit Onur Topaloglu
  • Patent number: 10943738
    Abstract: A thin film capacitor comprises a first electrode, a second electrode, and a dielectric substance disposed between the first electrode 10 and the second electrode. The second electrode has a first metallic layer, an intermediate layer, and a second metallic layer in sequence in this order from the side of the dielectric substance. The first metallic layer contains a metal element M1 as a main component, and the second metallic layer contains a metal element M2 different from the metal element M1 as a main component. The intermediate layer has one or more laminate structures each having a second metal sublayer containing the metal element M2 as a main component and a first metal sublayer containing the metal element M1 as a main component in sequence from the side of the first metallic layer toward the side of the second metallic layer.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: March 9, 2021
    Assignee: TDK Corporation
    Inventors: Masahiro Hiraoka, Hiroshi Takasaki, Hitoshi Saita
  • Patent number: 10847452
    Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: November 24, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Luisa Lin, Mohan Dunga, Venkatesh P. Ramachandra, Peter Rabkin, Masaaki Higashitani
  • Patent number: 10818562
    Abstract: A method for testing a semiconductor structure includes forming a dielectric layer over a test region of a substrate. A cap layer is formed over the dielectric layer. The dielectric layer and the cap layer are annealed. The annealed cap layer is removed. A ferroelectricity of the annealed dielectric layer is in-line tested.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Shiang Lin, Chia-Cheng Ho, Chun-Chieh Lu, Cheng-Yi Peng, Chih-Sheng Chang
  • Patent number: 10784157
    Abstract: Described are doped TaN films, as well as methods for providing the doped TaN films. Doping TaN films with Ru, Cu, Co, Mn, Al, Mg, Cr, Nb, Ti and/or V allows for enhanced copper barrier properties of the TaN films. Also described are methods of providing films with a first layer comprising doped TaN and a second layer comprising one or more of Ru and Co, with optional doping of the second layer.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: September 22, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Annamalai Lakshmanan, Paul F. Ma, Mei Chang, Jennifer Shan
  • Patent number: 10763431
    Abstract: Semiconductor structures are provided that include a memory device buried within interconnect dielectric materials and in which a combination of a compressive metal-containing layer and a tensile metal-containing layer have been used to minimize wafer bow and litho overlay shift as well as a method of forming such semiconductor structures.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: September 1, 2020
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Choonghyun Lee, Chih-Chao Yang, Seyoung Kim, Soon-Cheon Seo
  • Patent number: 10720439
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure having an active region, a gate insulating layer, a charge storage layer, a gate dielectric layer, and a gate layer sequentially formed on the active region. The method also includes forming a patterned metal layer on the substrate structure, removing a respective portion of the gate layer, the gate dielectric layer, the charge storage layer using the patterned metal gate layer as a mask to form multiple gate structures separated from each other by a space. The gate structures each include a stack containing a second portion of the charge storage layer, the gate dielectric layer, the gate layer, and one of the gate lines. The method further includes forming an interlayer dielectric layer on a surface of the gate structures stretching over the space while forming an air gap in the space.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: July 21, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Changgeng Song
  • Patent number: 10692759
    Abstract: Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: June 23, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Hao Jiang, He Ren, Hao Chen, Mehul B. Naik
  • Patent number: 10672772
    Abstract: A method for fabricating semiconductor device includes: forming a bottom electrode of a high aspect ratio; forming an interface layer by sequentially performing a first plasma process and a second plasma process onto a surface of the bottom electrode; forming a dielectric layer over the interface layer; and forming a top electrode over the dielectric layer.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventors: Beom-Yong Kim, Hun Lee, Deok-Sin Kil
  • Patent number: 10651266
    Abstract: Capacitors include a stack that has a first metallic layer formed over a substrate with at least one high domain and at least one low domain, an insulator formed over the first metallic layer, and a second metallic layer formed over the insulator. A bottom contact is formed in the substrate having a top surface that is even with a top surface of the substrate in the at least one high domain. A cap layer is formed directly on the substrate in the high domains, under the stack.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: May 12, 2020
    Assignee: Tessera, Inc.
    Inventors: Kisup Chung, Isabel C. Estrada-Raygoza, Hemanth Jagannathan, Chi-Chun Liu, Yann A. M. Mignot, Hao Tang
  • Patent number: 10636719
    Abstract: A method of forming a package includes providing a die, which includes a substrate having a circuit, a first passivation layer on the substrate, a plurality of pads on the first passivation layer, and a second passivation layer disposed on the first passivation layer and covering the plurality of pads. The method also includes forming one or more trenches by etching the second passivation layer that overlies a portion of the first passivation layer on the outside of the plurality of pads, and forming an organic polymer overlying the die after the one or more trenches are formed, thereby forming the package.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 28, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yuan Zi Yin
  • Patent number: 10629802
    Abstract: A magnetoresistance device is disclosed, comprising a bottom electrode, a magnetic tunneling junction (MTJ) disposed on the bottom electrode, a top electrode disposed on the magnetic tunneling junction, a first spacer disposed on the magnetic tunneling junction and covering a sidewall of the top electrode, and a second spacer disposed on the first spacer and conformally covering along a sidewall of the first spacer, a sidewall of the magnetic tunneling junction and a sidewall of the bottom electrode.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chiu-Jung Chiu, Yu-Chun Chen, Ya-Sheng Feng, Hung-Chan Lin
  • Patent number: 10608075
    Abstract: An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: March 31, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bhaskar Srinivasan, Guru Mathur, Stephen Arlon Meisner, Shih Chang Chang, Corinne Ann Gagnet
  • Patent number: 10586582
    Abstract: A selected ferroelectric memory cell of a ferroelectric memory is electrically connected to a first bit line, a second bit line, a first word line, a second word line and a plate line. The selected ferroelectric memory cell includes a first field effect transistor (“FET”), a second FET and a ferroelectric capacitor. A control terminal and a first access terminal of the first FET are electrically connected to the first word line and the first bit line, respectively. A control terminal and a first access terminal of the second FET are electrically connected to the second word line and the second bit line, respectively. A second access terminal of the first FET is electrically connected to a first capacitor electrode of the ferroelectric capacitor and a second access terminal of the second FET. A second capacitor electrode of the ferroelectric capacitor is electrically connected to the plate line.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: March 10, 2020
    Assignee: NUSTORAGE TECHNOLOGY CO., LTD.
    Inventors: Fu-Chou Liu, Yung-Tin Chen
  • Patent number: 10580696
    Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sean Xuan Lin, Christian Witt, Mark V. Raymond, Nicholas V. LiCausi, Errol Todd Ryan
  • Patent number: 10573720
    Abstract: Some embodiments include constructions which have platinum-containing structures. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures and across metal oxide. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures, across a first material retaining the platinum-containing structures, and across metal oxide liners along sidewalls of the platinum-containing structures and directly between the platinum-containing structures and the first material. Some embodiments include methods of forming platinum-containing structures. In some embodiments, first material is formed across electrically conductive structures, and metal oxide is formed across the first material. Openings are formed to extend through the metal oxide and the first material to the electrically conductive structures. Platinum-containing material is formed within the openings and over the metal oxide.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Andrey V. Zagrebelny, Chet E. Carter, Andrew D. Carswell
  • Patent number: 10566136
    Abstract: Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container portion has an inner surface and an outer surface. Dielectric material lines the inner and outer surfaces of the upper container portion, and lines the outer surface of the lower pillar portion. A second electrode extends along the inner and outer surfaces of the upper container portion, and along the outer surface of the lower pillar portion. The second electrode is spaced from the first electrode by the dielectric material. Some embodiments include assemblies (e.g., memory arrays) which have capacitors. Some embodiments include methods of forming capacitors.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Hiroshi Amaike, Kota Hattori
  • Patent number: 10504920
    Abstract: An area occupied by a circuit element having at least a capacitor and a transistor is reduced in a semiconductor device. In a semiconductor device including a first transistor, a second transistor, and a capacitor, the first transistor and the capacitor are provided over the second transistor. Then, a common electrode, which serves as one of a source and a drain of the first transistor and one electrode of the capacitor, is provided. In addition, the other electrode of the capacitor is provided over the common electrode.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: December 10, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideki Matsukura
  • Patent number: 10475903
    Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ling Wang, Ping-Hung Chiang, Chang-Po Hsiung, Chia-Wen Lu, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 10453938
    Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 22, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ling Wang, Ping-Hung Chiang, Chang-Po Hsiung, Chia-Wen Lu, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 10453751
    Abstract: A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer. The patterning layer is etched to define a first pattern of raised structures and a complementary recessed pattern that is filled with a layer of image reverse material. The first pattern of raised structures is then removed to define a second pattern of structures comprising the image reverse material. A selective etching step is used to transfer the second pattern into a dielectric layer disposed between the layer of amorphous carbon and the substrate.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: October 22, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiaofeng Qiu, Michael V. Aquilino, Patrick D. Carpenter, Jessica Dechene, Ming Hao Tang, Haigou Huang, Huy Cao
  • Patent number: 10396034
    Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug. An interval between the first contact plug and the second contact plug may be about 10 nm or less.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Kong Siew, Wei Hsiung Tseng, Changhwa Kim
  • Patent number: 10361208
    Abstract: A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Choong-rae Cho
  • Patent number: 10347829
    Abstract: A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device with a reduced number of masking and etching steps is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate to expose a portion of the surface, and forming first spacers on sidewalls of the opening. A conductive layer is formed on the portion of the surface exposed in the opening and separated from the first spacers on the sidewalls of the opening by a gap therebetween. A bottom electrode of a ferroelectric capacitor is formed over the conductive layer and in the gap laterally of the conductive layer, a ferroelectric dielectric formed on the bottom electrode between the first spacers, and a top electrode formed on the ferroelectric dielectric.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: July 9, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, John Cronin, Tom E. Davenport
  • Patent number: 10340330
    Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Kirk Peterson, John Sheets, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang
  • Patent number: 10297600
    Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-hyoung Ahn, Youn-soo Kim, Jae-hyoung Choi, Jae-wan Chang, Sun-min Moon, Jin-sun Lee
  • Patent number: 10290422
    Abstract: Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container portion has an inner surface and an outer surface. Dielectric material lines the inner and outer surfaces of the upper container portion, and lines the outer surface of the lower pillar portion. A second electrode extends along the inner and outer surfaces of the upper container portion, and along the outer surface of the lower pillar portion. The second electrode is spaced from the first electrode by the dielectric material. Some embodiments include assemblies (e.g., memory arrays) which have capacitors. Some embodiments include methods of forming capacitors.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: May 14, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Hiroshi Amaike, Kota Hattori
  • Patent number: 10249637
    Abstract: A manufacturing method of a semiconductor device includes: forming a tunnel oxide layer and a charge-storage layer in a region of a flash memory transistor; forming a first oxide film; removing the first oxide film in regions of a first transistor and a second transistor; forming a third oxide film by adding a first oxide layer between a first oxide film and a semiconductor substrate in a region of a third transistor while forming a second oxide film in the regions of the first transistor and the second transistor by oxidation; removing the second oxide film in the region of the first transistor; and forming a fifth oxide film by adding a second oxide layer between the second oxide film and the semiconductor substrate in the region of the second transistor while forming a fourth oxide film in the region of the first transistor by oxidation, and forming a sixth oxide film by adding a third oxide layer between the first oxide layer and the semiconductor substrate in the region of the third transistor.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: April 2, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Satoshi Torii, Hideaki Matsumura, Shu Ishihara
  • Patent number: 10236390
    Abstract: A semiconductor device having stable electrical characteristics is provided. Alternatively, a highly reliable semiconductor device suitable for miniaturization or high integration is provided. The semiconductor device includes a first barrier layer, a second barrier layer, a third barrier layer, a transistor including an oxide, an insulator, and a conductor. The insulator includes an oxygen-excess region. The insulator and the oxide are between the first barrier layer and the second barrier layer. The conductor is in an opening of the first barrier layer, an opening of the second barrier layer, and an opening of the insulator with the third barrier layer positioned therebetween.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasumasa Yamane, Motomu Kurata, Ryota Hodo, Takahisa Ishiyama
  • Patent number: 10210921
    Abstract: The present invention relates to a non-volatile ferroelectric memory device including a semiconductor active layer, a plurality of memory cells connected in series on the semiconductor active layer, and a control circuit for performing a read operation and a program operation on the selected memory cell among the plurality of memory cells, each of the memory cells comprising a para-dielectric layer on the semiconductor active layer; a dielectric stack including a ferroelectric layer stacked on the para-dielectric layer and a charge trap site for generating a negative capacitance effect of the ferroelectric layer by charges disposed and trapped at an interface between the ferroelectric layer and the para-dielectric layer; and a control gate electrode on the ferroelectric layer.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: February 19, 2019
    Assignee: Seoul National University RDB foundation
    Inventor: Cheol Seong Hwang
  • Patent number: 10173421
    Abstract: Provided is a piezoelectric element including: a first electrode; a piezoelectric layer which is provided over the first electrode; and a second electrode provided on a side of the piezoelectric layer opposite to the first electrode, in which the second electrode includes a first layer which is provided on the piezoelectric layer side, and a second layer which is provided on a side of the first layer opposite to the piezoelectric layer, and the second layer does not contain platinum and covers an end portion of the first layer.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: January 8, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Masao Nakayama, Eiju Hirai, Naoto Yokoyama, Motoki Takabe, Toshihiro Shimizu
  • Patent number: 10177215
    Abstract: A microelectronic device includes a capacitor having a lower plate of interconnect metal, a capacitor dielectric layer with a lower silicon dioxide layer, a silicon oxy-nitride layer, and an upper silicon dioxide layer, and an upper plate over the capacitor dielectric layer. The silicon oxy-nitride layer has an average index of refraction of 1.85 to 1.95 at a wavelength of 248 nanometers. To form the microelectronic device, the lower silicon dioxide layer, the silicon oxy-nitride layer, and the upper silicon dioxide layer are formed in sequence over an interconnect metal layer. The upper plate is formed, leaving the lower silicon dioxide layer, the silicon oxy-nitride layer, and at least a portion of the upper silicon dioxide layer over the interconnect metal layer. An interconnect mask is formed of photoresist over the upper plate and the silicon oxy-nitride layer, using the silicon oxy-nitride layer as an anti-reflection layer.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: January 8, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bhaskar Srinivasan, Guru Mathur, Stephen Arlon Meisner, Shih Chang Chang, Corinne Ann Gagnet
  • Patent number: 10157915
    Abstract: A microelectronic device includes a capacitor having a lower plate of interconnect metal, a capacitor dielectric layer with a lower silicon dioxide layer, a silicon oxy-nitride layer, and an upper silicon dioxide layer, and an upper plate over the upper silicon dioxide layer. The silicon oxy-nitride layer has an average index of refraction of 1.60 to 1.75 at a wavelength of 248 nanometers. To form the microelectronic device, the lower silicon dioxide layer, the silicon oxy-nitride layer, and the upper silicon dioxide layer are formed in sequence over an interconnect metal layer. An upper plate layer is patterned to form the upper plate, leaving the lower silicon dioxide layer and at least half of the silicon oxy-nitride layer over the interconnect metal layer. An interconnect mask is formed of photoresist over the upper plate and the silicon oxy-nitride layer, using the silicon oxy-nitride layer as an anti-reflection layer.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: December 18, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Bhaskar Srinivasan, Shih Chang Chang, Poornika Gayathri Fernandes, Haowen Bu, Guru Mathur
  • Patent number: 10141353
    Abstract: The present disclosure provides integrated circuit apparatuses and methods for manufacturing integrated circuit apparatuses. An integrated circuit apparatus may include a first insulator, the first insulator being substantially planar and having a first top surface and a first bottom surface opposite the first top surface, a first conductor disposed on the first insulator, a second insulator, the second insulator being substantially planar and having a second top surface and a second bottom surface opposite the second top surface, a second conductor disposed on the second insulator, and a dielectric layer disposed between the first bottom conductor of the first insulator and the second top conductor of the second insulator.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: November 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Daeik Daniel Kim, Jonghae Kim, Mario Francisco Velez, Chengjie Zuo, David Francis Berdy
  • Patent number: 10121780
    Abstract: Disclosed are structures and methods related to a barrier layer for metallization of a selected semiconductor such as indium gallium phosphide (InGaP). In some embodiments, the barrier layer can include tantalum nitride (TaN). Such a barrier layer can provide desirable features such as barrier functionality, improved adhesion of a metal layer, reduced diffusion, reduced reactivity between the metal and InGaP, and stability during the fabrication process. In some embodiments, structures formed in such a manner can be configured as an emitter of a gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) or an on-die high-value capacitance element.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: November 6, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: Cristian Cismaru, Peter J. Zampardi, Jr.
  • Patent number: 10098230
    Abstract: A memory module and a method of manufacturing the same are disclosed. The memory module includes a substrate, at least one memory, a mask film and at least one light emitting diode. The substrate includes electrical circuit and golden fingers, and a notch is provided at the upper rim of the substrate. The mask film is formed of opaque copper foil, and has a notch and at least one hole close to the upper rim of the substrate. The light emitting diodes are configured on the substrate and connected to the electrical connection circuit, and each light emitting diode is provided at the corresponding hole of the mask film. Thus, light generated by the light emitting diodes passes through the hole and travels outwards along the upper rim of the substrate to form a specific bright pattern, text or strip, thereby enhancing a sense of vision.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: October 9, 2018
    Assignee: V-COLOR TECHNOLOGY INC.
    Inventor: Con-Ning Hung
  • Patent number: 10068184
    Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jared Barney Hertzberg, Werner A. Rausch, Sami Rosenblatt, Rasit O. Topaloglu
  • Patent number: 10066163
    Abstract: Monodisperse particles having: a single pure crystalline phase of a rare earth-containing lattice, a uniform three-dimensional size, and a uniform polyhedral morphology are disclosed. Due to their uniform size and shape, the monodisperse particles self assemble into superlattices. The particles may be luminescent particles such as down-converting phosphor particles and up-converting phosphors. The monodisperse particles of the invention have a rare earth-containing lattice which in one embodiment may be an yttrium-containing lattice or in another may be a lanthanide-containing lattice. The monodisperse particles may have different optical properties based on their composition, their size, and/or their morphology (or shape).
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: September 4, 2018
    Assignees: Intelligent Material Solutions, Inc., The Trustees of the University of Pennsylvannia
    Inventors: Joshua E. Collins, Howard Y. Bell, Xingchen Ye, Christopher Bruce Murray
  • Patent number: 10032674
    Abstract: A method for forming contacts on a semiconductor device includes forming trenches by etching an etch stop layer formed on an interlayer dielectric and etching the interlayer dielectric to expose source and drain regions between gate structures and depositing conductive material in the trenches and over the etch stop layer to a height above the etch stop layer. A resist is patterned on the conductive material with shapes over selected source and drain regions. The conductive material is subtractively etched to remove the conductive material from over the etch stop layer and to recess the conductive material into the trenches without the shapes to form self-aligned contacts below the shapes and lines in the trenches.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joshua M. Rubin, Balasubramanian Pranatharthiharan
  • Patent number: 10003022
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming Chyi Liu, Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 9991270
    Abstract: A semiconductor device and a manufacturing method for the same are provided in such a manner that the oxygen barrier film and the conductive plug in the base of a capacitor are prevented from being abnormally oxidized. A capacitor is formed by layering a lower electrode, a dielectric film including a ferroelectric substance or a high dielectric substance, and an upper electrode in this order on top of an interlayer insulation film with at least a conductive oxygen barrier film in between, and at least a portion of a side of the conductive oxygen barrier film is covered with an oxygen entering portion or an insulating oxygen barrier film.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: June 5, 2018
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Wensheng Wang
  • Patent number: 9985020
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. An epitaxial region is formed in a semiconductor substrate. A dielectric layer is formed on the epitaxial region, and a contact hole is formed in the dielectric layer. The contact hole exposes a part of the epitaxial region, and an oxide-containing layer is formed on the epitaxial region exposed by the contact hole. A contact structure is formed in the contact hole and on the oxide-containing layer. The oxide-containing layer is located between the contact structure and the epitaxial region. A semiconductor structure includes the semiconductor substrate, at least one epitaxial region, the contact structure, the oxide-containing layer, and a silicide layer. The contact structure is disposed on the epitaxial region. The oxide-containing layer is disposed between the epitaxial region and the contact structure. The silicide layer is disposed between the oxide-containing layer and the contact structure.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: May 29, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Yi-Kuan Wu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang, Yi-Wei Chen
  • Patent number: 9922982
    Abstract: An electric fuse structure is disclosed. The electric fuse preferably includes a substrate and a stacked capacitor on the substrate. Preferably, the stacked capacitor further includes: two or more bottom electrodes on the substrate; a capacitor dielectric layer on the two or more bottom electrodes; and a top electrode on the capacitor dielectric layer.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: March 20, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Yukihiro Nagai
  • Patent number: 9911847
    Abstract: A non-volatile memory device includes a substrate, a gate stack structure, an erase gate structure, and a ferroelectric layer. The gate stack structure is disposed on the substrate. The erase gate structure is disposed on the substrate and disposed at a first side of the gate stack structure. The ferroelectric layer is disposed on a sidewall of the gate stack structure, and the ferroelectric layer is disposed between the gate stack structure and the erase gate structure. The ferroelectric layer disposed between the gate stack structure and the erase gate structure may be used to forma negative capacitance effect for amplifying the voltage applied to the erase gate structure. The purpose of reducing power consumption may be achieved accordingly.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: March 6, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hock Chun Chin, Lanxiang Wang, Hong Liao, Chao Jiang, Chow Yee Lim
  • Patent number: 9899516
    Abstract: Coupling of switchable ferroelectric polarization with the carrier transport in an adjacent semiconductor enables a robust, non-volatile manipulation of the conductance in a host of low-dimensional systems, including the two-dimensional electron liquid that forms at the LaAlO3—SrTiO3 interface. However, the strength of the gate-channel coupling is relatively weak, limited in part by the electrostatic potential difference across a ferroelectric gate. Compositionally grading of PbZr1-xTixO3 ferroelectric gates enables a more than twenty-five-fold increase in the LAO/STO channel conductance on/off ratios. Incorporation of polarization gradients in ferroelectric gates can enable significantly enhanced performance of ferroelectric non-volatile memories.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 20, 2018
    Assignee: DREXEL UNIVERSITY
    Inventors: Zongquan Gu, Mohammad Anwarul Islam, Jonathan Eli Spanier
  • Patent number: 9893120
    Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a bottom electrode via (BEVA), a recap layer on the BEVA, and a magnetic tunneling junction (MTJ) layer over the recap layer. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA, and electroplated copper over the lining layer, filling the trench of the BEVA. The recap layer overlaps a top surface of the lining layer and a top surface of the electroplated copper.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Kuei-Hung Shen, Hsun-Chung Kuang, Cheng-Yuan Tsai, Ru-Liang Lee