Abstract: A manufacturing method for a ferroelectric memory device includes: forming a ferroelectric capacitor on a substrate, the ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode; forming a first hydrogen barrier film that covers the ferroelectric capacitor by a chemical vapor deposition method; forming a dielectric film on the first hydrogen barrier film; forming a sidewall composed of the dielectric film on a side of the ferroelectric capacitor by etching back the dielectric film; forming a second hydrogen barrier film on the first hydrogen barrier film and the sidewall by a chemical vapor deposition method; and forming an interlayer dielectric film on the second hydrogen barrier film.

Abstract: In an embodiment of the present invention is provided a method of manufacturing a varactor, comprising providing a substrate; positioning a bottom electrode on a surface of the substrate; placing a tunable dielectric material adjacent to and extending over the bottom electrode forming a step and in contact with a top electrode; placing an interconnect layer in contact with the bottom electrode, the tunable dielectric and the top electrode.

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract: The invention provides a method for fabricating a memory device having memory cells which are formed on a microstructured driving unit (100), in which method a shaping layer (104) is provided and is patterned in such a manner that vertical trench structures (105) are formed perpendicular to the surface of the driving unit (100). Deposition of a seed layer (106) on side walls (105a) of the trench structures (105) allows a crystallization agent (107) which has filled the trench structures (105), during crystallization, to have grain boundaries perpendicular to electrode surfaces that are to be formed. This provides memory cells based on vertical ferroelectric capacitors in a chain FeRAM structure.

Abstract: A ferroelectric memory device may include a substrate, an interlayer insulating layer on the semiconductor substrate, a contact plug penetrating the interlayer insulating layer, the contact plug being formed of a sequentially stacked metal plug and buffer plug, a conductive protection pattern covering the contact plug, the conductive protection pattern being a conductive oxide layer, a lower electrode, a ferroelectric pattern, and an upper electrode sequentially stacked on the conductive protection pattern, and an insulating protection layer covering the sequentially stacked lower electrode, ferroelectric pattern, and upper electrode.

Abstract: It is an aspect of the embodiments discussed herein to provide a method manufacturing a semiconductor device, including forming a bottom electrode film above a semiconductor substrate, forming an insulating film on the bottom electrode film, forming a top electrode on the insulating film, forming a capacitor insulating film by patterning the insulating film, and removing a substance adhered to at least one selected from a group consisting of the top electrode, the capacitor insulating film, the bottom electrode film by an etchback.

Abstract: A method for forming storage node contacts in a semiconductor device includes forming an interlayer dielectric layer on a semiconductor substrate provided with transistors; forming a hydrogen diffusion preventing layer on the interlayer dielectric layer; forming a hard mask layer containing hydrogen atoms on the hydrogen diffusion preventing layer; forming storage node contact holes, which pass through the hydrogen diffusion preventing layer and the interlayer dielectric layer and expose impurity regions of the transistors, by etching the hydrogen diffusion preventing layer and the interlayer dielectric layer using the hard mask layer as an etching barrier layer; and forming the storage node contacts by filling the storage node contact holes with a conductive layer.

Abstract: A method of fabricating a conductive metal oxide gate ferroelectric memory transistor includes forming an oxide layer a substrate and removing the oxide layer in a gate area; depositing a conductive metal oxide layer on the oxide layer and on the exposed gate area; depositing a titanium layer on the metal oxide layer; patterning and etching the titanium layer and the metal oxide layer to remove the titanium layer and the metal oxide layer from the substrate except in the gate area; depositing, patterning and etching an oxide layer to form a gate trench; depositing and etching a barrier insulator layer to form a sidewall barrier in the gate trench; removing the titanium layer from the gate area; depositing, smoothing and annealing a ferroelectric layer in the gate trench; depositing, patterning and etching a top electrode; and completing the conductive metal oxide gate ferroelectric memory transistor.

Abstract: Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

Abstract: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.

Abstract: To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7. Upper surfaces and side surfaces of the ferroelectric capacitors 7 are covered by a second hydrogen barrier layer. All upper electrodes 7c of the plural ferroelectric capacitors 7 to be connected to a common plate line P are connected to one another by an upper wiring layer 91. The upper wiring layer 91 is connected to the plate line P through a lower wiring 32 provided below the ferroelectric capacitors 7. A third hydrogen barrier layer 92 is formed on the upper wiring layer 91 such that all edge sections 92a of the third hydrogen barrier layer 92 come in contact with the first hydrogen barrier layer 5.

Abstract: A method of manufacturing a semiconductor storage device having a capacitive element having a dielectric layer having a perovskite-type crystal structure represented by general formula ABO3 and a lower electrode and an upper electrode disposed so as to sandwich the dielectric layer therebetween; in the method are carried out forming, on a lower electrode conductive layer, using a MOCVD method, an initial nucleus containing at least one metallic element the same as a metallic element in the dielectric layer, forming, on the initial nucleus, using a MOCVD method, a buffer layer containing at least one metallic element the same as the metallic element contained in both the initial nucleus and the dielectric layer, in a higher content than the content of this metallic element contained in the initial nucleus, and forming, on the buffer layer, using a MOCVD method, the dielectric layer having a perovskite-type crystal structure.

Abstract: A semiconductor device of the present invention includes capacitors made up of a lower electrode, a capacitive insulation film made from metal oxide material, provided on one surface of a semiconductor substrate. An ozone TEOS film is provided on these capacitors, and a protective film for covering the upper surfaces of the capacitors is then provided on this ozone TEOS film. An interlay insulation film that is thicker than the ozone TEOS film is provided on the protective film for covering the upper surfaces of the capacitors. In this way, the present invention prevents degradation in film quality of the capacitive insulation film due to mutual reaction etc. As a result, it becomes possible to provide a capacitor using an insulating film made of a metal oxide as a capacitive insulation film, having a protective film for sufficiently preventing diffusion of H2, a semiconductor device having high reliability, and a method of manufacturing such a semiconductor device, are provided.

Abstract: One aspect of the invention relates to a method of cleaning high density capacitors. According to the method, the capacitors are cleaned with a plasma that includes fluorine-containing radicals. The plasma removes a small layer from the capacitors, including their sidewalls, and thereby removes surface contaminants. The method is effective even when the capacitors include hard-to-etch dielectric materials, such as tantalum and hafnium oxides. In a preferred embodiment, the plasma clean is combined with a solvent clean.

Abstract: An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used.

Abstract: Methods for fabricating high work function p-MOS device metal electrodes are provided. In one embodiment, a method is provided for producing a metal electrode including the steps of: providing a high k dielectric stack with an exposed surface; contacting the exposed surface of the high k dielectric stack with a vapor of a metal oxide wherein the metal oxide is selected from the group consisting of RuOx, IrOx, ReOx, MoOx, WOx, VOx, and PdOx; and contacting the exposed surface of the dielectric stack with a vapor of an additive selected from the group consisting of SiO2, Al2O3, HfO2, ZrO2, MgO, SrO, BaO, Y2O3, La2O3, and TiO2, whereby contacting the exposed surface of the dielectric stack with the vapor of the metal oxide and the vapor of the additive forms an electrode and wherein the additive is present at an amount between about 1% to about 50% by atomic weight percent in the electrode.

Abstract: A first hydrogen barrier film and an intermediate layer are formed on an interlayer dielectric film. A ferroelectric capacitor is formed on the intermediate layer, and a second hydrogen barrier film is formed over the entire surface including on the upper surface and side surfaces of the ferroelectric capacitor and on the intermediate layer. Then, the second hydrogen barrier film and the intermediate layer are removed while leaving at least portions on the upper surface and side surfaces of the ferroelectric capacitor. Then, a third hydrogen barrier film is formed on the second hydrogen barrier film, on side surfaces of the second hydrogen barrier film and the intermediate layer, and on the first hydrogen barrier film.

Abstract: A method of depositing a hafnium-based dielectric film is provided. The method comprises atomic layer deposition using ozone and one or more reactants comprising a hafnium precursor. A semiconductor device is also provided. The device comprises a substrate, a hafnium-based dielectric layer formed atop the substrate, and an interfacial layer formed between the substrate and the hafnium-based dielectric layer, wherein the interfacial layer comprises silicon dioxide and has a crystalline structure.

Abstract: The invention provides a method for forming a ferroelectric thin film that is uniform and good in crystallinity. The method includes applying a liquid to a surface of a substrate. The liquid includes ultra-fine particle powder comprising at least one element constituting the ferroelectric thin film to a surface of a substrate. The liquid applied to the surface of substrate is then baked.

Abstract: A method for manufacturing a ferroelectric capacitor includes successively disposing a lower electrode, at least one intermediate electrode and an upper electrode over a base substrate, and providing ferroelectric films between the electrodes, respectively. In the step of forming the intermediate electrode, (a) a first metal film is formed by a sputter method over the ferroelectric film, and (b) a second metal film is formed by a vapor deposition method over the first metal film.

Abstract: A method is provided for manufacturing a capacitor including the steps of forming a lower electrode on a substrate, forming an insulation film formed of a perovskite type metal oxide on the lower electrode, and forming an upper electrode on the insulation film. The step of forming the insulation film includes the steps of coating a dispersion liquid in which fine crystal powder of a second metal oxide of a perovskite type in a liquid containing a precursor compound of a first metal oxide of a perovskite type on the lower electrode, and performing a heat treatment of the dispersion liquid after coating.

Abstract: The present invention lowers a drive voltage of a RRAM, which is a promising low power consumption, high-speed memory and suppresses variations in the width of an electric pulse for realizing a same resistance change. The present invention provides a variable resistance element including: a first electrode; a layer in which its resistance is variable by applying an electric pulse thereto, the layer being formed on the first electrode; and a second electrode formed on the layer; wherein the layer has a perovskite structure; and the layer has at least one selected from depressions and protrusions in an interface with at least one electrode selected from the first electrode and the second electrode.

Abstract: A method for integrating a metal-insulator-metal (MIM) capacitor in back end of line (BEOL) wiring levels of a semiconductor device includes forming an isolating layer over a lower wiring level, forming a bottom electrode of the capacitor on the isolating layer, and forming an interlevel dielectric material on the isolating layer and the bottom electrode. A capacitor dielectric is formed on the bottom electrode and a top electrode of the capacitor is formed on the capacitor dielectric, wherein the top electrode is formed concurrently with an upper wiring level, the upper level being the next successive wiring level with respect to the lower wiring level.

Abstract: The present invention provides a semicondctor device that includes a conductor comprised of first and second layers of perovskite that have different stoichiometric compositions. The conductors provide a good template for the formation of dielectric layers thereon and are resistant to oxidizing environments used in semiconductor processing.

Abstract: A semiconductor device is disclosed that includes an interposer and a semiconductor chip. The interposer includes a Si substrate; multiple through vias provided through an insulating material in corresponding through holes passing through the Si substrate; a thin film capacitor provided on a first main surface of the Si substrate so as to be electrically connected to the through vias; and multiple external connection terminals provided on a second main surface of the Si substrate so as to be electrically connected to the through vias. The second main surface faces away from the first main surface. The semiconductor chip is provided on one of the first main surface and the second main surface so as to be electrically connected to the through vias. The Si substrate has a thickness less than the diameter of the through holes.