Abstract: A method for manufacturing a photomask includes obtaining a substrate on which a halftone film, a light-shielding film, and a resist film are stacked, irradiating a first region of the resist film at a first dose and a second region of the resist film that surrounds the first region at a second dose greater than the first dose, developing the resist film in the first region to form a mask pattern while leaving the resist film in the second region to form a mask frame pattern, and then patterning the light-shielding film using the mask pattern formed in the resist film.

Abstract: A method includes: providing a device having a first layer and a second layer in contact with a surface of the first layer, in which the second layer includes a first superconductor material; forming a buffer material on the second layer to form an etch buffer layer, in which an etch rate selectivity of the buffer material relative to the second layer upon exposure to a photoresist developer is such that the underlying second layer is not etched during exposure of the buffer layer to the photoresist developer; depositing and removing a selected portion of a resist layer to uncover a first portion of the etch buffer layer, wherein removing the selected portion of the resist layer comprises applying the photoresist developer to the selected portion of the resist layer.

Abstract: A method includes: providing a device having a first layer and a second layer in contact with a surface of the first layer, in which the second layer includes a first superconductor material; forming a buffer material on the second layer to form an etch buffer layer, in which an etch rate selectivity of the buffer material relative to the second layer upon exposure to a photoresist developer is such that the underlying second layer is not etched during exposure of the buffer layer to the photoresist developer; depositing and removing a selected portion of a resist layer to uncover a first portion of the etch buffer layer, wherein removing the selected portion of the resist layer comprises applying the photoresist developer to the selected portion of the resist layer.

Abstract: A method includes: providing a device having a first layer and a second layer in contact with a surface of the first layer, in which the second layer includes a first superconductor material; forming a buffer material on the second layer to form an etch buffer layer, in which an etch rate selectivity of the buffer material relative to the second layer upon exposure to a photoresist developer is such that the underlying second layer is not etched during exposure of the buffer layer to the photoresist developer; depositing and removing a selected portion of a resist layer to uncover a first portion of the etch buffer layer, wherein removing the selected portion of the resist layer comprises applying the photoresist developer to the selected portion of the resist layer.

Abstract: Device structures for a field-effect transistor and methods for forming a device structure for a field-effect transistor. A first dielectric layer is formed, and a second dielectric layer are formed on the first dielectric layer. An opening is formed that extends vertically through the first and second dielectric layers. After the first opening is formed, the second dielectric layer is laterally recessed relative to the first dielectric layer with a selective etching process, which widens a portion of the opening extending vertically through the second dielectric layer relative to a portion of the opening extending vertically through the first dielectric layer. After the second dielectric layer is laterally recessed, a gate electrode is formed that includes a narrow section in the portion of the opening extending vertically through the first dielectric layer and a wide section in the portion of the opening extending vertically through the second dielectric layer.

Abstract: An array substrate and a fabrication method thereof, and a display device are provided. The array substrate comprises: a thin film transistor (TFT 10) provided on a base substrate (01), a first passivation layer (200) provided on the thin film transistor (TFT 10), and a transparent electrode layer (300) provided on a surface of the first passivation layer (200). The first passivation layer (300) includes: a first sub-thin film layer (210), and a second sub-thin film layer (211) which is provided on a surface of the first sub-thin film layer (210) and in contact with the transparent electrode layer (300); and a film density of the second sub-thin film layer (211) is greater than that of the first sub-thin film layer (210).

Abstract: When a coating film 4 is formed on a substrate 1, on which elements 3 are formed, by an ALD film forming method or the like, the coating film 4 is partially removed in a simple step. A method for manufacturing an electronic device includes a step of coating the substrate 1 partially with a partially coating member 2, a step of forming the elements 3 on the substrate 1, a step of forming the coating film 4 on the substrate 1 to cover the elements 3 and the partially coating member 2, and a step of forming a crack 4A in the coating film 4 on the partially coating member 2.

Abstract: An array substrate and a fabricating method thereof are disclosed. The array substrate has a transparent substrate, a buffer layer, a first/second gate pattern, a transparent insulating layer and a first/second polysilicon pattern. The buffer layer is located on first/second portions of the transparent substrate. The first/second gate patterns are formed on the buffer layer and located respectively on the first/second portions. The transparent insulating layer covers the first/second gate patterns and the buffer layer. The first/second polysilicon patterns are formed on the transparent insulating layer, and have neighboring first/second regions and neighboring third/fourth regions; the second/fourth regions are first/second lightly doped polysilicon regions respectively; the first region and the first gate pattern have an identical first patterning shape; and the third region and the second gate pattern have an identical second patterning shape.

Abstract: Provided is a method of fabricating a light-emitting diode (LED) device. The method includes providing a substrate having opposite first and second sides. A semiconductor layer is formed on the first side of the substrate. The method includes forming a photoresist layer over the semiconductor layer. The method includes patterning the photoresist layer into a plurality of photoresist components. The photoresist components are separated by openings. The method includes filling the openings with a plurality of thermally conductive components. The method includes separating the semiconductor layer into a plurality of dies using a radiation process that is performed to the substrate from the second side. Each of the first regions of the substrate is aligned with one of the conductive components.

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method comprises following steps. A substrate is provided. A sacrificial layer is formed on the substrate. The sacrificial layer is patterned to develop a first opening and a second opening. The first opening corresponds to an exposed portion of the substrate and the second opening corresponds to an unexposed portion of the substrate. A heat procedure is performed. A target material is formed on the exposed portion of the substrate and a rest part of the sacrificial layer. The rest part of the sacrificial layer and parts of the target material on the rest part of the sacrificial layer are removed. A predetermined patterned target material is obtained.

Abstract: A manufacturing method for an array substrate comprising: sequentially forming a gate metal film, a gate insulating layer and an active layer film; applying photoresist, and patterning the photoresist; etching the stacked layers corresponding to a photoresist-completely-removed region; ashing to remove the photoresist in a photoresist-partially-remained region and remain a part of photoresist in a photoresist-completely-remained region, etching the gate insulating layer and the active layer film in the photoresist-partially-remained region; forming an insulating layer film; lifting off the photoresist and the insulating layer film thereon; forming a conductive film, and patterning the conductive film to from a source electrode, a drain electrode, a data line, a pixel electrode and an active layer channel.

Abstract: The present invention related to a lift-off structure adapted to a substrate having a photoelectric device, the structure comprising: a buffer layer, forming on the substrate; an upper sacrificial layer, forming on the buffer layer; an etch stop layer, forming on the upper sacrificial layer, and the photoelectric device structure forming on the etch stop layer.

Abstract: A method for applying a predetermined structure of a structural material to a semiconductor element. The method includes the following steps: A) partially covering a surface of the semiconductor element with a masking layer, B) applying a film of a structural material to the masking layer and to the surface of the semiconductor element in the zones that are devoid of the masking layer and C) removing the masking layer together with the structural material present on the masking layer. The method according to the invention provides that between process steps B and C, the film of structural material is partially removed in a process step B2.

Abstract: A thin film patterning method comprising: depositing a first thin film and applying a photoresist layer on the first thin film; exposing and developing the photoresist layer to define first, second and third regions, wherein the photoresist layer in the first region is thicker than that in the second region, and no photoresist layer is left in the third region; over-etching to remove the first thin film in the third region and form an over-etched region in the peripheral region of the first region; removing a part of the photoresist layer to expose the first thin film in the second region; depositing a second thin film so that the first thin film contacts the second thin film in the second region; and lifting off the photoresist layer to remove the second thin film in the first region and exposing the substrate in the over-etched region of the first region.

Abstract: A method for fabricating optical devices on a reusable handle substrate. The method includes providing a handle substrate having a surface region. The method also includes forming a plurality of optical device using at least an epitaxial growth process overlying the surface region and then releasing the handle substrate from the plurality of optical devices. The method reuses the handle substrate for another fabrication process.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: Ordered, two-dimensional arrays of pyramidal particulates and related methods of preparation.

Abstract: The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer.

Abstract: Devices are presented including: a substrate including a dielectric region and a conductive region; a molecular self-assembled layer selectively formed on the dielectric region; and a capping layer formed on the conductive region, where the capping layer is an electrically conductive material such as: an alloy of cobalt and boron material, an alloy of cobalt, tungsten, and phosphorous material, an alloy of nickel, molybdenum, and phosphorous. In some embodiments, devices are presented where the molecular self-assembled layer includes one or more of a polyelectrolyte, a dendrimer, a hyper-branched polymer, a polymer brush, a block co-polymer, and a silane-based material where the silane-based material includes one or more hydrolysable substituents of a general formula RnSiX4-n, where R is: an alkyl, a substituted alkyl, a fluoroalkyl, an aryl, a substituted aryl, and a fluoroaryl, and where X is: a halo, an alkoxy, an aryloxy, an amino, an octadecyltrichlorosilane, and an aminopropyltrimethoxysilane.

Abstract: An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat.

Abstract: For the manufacture of a photovoltaic module (1), there are attached to a transparent substrate (2) a transparent front electrode layer (3), a semiconductor layer (4) and a rear electrode layer (5) which, for forming cells (C1, C2, . . . , Cn, Cn+1) connected in series, are structured by dividing lines (6, 7, 8). A water-soluble detachment mass (12) is applied using an inkjet printer (15) to the regions of the semiconductor layer (4) at which the dividing lines (8) are to be formed in the rear electrode layer (5), whereon the rear electrode layer (5) is attached. The detachment mass (12), with the regions attached thereto of the rear electrode layer (5), is removed using a water jet (13) while forming the dividing lines (8) in the rear electrode layer (5).

Abstract: An etchant, a method for fabricating a multi-layered interconnection line using the etchant, and a method for fabricating a thin film transistor (TFT) substrate using the etchant. The etchant for the multi-layered line comprised of molybdenum/copper/molybdenum nitride illustratively includes 10-20 wt % hydrogen peroxide, 1-5 wt % organic acid, a 0.1-1 wt % triazole-based compound, a 0.01-0.5 wt % fluoride compound, and deionized water as the remainder.

Abstract: The method of manufacturing a semiconductor device comprising: forming a first hard mask layer and a second hard mask layer on the layer to be etched (S11); a first groove-forming mask pattern forming process for forming a groove-forming mask pattern which has a first pitch, is formed of the second hard mask layer, and is used as an etching mask when forming groove patterns(S12-S14); and a first concave portion-forming mask pattern forming process for etching the first hard mask layer using the second resist pattern as an etching mask, wherein the second resist pattern is formed of the second resist layer having an opening portion that has a fourth pitch and the first organic layer having an opening portion that is connected to an opening portion of the second resist layer and has a smaller size than the opening portion of the second resist layer (S15-S18).

Abstract: A thin-film transistor (“TFT”) substrate and a method of fabricating the same include: an insulating substrate; gate wiring which is disposed on the insulating substrate and includes a gate line and a gate electrode; a semiconductor pattern which is disposed on the gate electrode; data wiring which is disposed on the semiconductor pattern and includes a data line, a source electrode, and a drain electrode; a passivation layer which includes a first sub-passivation layer and a second sub-passivation layer deposited on the data wiring; and a pixel electrode which is electrically connected to the drain electrode through a contact hole disposed in the passivation layer, wherein the second sub-passivation layer has a lower density than the first sub-passivation layer.

Abstract: Systems and methods for MEMS device fabrication. A layer of photoresist is formed on a substrate. A first region of the substrate is exposed to a radiation source through a photomask. The first region of exposed photoresist is developed with a developer solution in order to etch the exposed regions to a first depth. A second region is exposed to radiation through a second photomask. The second photomask defines areas in which a bump feature is intended on the substrate. The second region is developed with the developer solution, preparing the first and second exposed regions for a layer of metal. A layer of metal is deposited on the substrate, such that the metal attaches to both the substrate and any remaining photoresist on the substrate. The remaining photoresist and its attached metal is dissolved away leaving an interconnect pattern and at least one bump feature.

Abstract: A method for forming an electrode structure in a light emitting device is disclosed. The method includes the steps of: forming a mask material layer having an opening; depositing a first material layer on the mask material layer and on a portion of a compound semiconductor layer exposed through the bottom of the opening by a physical vapor deposition method reducing the particle density so that the mean free path for collision is long; depositing a second material layer on the first material layer on the mask material layer, on the first material layer deposited on the bottom of the opening, and on a portion of the compound semiconductor layer exposed through the bottom of the opening by a vapor deposition method other than the physical vapor deposition method; and removing the mask material layer and the first and second material layers deposited on the mask material layer.

Abstract: A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced relative one another. Width of the spaced second features is laterally trimmed to a greater degree than any lateral trimming of width of the spaced first features while laterally trimming width of the spaced second features. After laterally trimming of the second features, spacers are formed on sidewalls of the spaced first features and on sidewalls of the spaced second features. The spacers are of some different composition from that of the spaced first features and from that of the spaced second features. After forming the spacers, the spaced first features and the spaced second features are removed from the substrate. The substrate is processed through a mask pattern comprising the spacers. Other embodiments are disclosed.

Abstract: A method for fabricating a semiconductor device is provided. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a first insulating layer, a first conductive layer and a chemical mechanical polishing (CMP) stop layer over the semiconductor substrate in sequence; forming openings in the chemical mechanical polishing (CMP) stop layer and the underlying first conductive layer to expose the first insulating layer, thereby leaving a patterned chemical mechanical polishing (CMP) stop layer and a patterned first conductive layer; forming a second insulating layer on the patterned chemical mechanical polishing (CMP) stop layer, filling in the openings; performing a planarization process to remove a portion of the second insulating layer until the patterned chemical mechanical polishing (CMP) stop layer is exposed, thereby leaving a remaining second insulating layer in the openings; removing the patterned chemical mechanical polishing (CMP) stop layer.

Abstract: A method for fabricating a pixel structure is provided. First, a substrate having an active device formed thereon is provided. The active device has a gate, a gate dielectric layer, and a semiconductor layer having a channel, a source, and a drain region. Then, a dielectric layer is formed to cover the active device, and a photo-resist layer having a first photo-resist block and a second photo-resist block thinner than the first photo-resist block is formed on the dielectric layer. The second photo-resist block has openings above the source and the drain region, respectively. The source and the drain regions are exposed by removing part of the dielectric layer with the photo-resist layer as a mask. A second metal layer is formed after removing the second photo-resist block. A source and a drain are formed after removing the first photo-resist block. A pixel electrode connected to the drain is formed.

Abstract: A wafer comprising a low-k dielectric layer is refurbished for reuse. Initially, a removable layer is provided on the wafer. The low-k dielectric layer is formed over the removable layer. The overlying low-k dielectric layer is removed from the wafer by etching away the removable layer by at least partially immersing the wafer in an etching solution. Thereafter, another low-k dielectric layer can be formed over another removable layer.

Abstract: Disclosed is a method of fabricating a liquid crystal display (LCD) device in which a photosensitive film is selectively patterned using a half-tone mask, and then a portion of a passivation layer at a pixel area is selectively removed to secure an penetration path of a stripper. Additionally, a crack is generated on a conductive film formed on a photosensitive film pattern through a predetermined heat treatment to facilitate a lift-off process. Thus, the number of masks can be reduced to simplify the fabrication process of the LCD device and reduce fabrication costs.

Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a plasma source to provide an increased reactive species density. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation.

Abstract: A patterning method for a semiconductor substrate is disclosed. A substrate is provided and a stack structure is laid thereon. The stack layer includes at least a target layer and a pad layer sequentially formed on the substrate. Follow by a lithography process, wherein photoresists are laid on the stack layer to form a plurality of photoresist elements. Thus, a plurality of pattern is formed on the target layer, and a portion of target layer's surface is exposed. Lastly, ion implanting is provided and defines a doped area as hard mask for the etching process.

Abstract: A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy formularized as M1M2R wherein M1 is cobalt (Co) or molybdenum (Mo), M2 is tungsten (W), molybdenum (Mo), rhenium (Re) or vanadium (V), and R is boron (B) or phosphorus (P).

Abstract: Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer.

Abstract: A manufacturing method for an electronic substrate, includes: preparing a substrate and a mask having a predetermined region; forming a wiring pattern on the substrate; forming an aperture portion in the predetermined region of the mask; affixing the mask on the substrate; and removing at least a part of the wiring pattern through the aperture portion of the mask thereby forming the electronic element on the substrate.

Abstract: Ultrafine dimensions, smaller than conventional lithographic capabilities, are formed employing an efficient inverse spacer technique comprising selectively removing spacers. Embodiments include forming a first mask pattern over a target layer, forming a spacer layer on the upper and side surfaces of the first mask pattern leaving intermediate spaces, depositing a material in the intermediate spacers leaving the spacer layer exposed, selectively removing the spacer layer to form a second mask pattern having openings exposing the target layer, and etching the target layer through the second mask pattern.

Abstract: A method of manufacturing a device includes doping a low voltage threshold area and a high voltage threshold area. Gate structures are formed over the low voltage threshold and high voltage threshold areas while protecting the gate structure over the low voltage threshold area. A silicidation process is performed over the high voltage threshold area while the gate structure over the low voltage threshold area remains protected. Siliciding includes depositing metal on the gate of the high voltage threshold area and annealing the metal, the metal is deposited either by CVD or sputtering followed by anneal to fully suicide the gate structure of the high voltage threshold area. The metal, preferably cobalt or nickel is deposited to a thickness of approximately 500 ?, annealed for about 3 minutes at about 400° C.

Abstract: A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial polymer containing silicon that is deposited over a gate conductor layer and covered by a cover layer. The sacrificial polymer layer is patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the polymer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.

Abstract: A method for the production of a planar structure is disclosed. The method comprises producing on a substrate a plurality of structures of substantially equal height, and there being a space in between the plurality of structures. The method further comprises providing a fill layer of electromagnetic radiation curable material substantially filling the space between the structures. The method further comprises illuminating a portion of the fill layer with electromagnetic radiation, hereby producing a exposed portion and an unexposed portion, the portions being separated by an interface substantially parallel with the first main surface of the substrate. The method further comprises removing the portion above the interface.

Abstract: A method of patterning a transparent conductive film adaptive for selectively etching a transparent conductive film without any mask processes, a thin film transistor for a display device using the same and a fabricating method thereof are disclosed. In the method of patterning the transparent conductive film, an inorganic material substrate is prepared. An organic material pattern is formed at a desired area of the inorganic material substrate. A thin film having a different crystallization rate depending upon said inorganic material and said organic material is formed. The thin film is selectively etched in accordance with said crystallization rate.

Abstract: This invention relates to etching solutions which comprise hydrofluoric acid and organic solvents for use in the process for the production of integrated circuits. The etching solutions according to the invention are particularly suitable for the selective etching of doped silicate layers.

Abstract: A thin film transistor substrate and a fabricating method thereof for simplifying a process are disclosed. In a liquid crystal display device according to the present invention, a gate line is provided on a substrate. A data line crosses the gate line with having a gate insulating film therebetween to define a pixel area. A thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode opposed to the source electrode and a semiconductor layer for defining a channel between the source electrode and the drain electrode. A pixel electrode is connected to the drain electrode and is provided at said pixel area. Herein, said data line, said source electrode and said drain electrode have a double-layer structure in which a source/drain metal pattern and a transparent conductive pattern are built. Said pixel electrode is formed by an extension of the transparent conductive pattern of the drain electrode.

Abstract: A method is invented for processing a thin-film head/semiconductor wafer. A layer of polymer is applied onto a wafer. A layer of dielectric material is added above the polymer layer. A layer of photoresist is added above the dielectric layer. The photoresist layer is patterned using a photolithography process. Exposed portions of the dielectric layer are removed. Exposed portions of the polymer layer are removed. Exposed portions of the wafer are removed. The polymer layer and any material thereabove is removed after hard bias/leads deposition.

Abstract: A method for fabricating at least one mesa or ridge structure in a layer or layer sequence, in which a sacrificial layer (4) is applied and patterned above the layer or layer sequence. A mask layer is applied and patterned above the sacrificial layer for definition of the mesa or ridge dimensions. The sacrificial layer (4) and of the layer or layer sequence are removed so that the mesa or ridge structure is formed in the layer or layer sequence. A part of the sacrificial layer (4) is selectively removed from the side areas thereof which have been uncovered in the previous step, so that a sacrificial layer remains which is narrower in comparison with a layer that has remained above the sacrificial layer as seen from the layer or layer sequence. A coating is applied at least to the sidewalls of the structure produced in the previous steps so that the side areas of the residual sacrificial layer are not completely overformed by the coating material.