Abstract: A method of generating a layout pattern includes disposing a photoresist layer of a resist material on a substrate and disposing a top layer over of the photoresist layer. The top layer is transparent for extreme ultraviolet (EUV) radiation and the top layer is opaque for deep ultraviolet (DUV) radiation. The method further includes irradiating the photoresist layer with radiation generated from an EUV radiation source. The radiation passes through the top layer to expose the photoresist layer.

Abstract: Apparatuses and methods directed toward endpoint detection are disclosed herein. An example method at least includes forming a plurality of lines on a top surface of a sample; removing, a plurality of times, material from a working surface of the sample, the working surface different than the top surface; imaging, a plurality of times, the sample to at least capture the plurality of lines; and determining an endpoint based on a relative spatial characteristic between two or more lines of the plurality of lines.

Abstract: An apparatus for processing a substrate is disclosed and includes, in one embodiment, a twin chamber housing having two openings formed therethrough, a first pump interface member coaxially aligned with one of the two openings formed in the twin chamber housing, and a second pump interface member coaxially aligned with another of the two openings formed in the twin chamber housing, wherein each of the pump interface members include three channels that are concentric with a centerline of the two openings.

Abstract: A method for forming openings in an underlayer includes: forming a photoresist layer on an underlayer formed on a substrate; exposing the photoresist layer; forming photoresist patterns by developing the exposed photoresist layer, the photoresist patterns covering regions of the underlayer in which the openings are to be formed; forming a liquid layer over the photoresist patterns; after forming the liquid layer, performing a baking process so as to convert the liquid layer to an organic layer in a solid form; performing an etching back process to remove a portion of the organic layer on a level above the photoresist patterns; removing the photoresist patterns, so as to expose portions of the underlayer by the remaining portion of the organic layer; forming the openings in the underlayer by using the remaining portion of the organic layer as an etching mask; and removing the remaining portion of the organic layer.

Abstract: A method of forming patterns of a semiconductor device includes forming a photoresist pattern, which contains a first carbon compound, on a substrate, reforming a top surface of the photoresist pattern to form an upper mask layer which contains a second carbon compound, different from the first carbon compound, on the photoresist pattern, and etching a portion of the substrate using the upper mask layer and the photoresist pattern as an etch mask.

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

Abstract: A method of forming a semiconductor device includes following steps. First of all, a substrate is provided, and a stacked structure is formed on the substrate. Then, a patterned silicon-containing mask layer is formed on the stacked structure, and the stacked structure is partially removed through the patterned silicon-containing mask layer, to form plural openings in the stacked structure. Following these, a bromine covering process is performed, to form a bromide layer on a portion of the patterned silicon-containing mask layer, and a bromide sublimation process is then performed, to completely remove the bromide layer.

Abstract: For simplifying the manufacture of a MEMS structural component including a deflectable diaphragm which spans an opening in the rear side of the structural component, and including a fixed counter-element, which is provided with passage openings, the counter-element from the base substrate of the MEMS structural component is patterned and the deflectable diaphragm is implemented in a layered structure on the base substrate. These measures are intended to improve the diaphragm properties and reduce the overall height of the MEMS structural component.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes forming a main pattern on a substrate; forming a spacer on sidewalls of the main pattern; forming a cut pattern having an opening by a first lithography process; and performing a cut process to selectively remove portions of the spacer within the opening of the cut pattern while the main pattern remains unetched, thereby defining a circuit pattern by the main pattern and the spacer. The circuit pattern includes a sharp jog.

Abstract: An organic film can be etched while suppressing damage on an underlying layer. A method of etching the organic film includes etching the organic film within a processing vessel of a plasma processing apparatus which accommodates a processing target object. A processing gas containing a hydrogen gas and a nitrogen gas is supplied into the processing vessel, and plasma of the processing gas is generated. Further, a flow rate ratio of the hydrogen gas to a flow rate of the processing gas is set to be in a range from 35% to 75%, and a high frequency bias power for ion attraction to the processing target object is set to be in a range from 50 W to 135 W, in the etching of the organic film.

Abstract: A method of generating a photo mask for use during fabrication of a semiconductor device includes; generating an initial layout design including critical circuit paths and non-critical circuit paths by shielding all gate line patterns used to implement transistors in the critical circuits and non-critical circuits, and thereafter generating a layout design from the initial layout design by selectively un-shielding a non-critical gate line pattern among the gate line patterns used to implement a gate of a non-critical transistor in a non-critical circuit, while retaining the shielding of all critical gate line patterns among the gate line patterns.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a molding layer and a supporter layer on a semiconductor substrate, forming a multiple mask layer including a first mask layer and a second mask layer formed on the first mask layer, on the supporter layer. The first mask layer is formed of a material having an etch selectivity with respect to the molding layer and the second mask layer is formed of a material having an etch selectivity with respect to the supporter layer. The method includes forming a first mask pattern and a second mask pattern formed on the first mask pattern by patterning the multiple mask layer, etching the supporter layer by performing a first etching process using the second mask pattern as an etch mask, etching the molding layer, and forming a hole by performing a second etching process using the first mask pattern as an etch mask.

Abstract: A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Trenches are formed in a first dielectric then a sacrificial film is deposited onto the first dielectric and the trench surfaces formed therein. Planar sacrificial film is removed from the face of the first dielectric and bottom of the trenches, leaving only sacrificial films on the trench walls. A gap between the sacrificial films on the trench walls is filled in with a second dielectric. A portion of the second dielectric is removed to expose tops of the sacrificial films. The sacrificial films are removed leaving ultra-thin gaps that are filled in with a conductive material. The tops of the conductive material in the gaps are exposed to create “fence conductors.” Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors.

Abstract: Methods and systems for dicing a semiconductor wafer including a plurality of integrated circuits (ICs) are described. In one embodiment, a method involves adhering an adhesive tape to a thin water soluble dry film. The method involves applying the thin water soluble dry film adhered to the adhesive tape over a surface of the semiconductor wafer. The method involves removing the adhesive tape from the thin water soluble dry film. The thin water soluble dry film is patterned with a laser scribing process, exposing regions of the semiconductor wafer between the ICs. The method involves etching the semiconductor wafer through gaps in the patterned thin water soluble dry film, and removing the thin water soluble dry film.

Abstract: The present invention provides a composition enabling to form a fine negative photoresist pattern less suffering from surface roughness, and also provides a pattern formation method employing that composition. The composition is used for miniaturizing a resist pattern by fattening in a process of forming a positive resist pattern from a chemically amplified positive-working type resist composition, and it contains a polymer comprising a repeating unit having an amino group, a solvent, and an acid. In the pattern formation method, the composition is cast on a positive photoresist pattern beforehand obtained by development and is then heated to form a fine pattern.

Abstract: Techniques disclosed herein include increasing pattern density for creating high-resolution contact openings, slots, trenches, and other features. A first line-generation sequence creates a first layer of parallel lines of alternating and differing material by using double-stacked mandrels, sidewall image transfer, and novel planarization schemes. This line-generation sequence is repeated on top of the first layer of parallel lines, but with the second layer of parallel lines of alternating and differing material being oriented to elevationally cross lines of the first layer. Etching selective to one of the materials within the double stack of parallel lines results in defining a pattern of openings, slots, etc., which can be transferred into underlying layers. Such patterning techniques herein can quadruple a density of features in a given pattern, which can be described as created a pitch quad.

Abstract: A thin film transistor substrate is equipped with: an insulating substrate (10a); a gate electrode (2) constituted by a stack of a first barrier metal layer (3) formed of titanium and disposed over the insulating substrate (10a), a first copper layer (4) disposed over the first barrier metal layer (3), and a second barrier metal layer (5) formed of titanium and disposed over the first copper layer (4); a gate insulating layer (7) disposed covering the gate electrode (2); and a semiconductor layer (8) disposed over the gate insulating layer (7), and having a channel region (C) disposed overlapping the gate electrode (2).

Abstract: A method for manufacturing a light-emitting device includes a step of forming an etching resistant protection layer on a substrate provided with an organic planarizing layer, a step of forming a plurality of electrodes on the etching resistant protection layer, a step of forming an organic compound layer on the substrate provided with the plurality of electrodes, a step of forming a resist layer on the organic compound layer formed on parts of electrodes among the plurality of electrodes using a photolithographic method, and a step of removing the organic compound layer in a region not covered with the resist layer by dry etching, wherein an entire surface of the organic planarizing layer on the substrate on which steps up to the step of forming the plurality of electrodes have been performed is covered with at least one of the etching resistant protection layer and the electrode.

Abstract: Integrated optical waveguides and methods for the production thereof which have a patterned upper cladding with a defined opening to allow at least one side or at least one end of a light transmissive element to be air clad. The at least one side or at least one end is, for preference, a lens structure unitary with the waveguide or a bend. Also provided is a method of fabricating an optical waveguide with a patterned cladding.

Abstract: A manufacturing method of an organic light emitting diode (OLED) display includes manufacturing a mother substrate including a plurality of panels formed with a plurality of anodes for each pixel and a test pad connected to each anode of the panel. The method further includes loading the mother substrate into a plasma chamber and applying a plasma voltage to the test pad of the mother substrate to perform a plasma surface treatment process. The test pad is applied with a different plasma voltage for each pixel.

Abstract: The invention relates to a top-emissive organic light-emitting diode (OLED) (10) arranged to emit light having different emission colors, comprising a multi-layered structure provided with a first electrode, a second electrode and a functional layer enabling light emission disposed between the first electrode and the second electrode, wherein thickness (H1, H2) of the functional layer is modulated by allowing at least a portion of the functional layer to interact with a thickness modulator (5a, 5b, 5c), wherein the functional layer comprises a hole injection layer or the electron injection layer.

Abstract: A method of arranging a diamagnetic rod includes levitating a diamagnetic rod above a contact line at which a first magnet contacts a second magnet, the first magnet and the second magnet having diametric magnetization in a direction perpendicular to the contact line.

Abstract: A method for defining a template for directed self-assembly (DSA) materials includes forming an etch stop layer on a neutral material, forming a mask layer on the etch stop layer and forming an anti-reflection coating (ARC) on the mask layer. A resist layer is patterned on the ARC using optical lithography to form a template pattern. The ARC and the mask layer are reactive ion etched down to the etch stop layer in accordance with the template pattern to form a template structure. The ARC is removed from the mask layer and the template structure is trimmed to reduce a width of the template structure. A wet etch is performed to remove the etch stop layer to permit the neutral material to form an undamaged DSA template for DSA materials.

Abstract: A device having three evaporation sources and a unit for moving the respective evaporation sources in one chamber is used, whereby it becomes possible to increase efficiency of use of an evaporation material. Consequently, manufacturing cost can be reduced, and a uniform thickness can be obtained over an entire surface of a substrate even in the case in which a large area substrate is used.

Abstract: Disclosed herein is a Light Emitting Diode (LED) backlight unit without a Printed Circuit board (PCB). The LED backlight unit includes a chassis, insulating resin layer, and one or more light source modules. The insulating resin layer is formed on the chassis. The circuit patterns are formed on the insulating resin layer. The light source modules are mounted on the insulating resin layer and are electrically connected to the circuit patterns. The insulating resin layer has a thickness of 200 ?m or less, and is formed by laminating solid film insulating resin on the chassis or by applying liquid insulating resin to the chassis using a molding method employing spin coating or blade coating. Furthermore, the circuit patterns are formed by filling the engraved circuit patterns of the insulating resin layer with metal material.

Abstract: A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric.

Abstract: A method for fabricating a semiconductor device includes forming a mold layer over a substrate, wherein the mold layer includes a first sacrificial layer and a second sacrificial layer that are stacked, forming an insulation layer pattern that has an etch selectivity to the first sacrificial layer and the second sacrificial layer on the mold layer, etching the mold layer using the insulation layer pattern as an etch barrier to form storage node holes, forming a storage node conductive layer over a substrate structure including the insulation layer pattern and the mold layer that has been etched, performing a storage node isolation process that simultaneously forms storage nodes and forming the insulation layer pattern to a first thickness, and removing the first sacrificial layer and the second sacrificial layer.

Abstract: A device is prepared using a chemical vapor deposition method and has a patterned thin film on a substrate that is applied using a deposition inhibitor material. The deposition inhibitor material is a hydrophilic polymer that is a neutralized acid having a pKa of 5 or less, wherein at least 90% of the acid groups are neutralized. The deposition inhibitor material can be patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.

Abstract: A micromachine is generally formed using a semiconductor substrate such as a silicon wafer. One of the objects of the present invention is to realize further reduction in cost by integrating a minute structure and a semiconductor element controlling the minute structure over one insulating surface in one step. A minute structure has a structure in which a first layer formed into a frame-shape are provided over an insulating surface, a space is formed inside the frame, and a second layer is formed to cross over the first layer. Such a minute structure and a thin film transistor can be integrated over one insulating surface in one step.

Abstract: Embodiments described herein relate to a method for processing a substrate. In one embodiment, the method includes introducing a gas mixture comprising a hydrocarbon source and a diluent gas into a deposition chamber located within a processing system, generating a plasma from the gas mixture in the deposition chamber at a temperature between about 200° C. and about 700° C. to form a low-hydrogen content amorphous carbon layer on the substrate, transferring the substrate into a curing chamber located within the processing system without breaking vacuum, and exposing the substrate to UV radiation within the curing chamber at a curing temperature above about 200° C.

Abstract: The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.

Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

Abstract: A method for forming an electronic device having a semiconducting active layer comprising a polymer, the method comprising aligning the chains of the polymer parallel to each other by bringing the polymer into a liquid-crystalline phase.

Abstract: A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed.

Abstract: A method of fabricating a light emitting diode array, comprising: providing a temporary substrate; forming a first light emitting stack and a second light emitting stack on the temporary substrate; forming a first insulating layer covering partial of the first light emitting stack; forming a wire on the first insulating layer and electrically connecting to the first light emitting stack and the second light emitting stack; forming a second insulating layer fully covering the first light emitting stack, the wire and partial of the second light emitting stack; forming a metal connecting layer on the second insulating layer and electrically connecting to the second light emitting stack; forming a conductive substrate on the metal connecting layer; removing the temporary substrate; and forming a first electrode connecting to the first light emitting stack.

Abstract: An organic semiconductor polymer and transistor are provided, the organic semiconductor polymer is represented by the following Chemical Formula (1)

Abstract: A device having three evaporation sources and a unit for moving the respective evaporation sources in one chamber is used, whereby it becomes possible to increase efficiency of use of an evaporation material. Consequently, manufacturing cost can be reduced, and a uniform thickness can be obtained over an entire surface of a substrate even in the case in which a large area substrate is used.

Abstract: Openings are formed in first and second mask layers. Next, diameter of the opening in the second mask layer is enlarged so that the diameter of the opening in the second mask layer becomes larger by a length X than diameter of the opening in the first mask layer. Thereafter, mask material is formed into the opening in the second mask layer, to form a cavity with a diameter X within the opening in the second mask layer. There is formed a mask which includes the second mask layer and the mask material having therein opening including the cavity.

Abstract: A method for generating an electrode layer pattern in an organic functional device (101; 201) comprising a first transparent electrode layer (103; 203), a second electrode layer (104; 204) and an organic functional layer (102; 202) sandwiched between said first and second electrode layers (103, 104; 203, 204). The method comprises the steps of arranging (601) a laser (704; 804) to irradiate said organic functional device (701; 801) through said first transparent electrode layer (103; 203), selecting (602) a set of laser parameters in order to enable said laser (704; 804) to locally modify an electric conductivity of said second electrode layer (104; 204), and locally modifying, by said laser (704; 804) in accordance with said set of laser parameters, the electric conductivity of said second electrode layer (104; 204), thereby generating said electrode layer pattern.

Abstract: An organic electroluminescent device includes: a switching element and a driving element connected to each other on a substrate including a pixel region; a planarization layer on the switching element and the driving element, the planarization layer having a substantially flat top surface; a cathode on the planarization layer, the cathode connected to the driving element; an emitting layer on the cathode; and an anode on the emitting layer.

Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Abstract: A chemical vapor deposition method such as an atomic-layer-deposition method for forming a patterned thin film includes applying a deposition inhibitor material to a substrate. The deposition inhibitor material is a hydrophilic polymer that is a neutralized acid having a pKa of 5 or less, wherein at least 90% of the acid groups are neutralized. The deposition inhibitor material is patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.

Abstract: Openings are formed in first and second mask layers. Next, diameter of the opening in the second mask layer is enlarged so that the diameter of the opening in the second mask layer becomes larger by a length X than diameter of the opening in the first mask layer. Thereafter, mask material is formed into the opening in the second mask layer, to form a cavity with a diameter X within the opening in the second mask layer. There is formed a mask which includes the second mask layer and the mask material having therein opening including the cavity.

Abstract: In one embodiment, a pattern formation method is disclosed. The method can place a liquid resin material on a workpiece substrate. The method can press a template against the resin material and measuring distance between a lower surface of a projection of the template and an upper surface of the workpiece substrate. The template includes a pattern formation region and a circumferential region around the pattern formation region. A pattern for circuit pattern formation is formed in the pattern formation region and the projection is formed in the circumferential region. The method can form a resin pattern by curing the resin material in a state of pressing the template. In addition, the method can separate the template from the resin pattern.

Abstract: A method of fabricating a light emitting diode array, comprising: providing a temporary substrate; forming a first light emitting stack and a second light emitting stack on the temporary substrate; forming a first insulating layer covering partial of the first light emitting stack; forming a wire on the first insulating layer and electrically connecting to the first light emitting stack and the second light emitting stack; forming a second insulating layer fully covering the first light emitting stack, the wire and partial of the second light emitting stack; forming a metal connecting layer on the second insulating layer and electrically connecting to the second light emitting stack; forming a conductive substrate on the metal connecting layer; removing the temporary substrate; and forming a first electrode connecting to the first light emitting stack.

Abstract: A method for forming an organic semiconductor film having a high carrier mobility is provided by having an average volatilization rate of a solvent within a prescribed range during a step of drying, at the time of applying a coating solution, which includes an organic semiconductor material and a non-halogen solvent, on a substrate. In such forming method, characteristic fluctuation in repeated use of the organic semiconductor film is suppressed, and an organic thin film transistor having an excellent film forming characteristic even on an insulator with reduced gate voltage threshold can be obtained.

Abstract: An organic electroluminescent device includes: a switching element and a driving element connected to each other on a substrate including a pixel region; a planarization layer on the switching element and the driving element, the planarization layer having a substantially flat top surface; a cathode on the planarization layer, the cathode connected to the driving element; an emitting layer on the cathode; and an anode on the emitting layer.

Abstract: Devices are presented including: a substrate including a dielectric region and a conductive region; a molecular self-assembled layer selectively formed on the dielectric region; and a capping layer formed on the conductive region, where the capping layer is an electrically conductive material such as: an alloy of cobalt and boron material, an alloy of cobalt, tungsten, and phosphorous material, an alloy of nickel, molybdenum, and phosphorous. In some embodiments, devices are presented where the molecular self-assembled layer includes one or more of a polyelectrolyte, a dendrimer, a hyper-branched polymer, a polymer brush, a block co-polymer, and a silane-based material where the silane-based material includes one or more hydrolysable substituents of a general formula RnSiX4-n, where R is: an alkyl, a substituted alkyl, a fluoroalkyl, an aryl, a substituted aryl, and a fluoroaryl, and where X is: a halo, an alkoxy, an aryloxy, an amino, an octadecyltrichlorosilane, and an aminopropyltrimethoxysilane.

Abstract: A lower-layer film to which a fluorine-doped polymer is added is formed on a film to be processed. The lower-layer film is baked. An intermediate film is formed on the lower-layer film. A resist film is formed on the intermediate film. The resist film is baked. A resist protection film is formed. The resist film is immersion-exposed. The resist film is developed to form a resist pattern.

Abstract: Methods for the production of integrated optical waveguides which have a patterned upper cladding with a defined opening to allow at least one side or at least one end of a light transmissive element to be air clad The at least one side or at least one end is, for preference, a lens structure unitary with the waveguide or a bend.