Abstract: The present invention is notably directed to an electro-optical device. This device has a layer structure, which comprises a stack of III-V semiconductor gain materials, an n-doped layer and a p-doped layer. The III-V materials are stacked along a stacking direction z, which is perpendicular to a main plane of the stack. The n-doped layer extends essentially parallel to the main plane of the stack, on one side thereof. The p-doped layer too extends essentially parallel to this main plane, but on another side thereof. A median vertical plane can be defined in the layer structure, which plane is parallel to the stacking direction z and perpendicular to the main plane of the stack. Now, the device further comprises two sets of ohmic contacts, wherein the ohmic contacts of each set are configured for vertical current injection in the stack of III-V semiconductor gain materials.

Abstract: This invention relates to a method of forming a fine pattern, and more particularly, to a method of forming a fine pattern using only sputtering, which enables the fine pattern to be simply formed at low cost, thus exhibiting superior productivity and economic benefits.

Abstract: Provided herein are multi-layer stacks for use in extreme ultraviolet lithography tailored to achieve optimum etch contrast to shrink features and smooth the edges of features while enabling use of an optical leveling sensor with little or reduced error. The multi-layer stacks may include an atomically smooth layer with an average local roughness of less than a monolayer, and one or more underlayers, which may be between a target layer to be patterned and a photoresist. Also provided are methods of depositing multi-layer stacks for use in extreme ultraviolet lithography.

Abstract: A lifting-off method and a manufacturing method for a thin film transistor (TFT) array substrate using the same are provided. A lifting-off method comprises forming a cavitation jet flow by using a lifting-off solution, and impacting a to-be-lifted-off surface of a substrate by means of the cavitation jet flow to remove a photoresist and a film deposited on the photoresist over the to-be-lifted-off surface. The disclosure may be applied to manufacturing processes for semiconductor devices or TFT array substrate.

Abstract: The present invention related to a lift-off structure adapted to a substrate having a photoelectric device, the structure comprising: a buffer layer, forming on the substrate; an upper sacrificial layer, forming on the buffer layer; an etch stop layer, forming on the upper sacrificial layer, and the photoelectric device structure forming on the etch stop layer.

Abstract: A method for fabricating a semiconductor lighting chip includes steps of: providing a substrate; forming a first etching layer on the substrate; forming a connecting layer on the first etching layer; forming a second etching layer on the connecting layer; forming a lighting structure on the second etching layer; and etching the first etching layer, the connecting layer, the second etching layer and the lighting structure, wherein an etching rate of the first etching layer and the second etching layer is lager than that of the connecting layer and the lighting structure, thereby to form the connecting layer and the lighting structure each with an inverted frustum-shaped structure.

Abstract: A method for fabricating a semiconductor lighting chip includes steps of: providing a substrate with a first block layer dividing an upper surface of the substrate into a plurality of epitaxial regions; forming a first semiconductor layer on the epitaxial regions; forming a second block layer partly covering the first semiconductor layer; forming a lighting structure on an uncovered portion of the first semiconductor layer; removing the first and the second block layers thereby defining clearances at the bottom surfaces of the first semiconductor layer and the lighting structure; and permeating etching solution into the first and second clearances to etch the first semiconductor layer and the lighting structure, thereby to form each of the first semiconductor layer and the lighting structure with an inverted frustum-shaped structure.

Abstract: A method for fabricating an LED chip is provided. Firstly, a SiO2 pattern layer is formed on a top surface of a substrate. Then, lighting structures are grown on a portion of the top surface of substrate without the SiO2 pattern layer thereon. Thereafter, the SiO2 pattern layer is removed by wet etching to form spaces between bottoms of the lighting structures and substrate. An etching solution is used to permeate into the spaces and etch the lighting structures from the bottoms thereof, whereby the lighting structures each with a trapezoid shape is formed. Sidewalls of each of the lighting structures are inclined inwardly along a top-to-bottom direction.

Abstract: A method of forming a patterned layer, including the steps of: (i) depositing via a liquid medium a first material onto a substrate to form a first body on said substrate; (ii) depositing via a liquid medium a second material onto said substrate to form a second body, wherein said first body is used to control said deposition of said second material so as to form a patterned structure including said first and second bodies; and (iii) using said patterned structure to control the removal of selected portions of a layer of material in a dry etching process or in a wet etching process using a bath of etchant.

Abstract: A method for fabricating optical devices on a reusable handle substrate. The method includes providing a handle substrate having a surface region. The method also includes forming a plurality of optical device using at least an epitaxial growth process overlying the surface region and then releasing the handle substrate from the plurality of optical devices. The method reuses the handle substrate for another fabrication process.

Abstract: Ordered, two-dimensional arrays of pyramidal particulates and related methods of preparation.

Abstract: The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer.

Abstract: Systems and methods of semiconductor device fabrication and layout generation are disclosed. An exemplary method includes processes of depositing a layer of a first material and patterning the layer to form an initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the first pattern on the substrate and etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the filled pattern to remove portions of the final material beyond dimensions of the layout elements.

Abstract: Systems and methods for MEMS device fabrication. A layer of photoresist is formed on a substrate. A first region of the substrate is exposed to a radiation source through a photomask. The first region of exposed photoresist is developed with a developer solution in order to etch the exposed regions to a first depth. A second region is exposed to radiation through a second photomask. The second photomask defines areas in which a bump feature is intended on the substrate. The second region is developed with the developer solution, preparing the first and second exposed regions for a layer of metal. A layer of metal is deposited on the substrate, such that the metal attaches to both the substrate and any remaining photoresist on the substrate. The remaining photoresist and its attached metal is dissolved away leaving an interconnect pattern and at least one bump feature.

Abstract: A method for forming a fine-pitch pattern on a semiconductor substrate is provided. The method includes patterning the semiconductor substrate to form a plurality of fine lines, forming a thermal oxide layer on the fine lines, polishing the thermal oxide layer to expose a top surface of the fine lines; etching the fine lines using the thermal oxide layer as a mask to expose first portions of the semiconductor substrate, etching a central bottom portion of the thermal oxide layer to expose second portions of the semiconductor substrate, and etching the semiconductor substrate using the etched thermal oxide layer as a mask.

Abstract: A method of forming a patterned material layer, the method comprising: a resist layer forming step of forming a resist layer on a substrate, the resist layer including a first photosensitive resin layer, an intermediate resin layer, and a second photosensitive resin layer; an exposing step; a developing step of partly removing the resist layer so as to form a trench exposing the substrate and partly removing the intermediate resin layer so as to form a groove on a side face of the trench, thereby forming a resist frame; a vacuum coating step of forming a vacuum coating layer having a material pattern part covering the exposed part of the substrate and a part to lift off covering the resist frame; and a liftoff step of removing the part to lift off in the vacuum coating layer together with the resist frame, so as to yield a patterned material layer.

Abstract: A wafer comprising a low-k dielectric layer is refurbished for reuse. Initially, a removable layer is provided on the wafer. The low-k dielectric layer is formed over the removable layer. The overlying low-k dielectric layer is removed from the wafer by etching away the removable layer by at least partially immersing the wafer in an etching solution. Thereafter, another low-k dielectric layer can be formed over another removable layer.

Abstract: A method of forming a gate line and gate electrode and a method of manufacturing a TFT array substrate. The metal gate line and gate electrode can be formed by: providing a substrate, forming a photoresist layer on the substrate, a photoresist pattern being formed complementary with that of the gate line and gate electrode, forming a metal Cu thin film or a composite thin film comprising a metal Cu thin film on the substrate, and removing the photoresist pattern and the metal Cu thin film or composite thin film comprising the metal Cu thin film formed thereon from the substrate.

Abstract: The present invention discloses a method for fabricating a light emitting diode element, which incorporates an epitaxial process with an etching process to etch LED epitaxial layers bottom up and form side-protrudent structures, whereby the LED epitaxial layers have non-rectangular inclines, which can solve the problem of total reflection and promote light-extraction efficiency. Further, the method of the present invention has a simple fabrication process, which can benefit mass production and lower cost.

Abstract: A metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is formed on the semiconductor substrate having the lower metal line, and a metal line forming region exposing at least a portion of the lower metal line is defined in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and includes a WNx layer, a W—N—B ternary layer, and a Ti—N—B ternary layer. A wetting layer is formed on the diffusion barrier and is made of one of a Ti layer or a TiN layer. An upper metal line is formed on the wetting layer to fill the metal line forming region of the insulation layer.

Abstract: A method of etching semiconductor structures is disclosed. The method may include etching an SRAM portion of a semiconductor device, the method comprising: providing a silicon substrate layer, a nitride layer thereover, an optical dispersive layer over the nitride layer, and a silicon anti-reflective coating layer thereover; etching the silicon anti-reflective coating layer using an image layer; removing the image layer; etching the optical dispersive layer while removing the silicon anti-reflective coating layer; etching the optical dispersive layer and the nitride layer simultaneously; and etching the optical dispersive layer, the nitride layer, and the silicon substrate simultaneously.

Abstract: A method is provided for fabricating current-carrying formation on substrates. The method includes providing a substrate including a layer of a voltage switchable dielectric material, forming a mask over the layer of the voltage switchable dielectric material, and forming an electrically conductive layer. The mask includes gaps and the electrically conductive layer is formed in the gaps. The voltage switchable dielectric material has a characteristic voltage and the electrically conductive layer is formed by applying a voltage in excess of the characteristic voltage to the substrate and depositing the electrically conductive material through an electrochemical process such as electroplating.

Abstract: A method of forming a suspended structure is disclosed. Initially, a substrate is provided. A patterned first sacrificial layer and a patterned second sacrificial layer are formed on a front surface of the substrate. The second sacrificial layer has an opening exposing a part of the substrate and a part of the first sacrificial layer. A structural layer is formed covering the abovementioned sacrificial layers. Thereafter, a lift-off process is performed to remove the second sacrificial layer and define the pattern of the structural layer. A first etching process is performed on a back surface of the substrate utilizing the first sacrificial layer as an etching barrier and a through hole is formed under the first sacrificial layer. A second etching layer is performed to remove the first sacrificial layer and a suspended structure is thereby formed.

Abstract: A voltage is applied across gate electrodes (103A) and (103B) in a two-dimensional electronic system (101) placed under a magnetic field, and the polarity of an electric current passed between ohmic electrodes (102D) and (102S) is selected to bring about inversion of electron spins based on a non-equilibrium distribution of electrons in a quantum Hall edge state and to initialize the polarization of nuclear spins. An oscillatory electric field of a nuclear magnetic resonance frequency is applied to coplanar waveguides (104A) and (104B) to control the nuclear spin polarization. The controlled spin polarization is read out by measuring the Hall resistance from ohmic electrodes (102VA) and (102VB).

Abstract: A method for fabricating at least one mesa or ridge structure in a layer or layer sequence, in which a sacrificial layer (4) is applied and patterned above the layer or layer sequence. A mask layer is applied and patterned above the sacrificial layer for definition of the mesa or ridge dimensions. The sacrificial layer (4) and of the layer or layer sequence are removed so that the mesa or ridge structure is formed in the layer or layer sequence. A part of the sacrificial layer (4) is selectively removed from the side areas thereof which have been uncovered in the previous step, so that a sacrificial layer remains which is narrower in comparison with a layer that has remained above the sacrificial layer as seen from the layer or layer sequence. A coating is applied at least to the sidewalls of the structure produced in the previous steps so that the side areas of the residual sacrificial layer are not completely overformed by the coating material.