Abstract: A method of fabricating nanostructures using macro pre-patterns according to the present invention, which comprises either depositing a target material on a substrate having macro pre-patterns formed thereon, or applying a target material to a substrate and then forming macro pre-patterns on the substrate, and then depositing the target material on the side surface of the macro pre-patterns by an ion bombardment phenomenon occurring during etching, provides a three-dimensional nanostructures with high aspect ratio and uniformity can be fabricated by a simple process at low cost by using the ion bombardment phenomenon occurring during physical ion etching, thereby achieving the high performance of future nano-devices, such as nanosized electronic devices, optical devices, bio devices and energy devices.

Abstract: An apparatus that includes a solution bath of a seasoned solution, the seasoned solution containing a mixture of hydrofluoric acid, nitric acid, and acetic acid; and one or more silicon wafers being suspended in a position above the solution bath, wherein at least a portion of the mixture having been used in thinning the one or more silicon wafers.

Abstract: The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.

Abstract: A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.

Abstract: Various embodiments disclose a method for fabricating a semiconductor structure including a plurality of vertical transistors each having different threshold voltages. In one embodiment the method includes forming a structure having at least a substrate, a source contact layer on the substrate, a first spacer layer on the source contact layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer. A first trench is formed in a first region of the structure. A first channel layer having a first doping concentration is epitaxially grown in the first trench. A second trench is formed in a second region of the structure. A second channel layer having a second doping concentration is epitaxially grown in the second trench. The second doping concentration is different from the first doping concentration.

Abstract: A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved.

Abstract: A method of forming a multilayer hard mask includes the following steps. An unpatterned multilayer hard mask is formed on a semiconductor substrate. The unpatterned multilayer hard mask includes a first hard mask layer formed on the semiconductor substrate and a second hard mask layer directly formed on the first hard mask layer. A treatment is performed on a top surface of the first hard mask layer before the step of forming the second hard mask layer, and the treatment is configured to remove impurities on the first hard mask layer and form dangling bonds on the top surface of the first hard mask layer. Defects related to the first hard mask layer and the second hard mask layer may be reduced, and the manufacturing yield may be enhanced accordingly.

Abstract: A method of forming contacts for a semiconductor device structure comprises forming contact holes extending into neighboring semiconductive pillars and into a nitride material of nitride-capped electrodes. Composite structures are formed within the contact holes and comprise oxide structures over sidewalls of the contact holes and nitride structures over the oxide structures. Conductive structures are formed over inner sidewalls of the composite structures. Additional nitride-capped electrodes are formed over the conductive structures and extend perpendicular to the nitride-capped electrodes. Pairs of nitride spacers are formed over opposing sidewalls of the additional nitride-capped electrodes and are separated from neighboring pairs of nitride spacers by apertures extending to upper surfaces of a portion of the neighboring semiconductive pillars. Portions of the oxide structures are removed to expose sidewalls of the portion of the neighboring semiconductive pillars.

Abstract: A method of forming a semiconductor device is disclosed. A substrate having a first area and a second area is provided. A target layer and a hard mask layer are sequentially formed on the substrate in the first area and in the second area. Transfer patterns are formed in a spacer form on the hard mask layer in the first area. A photoresist layer is formed directly on the hard mask layer, and covers the transfer patterns and the hard mask layer in the first area and in the second area. The photoresist layer in the first area is removed. The hard mask layer is patterned by using the transfer patterns as a mask.

Abstract: A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first heavily-doped region formed in the substrate and having the first conductivity type, a second heavily-doped region formed in the substrate and having the first conductivity type, and an embedded layer formed in the substrate and separated from the first and second heavily-doped regions. The embedded layer has a second conductivity type different from the first conductivity type. A portion of the embedded layer is beneath the first heavily-doped region. A third heavily-doped region is formed in the substrate, between the first and second heavily-doped regions, and contacting the embedded layer, and has the second conductivity type.

Abstract: Disclosed is a display device and an electronic apparatus incorporating the display device. The display device includes a transistor and a planarization film over the transistor. The planarization film has an opening where an edge portion is rounded. The display device further includes a first electrode over the planarization film and an organic resin film over the first electrode. The organic resin film also has an opening where an edge portion is rounded. The organic resin film is located in the opening of the planarization film. The first electrode and the transistor are electrically connected to each other through a conductive film. The first electrode is in contact with a top surface of the conductive film. Over the first electrode, a light-emitting member and a second electrode are provided.

Abstract: A method of producing a patterned inorganic thin film dielectric stack includes providing a substrate. A first patterned deposition inhibiting material layer is provided on the substrate. A first inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the first deposition inhibiting material layer is not present using an atomic layer deposition process. The first deposition inhibiting and first inorganic thin film dielectric material layers are simultaneously treated after deposition of the first inorganic thin film dielectric material layer. A second patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the second deposition inhibiting material layer is not present using an atomic layer deposition process.

Abstract: A method of producing an inorganic thin film dielectric material layer includes providing a substrate. A first inorganic thin film dielectric material layer is deposited on the substrate using an atomic layer deposition process. The first inorganic thin film dielectric material layer is treated after its deposition. A patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the deposition inhibiting material layer is not present using an atomic layer deposition process.

Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

Abstract: Disclosed is a display device and an electronic apparatus incorporating the display device. The display device includes a transistor and a planarization film over the transistor. The planarization film has an opening where an edge portion is rounded. The display device further includes a first electrode over the planarization film and an organic resin film over the first electrode. The organic resin film also has an opening where an edge portion is rounded. The organic resin film is located in the opening of the planarization film. The first electrode and the transistor are electrically connected to each other through a conductive film. The first electrode is in contact with a top surface of the conductive film. Over the first electrode, a light-emitting member and a second electrode are provided.

Abstract: Disclosed is a display device and an electronic apparatus incorporating the display device. The display device includes a transistor and a planarization film over the transistor. The planarization film has an opening where an edge portion is rounded. The display device further includes a first electrode over the planarization film and an organic resin film over the first electrode. The organic resin film also has an opening where an edge portion is rounded. The organic resin film is located in the opening of the planarization film. The first electrode and the transistor are electrically connected to each other through a conductive film. The first electrode is in contact with a top surface of the conductive film. Over the first electrode, a light-emitting member and a second electrode are provided.

Abstract: A method for applying a predetermined structure of a structural material to a semiconductor element. The method includes the following steps: A) partially covering a surface of the semiconductor element with a masking layer, B) applying a film of a structural material to the masking layer and to the surface of the semiconductor element in the zones that are devoid of the masking layer and C) removing the masking layer together with the structural material present on the masking layer. The method according to the invention provides that between process steps B and C, the film of structural material is partially removed in a process step B2.

Abstract: An electronic device includes at least a substrate, an area on the substrate which has to be protected against moisture and/or oxygen, at least one contact, and an encapsulation layer system including at least a first inorganic layer. The at least one contact extends from the sealed area to a part of the substrate not sealed by the encapsulation layer system. The contact includes a shunt, which is an interruption bridged by an electrically conductive bridge. The first inorganic layer of the encapsulation system is applied so that it is in direct physical contact with the electrically conductive bridge. The bridge has a structure and shape which can be sealingly covered by the encapsulation layer system and is made from a material through which no moisture and/or oxygen can penetrate.

Abstract: An image sensor including a first region where a pad is to be formed, and a second region where a light-receiving element is to be formed. A pad is formed over a substrate of the first region. A passivation layer is formed over the substrate of the first and second regions to expose a portion of the pad. A color filter is formed over the passivation layer of the second region. A microlens is formed over the color filter. A bump is formed over the pad. A protective layer is formed between the bump and the pad to expose the portion of the pad.

Abstract: A display device according to the present invention includes a barrier layer formed over the transistor and a planarization layer formed over the barrier layer. The planarization layer has an opening and an edge portion of the planarization layer formed at the opening of the planarization layer is rounded. Further, a resin film is formed over the planarization layer and in the opening of the planarization layer, and the resin film also has an opening and an edge portion of the resin film formed at the opening of the resin film is rounded. A light emitting member is formed over the resin film.

Abstract: By using a first substrate which has a light-transmitting property and whose first face is provided with a light-absorbing layer, a mixture including an organic compound and an inorganic material is irradiated with light having a wavelength, which is absorbed by the inorganic material to heat the mixture, and thereby a film of the organic compound included in the mixture is formed on the first face of the first substrate. Then, the first face of the first substrate and a deposition surface of a second substrate are arranged to be adjacent to or in contact with each other, irradiation with light having a wavelength, which is absorbed by the light-absorbing layer is conducted from a second face side of the first substrate, to heat the organic compound, and thereby at least part of the organic compound is formed as a film on the deposition surface of the second substrate.

Abstract: An array substrate includes a substrate including a display area and a peripheral area surrounding the display area, a transistor layer formed in the display area of the substrate and electrically connected to a gate line and a data line, a color filter formed in a pixel region on the transistor layer, a first light blocking member disposed between adjacent color filters, a first transparent member formed on the first light blocking member to cover the first light blocking member, a first color pattern formed in a peripheral area of the substrate and including substantially the same material as the color filter, and a second transparent member including substantially the same material as the first transparent member. The second transparent member is disposed in the peripheral area of the substrate to cover the first color pattern.

Abstract: Example methods may provide a thin film etching method. Example thin film etching methods may include forming a Ga—In—Zn—O film on a substrate, forming a mask layer covering a portion of the Ga—In—Zn—O film, and etching the Ga—In—Zn—O film using the mask layer as an etch barrier, wherein an etching gas used in the etching includes chlorine. The etching gas may further include an alkane (CnH2n+2) and H2 gas. The chlorine gas may be, for example, Cl2, BCl3, and/or CCl3, and the alkane gas may be, for example, CH4.

Abstract: A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch can be carried out to expose at least a portion of the sidewall, causing the dielectric hard mask to recede to a greater degree in the lateral direction than the vertical direction. The process may include second etching the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded hard mask. The thinned semiconductor fin may have a characteristic dimension that can exceed photolithography limits. Electronic devices may include the thinned semiconductor fin as part of a field effect transistor.

Abstract: A method for manufacturing a solid-state image capturing apparatus including a pixel array constituted of a plurality of pixels, is provided, where each of the plurality of pixels includes a photoelectric conversion section, the method comprising the steps of: forming an impurity diffusion area in a surface area of a semiconductor substrate; and forming a plurality of different impurity diffusion areas in the surface area of the semiconductor substrate, other than the impurity diffusion area constituting the photoelectric conversion section.

Abstract: On one face of a semiconductor wafer 1 having a first face (principal face) 1a and a second face (rear face) 1b, a protection film 2 is formed. When allowing the semiconductor wafer 1 to be attracted onto an attracting face of an electrostatic chuck 6 which is heated to 400° C. or more, the semiconductor wafer 1 is attracted onto the attracting face via the protection film 2. While heating the semiconductor wafer 1 to 400° C. or more, an ion implantation is performed for the face of the semiconductor wafer 1 on which the protection film 2 is not formed. Thereafter, the protection film 2 is removed from the semiconductor wafer 1.

Abstract: A method and apparatus for an optically transparent field effect transistor on a substrate. The gate electrode, the dielectric, the semiconducting layer, the source electrode, and the drain electrode are optically transparent layers of nanoparticles that are formed using one or more graphic arts printing processes. The dielectric layer is in contact with the gate electrode, the semiconducting layer is in contact with the dielectric layer, and the source and drain electrodes are in contact with the semiconducting layer.

Abstract: A junction field effect transistor comprises an insulating layer formed in a substrate. A source region of a first conductivity type is formed on the insulating layer, and a drain region of the first conductivity type is formed on the insulating layer and spaced apart from the drain region. A channel region of the first conductivity type is located between the source region and the drain region and formed on the insulating layer. A gate region of the second conductivity type surrounds all surfaces of a length of the channel region such that the channel region is embedded within the gate region.

Abstract: A method of forming a patterned material layer, the method comprising: a resist layer forming step of forming a resist layer on a substrate, the resist layer including a first photosensitive resin layer, an intermediate resin layer, and a second photosensitive resin layer; an exposing step; a developing step of partly removing the resist layer so as to form a trench exposing the substrate and partly removing the intermediate resin layer so as to form a groove on a side face of the trench, thereby forming a resist frame; a vacuum coating step of forming a vacuum coating layer having a material pattern part covering the exposed part of the substrate and a part to lift off covering the resist frame; and a liftoff step of removing the part to lift off in the vacuum coating layer together with the resist frame, so as to yield a patterned material layer.

Abstract: A gate insulating film 3 is formed of an insulative inorganic material containing silicon and oxygen as a main material. The gate insulating film 3 contains hydrogen atoms. A part of the absorbance of infrared radiation of which wave number is in the range of 830 to 900 cm?1 is less than both the absorbance of infrared radiation at the wave number of 830 cm?1 and the absorbance of infrared radiation at the wave number of 900 cm?1 when the insulating film to which an electric field has never been applied is measured by means of Fourier Transform Infrared Spectroscopy at room temperature.

Abstract: Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern.

Abstract: The present invention provides a method for forming a semiconductor region having a desired shape, and also provides a method for manufacturing a semiconductor device with few variations. Moreover, the present invention provides a method for manufacturing a semiconductor device which can reduce the cost with a small number of materials and with high yield. According to the present invention, after a semiconductor film is partially oxidized to form an oxide layer, the semiconductor film is etched using the oxide layer as a mask to form a semiconductor region having a desired shape, and thereafter a semiconductor device using the semiconductor region is manufactured. Thus, a semiconductor region having a desired shape can be formed in a predetermined position without using a known photolithography step using a resist.

Abstract: An etching method which makes it possible to obtain a desired etching shape with ease, and a computer-readable storage medium storing a program for implementing the method. The etching method is executed by a substrate processing apparatus that performs plasma processing on a semiconductor wafer by plasma. The apparatus comprises a substrate accommodating chamber for accommodating the semiconductor wafer which has an oxide film and a resist film formed on the oxide film, and an upper electrode plate disposed in the substrate accommodating chamber and exposed in a processing space in the substrate accommodating chamber. At least part of the upper electrode plate is formed of a silicon-containing material. The upper electrode plate is sputtered by plasma, and the oxide film is etched by plasma.

Abstract: A method for fabricating a fine pattern in a semiconductor device includes forming a first polymer layer and a second polymer layer over an etch target layer. The second polymer layer is patterned at a first substrate temperature. The first polymer layer is etched at a second substrate temperature using an etch gas that does not include oxygen (O2). The first polymer layer is etched using the patterned second polymer layer as an etch mask. The etch target layer is then etched using the etched first polymer layer and the etched second polymer layer as an etch mask.

Abstract: In order to reduce an unevenness of a surface of a body, a sacrificial layer is applied to the surface, a chemical-mechanical polishing of the sacrificial layer and material of said body is performed to reduce the unevenness of the surface, and a remainder of the sacrificial layer, if any, may be removed.

Abstract: The present invention discloses a solar cell having a multi-layered nanostructure that is used to generate, transport, and collect electric charges. The multi-layered nanostructure comprises a cathode, a hole-blocking layer, a photo-active layer, and an anode. The hole-blocking layer is made of the material selected from the group consisting of the following: inorganic semiconducting material, metal oxide material and mixture of inorganic and metal oxide materials. The photo-active layer comprises a porous body and a conjugated polymer filler. The porous body is used as an electron acceptor while the conjugate polymer filler is as an electron donor. The conjugated polymer filler is formed in the pores of the porous body by in-situ polymerization. In addition, the invention discloses a method for preparing the solar cell having a multi-layered nanostructure.

Abstract: A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.

Abstract: The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region received about a peripheral edge of the semiconductor substrate. A layer comprising amorphous carbon is provided over the substrate outer surface. A masking layer is provided outwardly of the amorphous carbon-comprising layer. A resist layer is provided outwardly of the masking layer. At least a portion of the peripheral region of the outer surface includes the amorphous carbon-comprising layer and the resist layer, but is substantially void of the masking layer. The amorphous carbon-comprising layer is patterned using the resist layer and the masking layer effective to form a mask over the semiconductor substrate. After the patterning, the semiconductor substrate is processed inwardly of the mask through openings formed in the mask.

Abstract: A method for fabricating a multiple layer silicon nitride film on a semiconductor substrate is provided herein. In one embodiment, a method for fabricating a multiple layer silicon nitride film on a semiconductor substrate includes providing a substrate over which the multiple layer silicon nitride film is to be formed; and forming the multiple layer silicon nitride film in a single processing reactor by: (a) depositing a base layer comprising silicon nitride on the base structure; (b) depositing a middle layer comprising a stress-controlling material on the base layer; and (c) depositing a top layer comprising silicon nitride on the middle layer. The stress-controlling material selectively increases or reduces the stress of the multiple layer silicon nitride film as compared to silicon nitride alone.

Abstract: An object of the present invention is to provide an EL display device having high operation performance and reliability. A third passivation film 45 is disposed under the EL element 203 comprising a pixel electrode (anode) 46, an EL layer 47 and a cathode 48, and diffusion of alkali metals from the EL element 203 formed by ink jet method into TFTs is prevented. Further, the third passivation film 45 prevents penetration of moisture and oxygen from the TFTs, and suppress degradation of the EL element 203 by dispersing the heat generated by the EL element 203.

Abstract: The semiconductor device of this invention includes an active region formed from a group III nitride semiconductor grown on a substrate and an insulating oxide film formed in a peripheral portion of the active region by oxidizing the group III nitride semiconductor. On the active region, a gate electrode in Schottky contact with the active region extending onto the insulating oxide film and having an extended portion on the insulating oxide film is formed, and ohmic electrodes respectively serving as a source electrode and a drain electrode are formed with space from side edges along the gate length direction of the gate electrode.

Abstract: A method for forming a conductive wire structure for a semiconductor device includes defining a mandrel on a substrate, forming a conductive wire material on the mandrel by atomic layer deposition, and forming a liner material around the conductive wire material by atomic layer deposition.

Abstract: A method of forming a mask pattern for fabricating a semiconductor device. A first region and a second region, having an intersecting third region, are defined in the semiconductor substrate. An inorganic mask layer is etched in the first region to a predetermined thickness, and etched in the second region to another predetermined thickness. While the inorganic mask layer is etched in the first and second region, an organic mask layer is exposed in the third region. The organic mask layer exposed in the third region is removed to form a mask pattern. Consequently, double exposure is performed using the organic mask layer and the inorganic mask layer, so that a fine feature size that closely follows a desired layout can be formed, damage to the organic mask layer by ashing is prevented, and adhesiveness between the organic mask layer and the inorganic mask layer can be improved.

Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening by a metal deposition process employing a target which includes metal and silicon. The metal-silicide layer may then be annealed.

Abstract: An object of the present invention is to provide an EL display device having high operation performance and reliability. A third passivation film 45 is disposed under the EL element 203 comprising a pixel electrode (anode) 46, an EL layer 47 and a cathode 48, and diffusion of alkali metals from the EL element 203 formed by ink jet method into TFTs is prevented. Further, the third passivation film 45 prevents penetration of moisture and oxygen the TFTs, and suppress degradation of the EL element 203 by dispersing the heat generated by the EL element 203.

Abstract: Aperture masks and deposition techniques for using aperture masks are described. In addition, techniques for creating aperture masks and other techniques for using the aperture masks are described. The various techniques can be particularly useful in creating circuit elements for electronic displays and low-cost integrated circuits such as radio frequency identification (RFID) circuits. In addition, the techniques can be advantageous in the fabrication of integrated circuits incorporating organic semiconductors, which typically are not compatible with wet processes.

Abstract: A method for monitoring an ion implanter is disclosed. In one embodiment, the method comprises providing a wafer, forming a barrier layer on the surface of the wafer wherein the barrier layer has a substantial blocking effect on ion implantation, performing an ion implantation process to the wafer, performing a thermal treatment process, removing the barrier layer, and measuring a physical property of the wafer. The measured physical property of the wafer can be used to ascertain the status of the ion implanter. For instance, the measured physical property can be used to determine whether the ion implanter has problems when the energy or concentration of the implanted ions is changed.

Abstract: A laser ablation method is utilized to define the channel length of an organic transistor. A substrate is coated with a deposition of a metal or conductive polymer deposition, applied in a thin layer in order to enhance the resolution that can be attained by laser ablation. The laser ablation method can be used in a roll-to-roll process, and achieves speeds, volumes, prices and resolutions that are adequate to produce printed electronic technologies.

Abstract: A laser ablation method is utilized to define the channel length of an organic transistor. A substrate is coated with a deposition of a metal or conductive polymer deposition, applied in a thin layer in order to enhance the resolution that can be attained by laser ablation. The laser ablation method can be used in a roll-to-roll process, and achieves speeds, volumes, prices and resolutions that are adequate to produce printed electronic technologies.