Abstract: A method for fabrication of a semiconductor structure according to some embodiments of the present disclosure comprises following steps. A first mandrel is formed over a target layer over a substrate, wherein the first mandrel comprises a mandrel island connecting a first mandrel strip and a second mandrel strip. A first spacer is formed along first and second sidewalls of the mandrel island, the first mandrel strip, and the second mandrel strip. The first mandrel is then removed, and the target layer is patterned with the first spacer remains over the target layer. The first mandrel strip and the second mandrel strip are misaligned from one another.

Abstract: Ferroelectric capacitor is formed by conformably depositing a non-conductive dielectric over the etched first and second electrodes, and forming a metal cap or helmet over a selective part of the non-conductive dielectric, wherein the metal cap conforms to portions of sidewalls of the non-conductive dielectric. The metal cap is formed by applying physical vapor deposition at a grazing angle to selectively deposit a metal mask over the selective part of the non-conductive dielectric. The metal cap can also be formed by applying ion implantation with tuned etch rate. The method further includes isotopically etching the metal cap and the non-conductive dielectric such that non-conductive dielectric remains on sidewalls of the first and second electrodes but not on the third and fourth electrodes.

Abstract: A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing the die on a substrate; disposing a molding surrounding the die; removing a portion of the molding to expose a sidewall of the sacrificial layer, wherein a top surface of the molding is at a level substantially same as the top surface of the die; and removing the sacrificial layer from the die.

Abstract: A method of forming a fin forced stack inverter includes the following steps. A substrate including a first fin, a second fin and a third fin across a first active area along a first direction is provided, wherein the first fin, the second fin and the third fin are arranged side by side. A fin remove inside active process is performed to remove at least a part of the second fin in the first active area. A first gate is formed across the first fin and the third fin in the first active area along a second direction. The present invention also provides a 1-1 fin forced fin stack inverter formed by said method.

Abstract: Embodiments provide a patterning process. A photoresist layer is patterned. At least portions of the photoresist layer are converted from an organic material to an inorganic material by a deposition process of a metal oxide. All or some of the patterned photoresist layer may be converted to a carbon-metal-oxide. A metal oxide crust may be formed over the patterned photoresist layer. After conversion, the patterned photoresist layer is used as an etch mask to etch an underlying layer.

Abstract: A semiconductor structure includes an etching stop layer over an inter-layer dielectric (ILD) layer; a low-k dielectric layer over the etching stop layer; and a tapered conductor extending through the low-k dielectric layer and the etching stop layer and partially through the ILD layer; wherein the tapered conductor includes a recess disposed within the ILD layer and indented towards the etching stop layer and the low-k dielectric layer, and a protrusion surrounding the recess and protruded from the etching stop layer towards the ILD layer.

Abstract: A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

Abstract: A polyethylene terephthalate resin composition which is characterized by having a manganese element content of 30 to 60 ppm, a potassium element content of 2 to 10 ppm, an antimony element content of 70 to 150 ppm, a molar ratio of metal elements to phosphorus element (M/P=(M1+M2/2)/P) satisfying formula (1), and a gelation ratio of 5% by weight or less: 0.6?(M1+M2/2)/P?1.3??(1) wherein M1 represents the content (mol/t) of a bivalent metal element selected from the group consisting of Mg, Mn, and Ca; M2 represents the content (mol/t) of a monovalent metal element selected from the group consisting of Li, Na, and K; and P represents the content (mol/t) of phosphorus element.

Abstract: A method may include providing a substrate, comprising a patterning layer. The method may include forming a first pattern of first linear structures in the patterning layer, the first linear structures being elongated along a first direction. The method may include forming a mask over the patterning layer, the mask comprising a second pattern of second linear structures, elongated along a second direction, forming a non-zero angle with respect to the first direction. The method may include selectively removing a portion of the patterning layer while the mask is in place, wherein a first etch pattern is formed in the patterning stack, the first etch pattern comprising a two-dimensional array of cavities. The method may include directionally etching the first etch pattern using an angled ion beam, wherein a second etch pattern is formed, comprising the two-dimensional array of cavities, elongated along the first direction.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: A method for forming a fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm.

Abstract: A method and structure of forming air gaps with a sidewall image transfer process such as self-aligned double patterning to reduce capacitances. Different materials can be provided in the mandrel and non-mandrel regions to enlarge a process window for metal line end formation.

Abstract: A patterning method includes the following steps. A second mask layer is formed on a first mask layer. A patterning process is performed to the first mask layer and the second mask layer. The first mask layer is patterned to be a first mask pattern, and the second mask layer is patterned to be a second mask pattern formed on the first mask pattern. A first trim process is performed to the second mask pattern. A width of the second mask pattern is smaller than a width of the first mask pattern after the first trim process. A cover layer is formed covering the first mask pattern and the second mask pattern after the first trim process, and an etching process is performed to the first mask pattern after the step of forming the cover layer.

Abstract: A method is provided for fabricating stripe structures. The method includes providing a substrate; and forming a to-be-etched layer on the substrate. The method also includes forming a hard mask pattern having a first stripe on the to-be-etched layer; and forming a photoresist pattern having a stripe opening on the to-be-etched layer and the hard mask pattern having the first stripe. Further, the method includes forming a polymer layer on a top surface and side surfaces of the photoresist pattern to reduce a width of the stripe opening; forming hard mask patterns having a second stripe by etching the hard mask pattern having the first stripe using the photoresist pattern having the polymer layer as an etching mask; and forming the stripe structures by etching the to-be-etching layer using the hard mask pattern having the second stripe as an etching mask until the substrate is exposed.

Abstract: Methods for achieving sub-lithographic feature sizes in an integrated circuit (IC) layer are provided that use ion implantation to enhance or reduce the etch rate of a thin masking layer. The etch rates also can be enhanced or reduced at specific locations through multiple implantation steps. The implantation can be performed at tilted angles to achieve sub-lithographic implanted regions that are self-aligned to pre-existing photoresist or hard-mask features over the masking layer on the surface of a substrate. A higher density of features can be achieved in an IC layer than are present in an overlying masking layer with the use of ion implantation.

Abstract: A self-aligned double patterning method includes the steps of forming line structures spaced apart from each other in a first direction on a mask layer, forming dielectric layer on the line structures, performing an etch back process so that the top surfaces of the line structures and the dielectric layer are flush, forming layer structure with same material as the line structures on the line structures and the dielectric layer, forming spacers spaced apart from each other in a second direction on the layer structure, and performing an etch process with the spacers as an etch mask to pattern the line structures and the dielectric layer.

Abstract: A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns.

Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure, in which the first spacer has a top portion and a bottom portion between the top portion and the substrate. The source/drain structure is present adjacent to the bottom portion of the first spacer. The conductor is electrically connected to the source/drain structure. The protection layer is present at least between the conductor and the top portion of the first spacer. The contact etch stop layer is present at least partially between the conductor and the bottom portion of the first spacer while absent between the protection layer and the top portion of the first spacer.

Abstract: Performance and reliability of a semiconductor device are improved. An insulating film is formed such that a control gate electrode, a memory gate electrode, and a gate electrode are embedded, and then tops of the control gate electrode, the memory gate electrode, and the gate electrode are exposed by first polishing. Subsequently, a trench is formed by removing the gate electrode and filled with a metal film, and second polishing is performed to form a gate electrode including the metal film. The insulating film is an O3-TEOS film having a high gap filling characteristic, and thus reduces formation of a seam in the insulating film. Furthermore, the O3-TEOS film is subjected to heat treatment in an oxidizing atmosphere before the first polishing, thereby dishing of the insulating film is reduced during the second polishing.

Abstract: A method includes depositing a first hard mask layer on a first substrate; lithographically patterning and etching the first substrate to form a semiconductor link connected to an anode semiconductor region and a cathode semiconductor region; removing the first hard mask layer from the first substrate; depositing a second hard mask layer on the first substrate; patterning a photoresist on the first substrate and etching to form an opening in the semiconductor link; etching to remove portions of the second hard mask layer to expose a portion of a sidewall of the semiconductor link; removing the photoresist from the first substrate and the semiconductor link; and recessing the sidewalls of the semiconductor link forming first anti-fuse tip and second anti-fuse tip to form an anti-fuse with an opening between the first and second anti-fuse tips.

Abstract: After forming a sacrificial mandrel located over a substrate, alternating channel layer portions and sacrificial layer portions are formed on sidewalls of the sacrificial mandrel by epitaxial growth of alternating layers of a channel material and a sacrificial material followed by planarization. The sacrificial mandrel and the sacrificial layer portions are sequentially removed, leaving channel layer portions extending upwards from the substrate.

Abstract: A method includes depositing a first hard mask layer on a first substrate; lithographically patterning and etching the first substrate to form a semiconductor link connected to an anode semiconductor region and a cathode semiconductor region; removing the first hard mask layer from the first substrate; depositing a second hard mask layer on the first substrate; patterning a photoresist on the first substrate and etching to form an opening in the semiconductor link; etching to remove portions of the second hard mask layer to expose a portion of a sidewall of the semiconductor link; removing the photoresist from the first substrate and the semiconductor link; and recessing the sidewalls of the semiconductor link forming first anti-fuse tip and second anti-fuse tip to form an anti-fuse with an opening between the first and second anti-fuse tips.

Abstract: Methods of forming self-aligned non-mandrel cuts during the fabrication of an interconnect structure. A first dielectric hardmask layer is formed on a metal hardmask layer. A plurality of mandrels are formed on the first dielectric hardmask layer, and a plurality of spacers are formed on the first dielectric hardmask layer. The spacers are located adjacent to the mandrels. A first sacrificial layer is formed that fills spaces between the spacers, and a second dielectric hardmask layer is formed on the first sacrificial layer, the spacers, and the mandrels. A plurality of sections of a second sacrificial layer are formed on the second dielectric hardmask layer and cover the second dielectric hardmask layer over a plurality of areas that are used to form the non-mandrel cuts.

Abstract: A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

Abstract: Reducing a chance of punch-through in a FinFET structure includes providing a substrate, creating a blanket layer of semiconductor material with impurities therein over the substrate, masking a portion of the blanket layer, creating epitaxial semiconductor material on an unmasked portion of the structure, removing the mask, and etching the structure to create n-type raised structure(s) and p-type raised structure(s), a bottom portion of the raised structure(s) being surrounded by isolation material. A middle portion of the raised structure(s) includes a semiconductor material with impurities therein, the middle portion extending across the raised structure(s), and a top portion including a semiconductor material lacking added impurities.

Abstract: Methods for determining a target thickness of a conformal film with reduced uncertainty, and an integrated circuit (IC) chip having a conformal film of the target thickness are provided. In an embodiment, a first critical dimension of a structure disposed on a wafer is measured. Said structure has at least one vertical surface. A first conformal film is deposited over the structure covering each of a horizontal and the vertical surface of the structure. A second critical dimension of the covered structure is then measured. The target thickness of the conformal film is determined based on difference between the first CD measured on the structure and the second CD measured on the covered structure.

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

Abstract: A method for etching an etch layer in a stack over a substrate wherein the etch layer is under a mask layer which is under a patterned organic mask is provided. The stack and substrate is placed on a support in the plasma chamber. A silicon based layer is deposited in situ over the stack. The silicon based layer is etched to form silicon based sidewalls or spacers on sides of the patterned organic mask. The mask layer is selectively etched with respect to the silicon based sidewalls or spacers, wherein the selectively etching the mask layer undercuts the silicon based sidewalls or spacers. The etch layer is selectively etched with respect to the mask layer. The stack and substrate are removed from the support and the plasma chamber.

Abstract: A semiconductor structure having tapered damascene aperture is disclosed. The semiconductor structure including an etching stop layer over an inter-layer dielectric (ILD) layer, a low-k dielectric layer over the etching stop layer, and a tapered aperture at least going into the low-k dielectric layer; wherein the tapered aperture is filled with copper (Cu), a width of a mouth surface portion of the aperture tapers inwardly from a first, wider width to a second, narrower width at a bottom surface portion of the aperture, and the width of the bottom surface portion of the tapered aperture is less than 50 nm. Associated methods of fabricating a semiconductor structure are also disclosed.

Abstract: Provided is a method for increasing pattern density of a structure on a substrate using an integration scheme comprising: providing a substrate having a patterned layer comprising a first mandrel and an underlying layer; performing a first conformal spacer deposition creating a first conformal layer; performing a first spacer reactive ion etch (RIE) process on the first conformal layer, creating a first spacer pattern; performing a first mandrel pull process removing the first mandrel; performing a second conformal spacer deposition creating a second conformal layer; performing a second RIE process creating a second spacer pattern, the first spacer pattern acting as a second mandrel; performing a second mandrel pull process removing the first spacer pattern; and transferring the second spacer pattern into the underlying layer; where the integration targets include patterning uniformity, pulldown of structures, slimming of structures, and gouging of the underlying layer.

Abstract: A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts.

Abstract: A method of fabricating a semiconductor device with conductive patterns comprises sequentially forming an etch-target layer and a middle mold layer on a substrate, forming a first upper mold pattern and a second upper mold pattern on the middle mold layer to have top surfaces at different levels, etching the middle mold layer using the first and second upper mold patterns as an etch mask to form first and second middle mold patterns, respectively, forming a third middle mold pattern between the first and second middle mold patterns, and etching the etch-target layer using the first to third middle mold patterns as an etch mask to form conductive patterns.

Abstract: A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer and masking layers over the dielectric layer. A thin spacer layer is used to form spacers alongside a pattern. A reverse image of the spacer pattern is formed and an enlargement process is used to slightly widen the pattern. The widened pattern is subsequently used to pattern an underlying layer. This process may be used to form a pattern in a dielectric layer, which openings may then be filled with a conductive material.

Abstract: Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET manufacturing without the utilization of multiple patterning processes. Embodiments described herein also provide for fin material manufacturing methods for transitioning from silicon to III-V materials while maintaining acceptable crystal lattice orientations of the various materials utilized. Further embodiments provide etching apparatus which may be utilized to perform the methods described herein.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm.

Abstract: The present disclosure relates to a method of forming a pattern on a semiconductor substrate. One or more layers are formed over the semiconductor substrate. A first self-assembled monolayer (SAM) layer is formed over the one or more layers, wherein the first SAM layer exhibits a first SAM pattern. At least a first of the one or more layers is patterned using the first SAM layer as a first etch mask to form first pillars in the first of the one or more layers and then removing the first SAM layer. A second self-assembled monolayer (SAM) layer is formed along sidewall portions of the first pillars after the first SAM layer has been removed, wherein the second SAM layer exhibits a second SAM pattern that differs from the first SAM pattern and where the second SAM layer differs in material composition from the first SAM layer.

Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Abstract: A first portion of a multiple cycle spacer is formed on a sidewall of a patterned feature over a substrate. A spacer layer is deposited on the first portion using a first plasma process. The spacer layer is etched to form a second portion of the multiple cycle spacer on the first portion using a second plasma process. A cycle comprising depositing and etching of the spacer layer is continuously repeated until the multiple cycle spacer is formed.

Abstract: A semiconductor device and a method of forming the same are provided. An embodiment comprises a target layer and masking layers over the target layer. First openings are formed in the uppermost layer of the masking layers. Spacers are formed along sidewalls of the first openings, remaining first openings having a first pattern. Second openings are formed in the uppermost layer of the masking layers, the second openings having a second pattern. The first pattern and the second pattern are partially transferred to the target layer.

Abstract: Sidewall spacers formed on sides of mandrels are separated by first gaps in a first region and separated by wider second gaps in a second region. The second gaps are filled while a capping layer caps the first gaps. The capping layer is etched thereby exposing mandrels in the first region, which are removed. An underlying layer is patterned using the sidewall spacers separated by first gaps to form word lines in the first region and using sidewall spacers with filled second gaps to form select lines in the second region.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of mandrels on the first region and a plurality of patterns on the second region, in which the widths of the patterns on the second region are greater than the widths of the mandrels on the first region; forming a hard mask on the second region to cover the patterns; and forming a cap layer on the first region and the second region to cover the mandrels and the hard mask.

Abstract: A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts.

Abstract: An integrated circuit containing linear structures on regular pitch distances may be formed by forming linear mandrels over a layer of material for the linear structures, with mandrel pitch distances that are twice the desired linear structures' pitch distances. Mandrels for a first plurality of linear structures are shortened. A layer of spacer material is conformally formed over the mandrels and anisotropically etched back to form spacers on lateral surfaces of the mandrels. Spacers on the shortened mandrels are narrower than spacers on the unshortened mandrels as a result of the anisotropic etchback. The mandrels are removed, leaving the spacers in place to form a spacer-based etch mask for the linear structures. The layer of material for the linear structures is etched using the spacer-based etch mask to form the linear structures. The linear structures from the shortened mandrels have lower widths than the linear structures from the unshortened mandrels.

Abstract: A substrate processing apparatus includes a source gas supply system including a source gas supply pipe connected to a source gas source and a source gas supply controller; a reactive gas supply system including a reactive gas supply pipe connected to a reactive gas source, a reactive gas supply controller, a plasma generation unit and an ion trap unit and an inert gas supply pipe whereat an inert gas supply controller is disposed; a processing chamber supplied with a source gas by the source gas supply system and a reactive gas by the reactive gas supply system; and a control unit configured to control the gas supply controllers. The inert gas supply pipe has a downstream side connected between the reactive gas supply controller and the plasma generation unit and an upstream side connected to an inert gas supply source.

Abstract: An organic light-emitting device including a substrate, an anode layer on the substrate, the anode layer including WOxNy (2.2?x?2.6 and 0.22?y?0.26), an emission structure layer on the anode layer, and a cathode layer on the emission structure layer.

Abstract: An organic electroluminescent (EL) element comprises: an anode; a cathode; a functional layer disposed between the anode and the cathode, and including a light-emitting layer containing an organic material; a hole injection layer disposed between the anode and the functional layer; and a bank that defines an area in which the light-emitting layer is to be formed, wherein the hole injection layer includes tungsten oxide and includes an occupied energy level that is approximately 1.8 electron volts to approximately 3.6 electron volts lower than a lowest energy level of a valence band of the hole injection layer in terms of a binding energy, the hole injection layer has a recess in an upper surface of the area defined by the bank, and an upper peripheral edge of the recess is covered with a part of the bank.

Abstract: A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics).

Abstract: The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.