Field-effect Transistor (epo) Patents (Class 257/E21.051)
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Patent number: 8021936Abstract: A thin film transistor (TFT) and a method of manufacturing the same are provided. The TFT includes a transparent substrate, an insulating layer on a region of the transparent substrate, a monocrystalline silicon layer, which includes source, drain, and channel regions, on the insulating layer and a gate insulating film and a gate electrode on the channel region of the monocrystalline silicon layer.Type: GrantFiled: March 26, 2009Date of Patent: September 20, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Takashi Noguchi, Wenxu Xianyu, Hans S. Cho, Huaxiang Yin
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Patent number: 8021982Abstract: A method is provided for forming a metal semiconductor alloy that includes providing a deposition apparatus that includes a platinum source and a nickel source, wherein the platinum source is separate from the nickel source; positioning a substrate having a semiconductor surface in the deposition apparatus; forming a metal alloy on the semiconductor surface, wherein forming the metal alloy comprises a deposition stage in which the platinum source deposits platinum to the semiconductor surface at an initial rate at an initial period that is greater than a final rate at a final period of the deposition stage, and the nickel source deposits nickel to the semiconductor surface; and annealing the metal alloy to react the nickel and platinum with the semiconductor substrate to provide a nickel platinum semiconductor alloy.Type: GrantFiled: September 21, 2009Date of Patent: September 20, 2011Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd., Infineon Technologies AGInventors: Oh-Jung Kwon, Anthony G. Domenicucci, O Sung Kwon, Jin-Woo Choi
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Patent number: 8017465Abstract: A method for manufacturing an array substrate of liquid crystal display is performed with the following steps: providing a substrate having gate lines, a gate insulating layer and an active layer pattern formed thereon in this order; depositing a first transparent conductive layer and a source/drain metal layer in this order on the substrate; forming a photoresist layer on the source/drain metal layer through a triple-tone mask; performing a wet-etching process on the source/drain metal layer and the first transparent conductive layer exposed from the photoresist layer; performing a first ashing process on the photoresist layer and performing a dry-etching process on the source/drain metal layer, the first transparent conductive layer and the active layer pattern exposed by the first ashing process; performing a second ashing process on the photoresist layer and performing a wet-etching process on the source/drain metal layer exposed by the second ashing process; and removing the remaining photoresist layer.Type: GrantFiled: September 24, 2009Date of Patent: September 13, 2011Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.Inventors: Seungjin Choi, Youngsuk Song, Seongyeol Yoo
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Patent number: 8012818Abstract: A method of manufacturing a semiconductor device based on a SiC substrate involves forming an oxide layer on a Si-terminated face of the SiC substrate at an oxidation rate sufficiently high to achieve a near interface trap density below 5×1011 cm?2; and annealing the oxidized SiC substrate in a hydrogen-containing environment, to passivate deep traps formed in the oxide-forming step, thereby enabling manufacturing of a SiC-based MOSFET having improved inversion layer mobility and reduced threshold voltage. It has been found that the density of DTs increases while the density of NITs decreases when the Si-face of the SiC substrate is subject to rapid oxidation. The deep traps formed during the rapid oxidation can be passivated by hydrogen annealing, thus leading to a significantly decreased threshold voltage for a semiconductor device formed on the oxide.Type: GrantFiled: August 29, 2007Date of Patent: September 6, 2011Assignee: NXP B.V.Inventors: Thomas C. Roedle, Elnar O. Sveinbjornsson, Halldor O. Olafsson, Gudjon I. Gudjonsson, Carl F. Allerstam
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Patent number: 8008696Abstract: A complementary metal-oxide-semiconductor (CMOS) optical sensor structure comprises a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data. Further, a design structure for the inventive complementary metal-oxide-semiconductor (CMOS) image sensor is also provided.Type: GrantFiled: June 26, 2008Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Toshiharu Furukawa, Robert Robison, William R. Tonti
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Patent number: 7994061Abstract: A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask pattern has openings exposing gaps between each two adjacent pillars in the first direction; etching the insulation layer to a predetermined depth using the mask pattern as an etching barrier to form trenches; and filling the trenches with a conductive material to form word lines extending in the first direction.Type: GrantFiled: June 30, 2008Date of Patent: August 9, 2011Assignee: Hynix Semiconductor Inc.Inventor: Jin-Ki Jung
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Patent number: 7989354Abstract: Disclosed is a patterning method including: forming a first film on a substrate; forming a first resist film on the first film; processing the first resist film into a first resist pattern having a preset pitch by photolithography; forming a silicon oxide film on the first resist pattern and the first film by alternately supplying a first gas containing organic silicon and a second gas containing an activated oxygen species to the substrate; forming a second resist film on the silicon oxide film; processing the second resist film into a second resist pattern having a preset pitch by the photolithography; and processing the first film by using the first resist pattern and the second resist pattern as a mask.Type: GrantFiled: June 6, 2008Date of Patent: August 2, 2011Assignee: Tokyo Electron LimitedInventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
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Patent number: 7989282Abstract: A method and structure for preventing latchup. The structure includes a latchup sensitive structure and a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure.Type: GrantFiled: March 26, 2009Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventor: Steven H. Voldman
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Patent number: 7985700Abstract: A method for fabricating a semiconductor device utilizing the step of forming a first insulating film of a porous material over a substrate; the step of forming on the first insulating film a second insulating film containing a silicon compound containing Si—CH3 bonds by 30-90%, and the step of irradiating UV radiation with the second insulating film formed on the first insulating film to cure the first insulating film. Thus, UV radiation having the wavelength which eliminates CH3 groups is sufficiently absorbed by the second insulating film, whereby the first insulating film is highly strengthened with priority by the UV cure, and the first insulating film can have the film density increased without having the dielectric constant increased.Type: GrantFiled: December 8, 2008Date of Patent: July 26, 2011Assignee: Fujitsu LimitedInventors: Shirou Ozaki, Yoshihiro Nakata, Ei Yano
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Patent number: 7977178Abstract: A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.Type: GrantFiled: March 2, 2009Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: Seong-Dong Kim, Zhijiong Lou, Huilong Zhu
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Patent number: 7968370Abstract: There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire 29.Type: GrantFiled: November 7, 2008Date of Patent: June 28, 2011Assignee: Renesas Electronics CorporationInventors: Nobuya Koike, Tsukasa Matsushita, Hiroshi Sato, Keiichi Okawa, Atsushi Nishikizawa
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Patent number: 7960224Abstract: A method for operating a memory device includes applying a sequence of bias arrangements across a selected metal-oxide memory element to change among resistance states. The sequence of bias arrangements includes a first set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the first resistance state to a third resistance state, and a second set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the third resistance state to the second resistance state.Type: GrantFiled: February 19, 2009Date of Patent: June 14, 2011Assignee: Macronix International Co., Ltd.Inventors: Wei-Chih Chien, Kuo-Pin Chang, Yi-Chou Chen, Erh-Kun Lai, Kuang-Yeu Hsieh
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Patent number: 7956393Abstract: A composition for a photoresist stripper and a method of fabricating a thin film transistor array substrate are provided according to one or more embodiments. In one or more embodiments, the composition includes about 5-30 weight % of a chain amine compound, about 0.5-10 weight % of a cyclic amine compound, about 10-80 weight % of a glycol ether compound, about 5-30 weight % of distilled water, and about 0.1-5 weight % of a corrosion inhibitor.Type: GrantFiled: September 21, 2009Date of Patent: June 7, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hyun Choung, Bong-Kyun Kim, Hong-Sick Park, Sun-Young Hong, Young-Joo Choi, Byeong-Jin Lee, Nam-Seok Suh, Byung-Uk Kim, Suk-Il Yoon, Jong-Hyun Jeong, Sung-Gun Shin, Soon-Beom Huh, Se-Hwan Jung, Doo-Young Jang, Sun-Joo Park, Oh-Hwan Kweon
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Patent number: 7952193Abstract: In one embodiment, the present invention is a method and apparatus for chip cooling. One embodiment of an inventive method for bonding a liquid metal to an interface surface (e.g., a surface of an integrated circuit chip or an opposing surface of a heat sink) includes applying an adhesive to the interface surface. A metal film is then bonded to the adhesive, thereby easily adapting the interface surface for bonding to the liquid metal.Type: GrantFiled: October 30, 2008Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Bruce K. Furman, Yves C. Martin, Theodore G. Van Kessel
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Patent number: 7947548Abstract: A method includes forming elongate structures (5) on a first substrate (3), such that the material composition of each elongate structure (7) varies along its length so as to define first and second physically different sections in the elongate structures. First and second physically different devices (1, 2) are then defined in the elongate structures. Alternatively, the first and second physically different sections may be defined in the elongate structures after they have been fabricated. The elongate structures may be encapsulated and transferred to a second substrate (7). The invention provides an improved method for the formation of a circuit structure that requires first and second physically different devices (1,2) to be provided on a common substrate. In particular, only one transfer step is necessary.Type: GrantFiled: March 30, 2009Date of Patent: May 24, 2011Assignee: Sharp Kabushiki KaishaInventors: Thomas Heinz-Helmut Altebaeumer, Stephen Day, Jonathan Heffernan
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Patent number: 7948017Abstract: A method of forming an imaging array includes providing a single crystal silicon substrate having an internal separation layer, forming a patterned conductive layer proximate a first side of the single crystal silicon substrate, forming an electrically conductive layer on the first side of the single crystal silicon substrate and in communication with the patterned conductive layer, securing the single crystal silicon substrate having the patterned conductive layer and electrically conductive layer formed thereon to a glass substrate with the first side of the single crystal silicon substrate proximate the glass substrate, separating the single crystal silicon substrate at the internal separation layer to create an exposed surface opposite the first side of the single crystal silicon substrate and forming an array comprising a plurality of photosensitive elements and readout elements on the exposed surface.Type: GrantFiled: June 19, 2009Date of Patent: May 24, 2011Assignee: Carestream Health, Inc.Inventors: Timothy J. Tredwell, Jackson Lai
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Publication number: 20110114919Abstract: A graphene field effect transistor includes a gate stack, the gate stack including a seed layer, a gate oxide formed over the seed layer, and a gate metal formed over the gate oxide; an insulating layer; and a graphene sheet displaced between the seed layer and the insulating layer.Type: ApplicationFiled: November 13, 2009Publication date: May 19, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Keith A. Jenkins, Yu-Ming Lin, Alberto Valdes-Garcia
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Patent number: 7943449Abstract: A method for producing a semiconductor structure and a semiconductor component are described.Type: GrantFiled: September 30, 2008Date of Patent: May 17, 2011Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Stefan Sedlmaier, Ralf Erichsen, Hans Weber, Oliver Haeberlen, Franz Hirler
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Patent number: 7939453Abstract: A method of producing an organic transistor which can form directly an organic semiconductor layer in pattern by simple processes and can produce an organic transistor excellent in transistor characteristics.Type: GrantFiled: February 26, 2009Date of Patent: May 10, 2011Assignees: Dai Nippon Printing Co., Ltd., RikenInventors: Masataka Kano, Kazuhito Tsukagoshi, Takeo Minari
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Publication number: 20110101309Abstract: A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene.Type: ApplicationFiled: November 4, 2009Publication date: May 5, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yu-Ming Lin, Jeng-Bang Yau
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Patent number: 7935638Abstract: Methods and structures for enhancing the homogeneity in a ratio of perimeter to surface area among heterogeneous features in different substrate regions. At least one shape on the substrate includes an added edge effective to reduce a difference in the perimeter-to-surface area ratio between the features in a first substrate region and features in a second substrate region. The improved homogeneity in the perimeter-to-surface area ratio reduces variations in a thickness of a conformal layer deposited across the features in the first and second substrate regions.Type: GrantFiled: September 24, 2009Date of Patent: May 3, 2011Assignee: International Business Machines CorporationInventors: James A. Culp, John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin
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Publication number: 20110089396Abstract: Provided is a method for manufacturing a field emission array with a carbon microstructure. The method includes: a photomask attachment step of attaching a photomask with a pattern groove to one surface of a transparent substrate; a photoresist attachment step of attaching a negative photoresist to one surface of the photomask; an exposure step of irradiating light toward the opposite surface of the transparent substrate from the photomask to cure a portion of the negative photoresist with the light irradiated on the negative photoresist through the pattern groove; a developing step of removing an uncured portion of the negative photoresist while leaving the cured portion of the negative photoresist as a microstructure; a pyrolysis step of heating and carbonizing the microstructure thus obtained; and a cathode attachment step of attaching a voltage-supplying cathode to the surface of the transparent substrate on which the microstructure is formed.Type: ApplicationFiled: July 1, 2008Publication date: April 21, 2011Applicant: Korea Advanced Institute of Science and TechnologyInventors: Seung Seob Lee, Seok Woo Lee, Jung A Lee
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Patent number: 7927956Abstract: A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.Type: GrantFiled: December 12, 2006Date of Patent: April 19, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Marius K. Orlowski, Alexander L. Barr, Mariam G. Sadaka, Ted R. White
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Patent number: 7910419Abstract: A method for making a transistor with self-aligned gate and ground plane includes forming a stack, on one face of a semi-conductor substrate, the stack including an organometallic layer and a dielectric layer. The method also includes exposing a part of the organometallic layer, a portion of the organometallic layer different to the exposed part being protected from the electron beams by a mask, the shape and the dimensions of a section, in a plane parallel to the face of the substrate, of the gate of the transistor being substantially equal to the shape and to the dimensions of a section of the organometallic portion in said plane. The method also includes removing the exposed part, and forming dielectric portions in empty spaces formed by the removal of the exposed part of the organometallic layer, around the organometallic portion.Type: GrantFiled: June 11, 2009Date of Patent: March 22, 2011Assignee: Commissariat a l'Energie AtomiqueInventors: Claire Fenouillet-Beranger, Philippe Coronel
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Patent number: 7910486Abstract: A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.Type: GrantFiled: June 12, 2009Date of Patent: March 22, 2011Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
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Patent number: 7910936Abstract: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.Type: GrantFiled: December 9, 2008Date of Patent: March 22, 2011Assignee: Texas Instruments IncorporatedInventors: Sameer Kumar Ajmera, Patricia Beauregard Smith, Changming Jin
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Patent number: 7906834Abstract: A display device having a thin film semiconductor device including a semiconductor thin film having first and second semiconductor regions formed each into a predetermined shape above an insulative substrate, a conductor fabricated into a predetermined shape to the semiconductor thin film and a dielectric film put between the semiconductor thin film and the conductor, in which the semiconductor thin film is a polycrystal thin film with the crystallization ratio thereof exceeding 90% and the difference of unevenness on the surface of the semiconductor thin film does not exceed 10 nm.Type: GrantFiled: July 29, 2008Date of Patent: March 15, 2011Assignee: Hitachi Displays, Ltd.Inventors: Toshiyuki Mine, Mitsuharu Tai, Akio Shima
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Patent number: 7902001Abstract: Provided is a sacrifice layer formed on a first substrate. A thin film laminated body is formed on the sacrifice layer. A separation groove exposing the sacrifice layer is formed to divide the thin film laminated body into at least one thin film device. The sacrifice layer is partially removed using a dry etching process. After the partial removal of the sacrifice layer, a remaining sacrifice layer region maintains the thin film device on the first substrate. A supporting structure is temporarily joined to the thin film device. The thin film device joined to the supporting structure is separated from the first substrate. Then, the remaining sacrifice layer is removed. The thin film device joined to the supporting structure is joined to a second substrate. Finally, the supporting structure is separated from the thin film device.Type: GrantFiled: June 5, 2009Date of Patent: March 8, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Sang Jin Kim, Yongsoo Oh, Hwan-Soo Lee
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Patent number: 7897514Abstract: System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer.Type: GrantFiled: January 24, 2008Date of Patent: March 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Shi Liu, Chen-Hua Yu
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Patent number: 7897414Abstract: A method of manufacturing a semiconductor device has forming a ferroelectric film over a substrate, placing the substrate having the ferroelectric film in a chamber substantially held in vacuum, introducing oxygen and an inert gas into the chamber, annealing the ferroelectric film in the chamber, and containing oxygen and the inert gas while the chamber is maintained sealed.Type: GrantFiled: January 8, 2009Date of Patent: March 1, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Kouichi Nagai
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Patent number: 7888266Abstract: A complementary metal-oxide-semiconductor (CMOS) optical sensor structure includes a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data.Type: GrantFiled: June 26, 2008Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Toshiharu Furukawa, Robert Robison, William R. Tonti
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Patent number: 7888221Abstract: The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.Type: GrantFiled: August 22, 2008Date of Patent: February 15, 2011Assignee: Intel CorporationInventors: Jack T. Kavalieros, Matthew V. Metz, Gilbert Dewey, Been-Yih Jin, Justin K. Brask, Suman Datta, Robert S. Chau
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Publication number: 20110024717Abstract: A method and system for the preferential growth of semiconducting vertically-aligned single-walled carbon nanotubes (VA-SWNTs) is provided. The method combines the use of plasma-enhanced chemical vapor deposition at low pressure with rapid heating. The method provides a high yield of up to approximately 96% semiconducting SWNTs in the VA-SWNT array. The as-synthesized semiconducting SWNTs can be used directly for fabricating field effect transistor (FET) devices without the need for any post-synthesis purification or separation.Type: ApplicationFiled: July 29, 2009Publication date: February 3, 2011Applicant: UNIVERSITY OF DAYTONInventors: Liangti Qu, Liming Dai
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Patent number: 7879666Abstract: A semiconductor process and apparatus fabricate a metal gate electrode (30) and an integrated semiconductor resistor (32) by forming a metal-based layer (26) and semiconductor layer (28) over a gate dielectric layer (24) and then selectively implanting the resistor semiconductor layer (28) in a resistor area (97) to create a conductive upper region (46) and a conduction barrier (47), thereby confining current flow in the resistor semiconductor layer (36) to only the top region (46) in the finally formed device.Type: GrantFiled: July 23, 2008Date of Patent: February 1, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Da Zhang, Chendong Zhu, Xiangdong Chen, Melanie Sherony
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Patent number: 7863140Abstract: A molecular detection chip including a metal oxide silicon-field effect transistor (MOSFET) on sidewalls of a micro-fluid channel and a molecular detection device including the molecular detection chip are provided. A molecular detection method, particularly, qualification methods for the immobilization of molecular probes and the binding of a target sample to the molecular probes, using the molecular detection device, and a nucleic acid mutation assay device and method are also provided. The formation of the MOSFET on the sidewalls of the micro-fluid channel makes easier to highly integrate a molecular detection chip. In addition, immobilization of probes directly on the surface of a gate electrode ensures the molecular detection chip to check for the immobilization of probes and coupling of a target molecule to the probes in situ.Type: GrantFiled: May 31, 2007Date of Patent: January 4, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Geun-Bae Lim, Chin-Sung Park, Yoon-Kyoung Cho, Sun-Hee Kim
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Patent number: 7858990Abstract: A graphene-based device is formed with a trench in one or more layers of material, a graphene layer within the trench, and a device structure on the graphene layer and within the trench. Fabrication techniques includes forming a trench defined by one or more layers of material, forming a graphene layer within the trench, and forming a device structure on the graphene layer and within the trench.Type: GrantFiled: August 29, 2008Date of Patent: December 28, 2010Assignee: Advanced Micro Devices, Inc.Inventors: An Chen, Zoran Krivokapic
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Patent number: 7858454Abstract: A method is provided for forming a self-aligned carbon nanotube (CNT) field effect transistor (FET). According to one feature, a self-aligned source-gate-drain (S-G-D) structure is formed that allows for the shrinking of the gate length to arbitrarily small values, thereby enabling ultra-high performance CNT FETs. In accordance with another feature, an improved design of the gate to possess a “T”-shape, referred to as the “T-Gate,” thereby enabling a reduction in gate resistance and further providing an increased power gain. The self-aligned T-gate CNT FET is formed using simple fabrication steps to ensure a low cost, high yield process.Type: GrantFiled: July 29, 2008Date of Patent: December 28, 2010Assignee: RF Nano CorporationInventor: Amol M. Kalburge
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Patent number: 7858461Abstract: A semiconductor device includes a transistor having a recessed gate, contact plugs formed in a region of a plurality of trenches, which are formed by recessing a semiconductor substrate. Further, a metal line and a source/drain region can be connected through the contact plug, so that on-current can be increased as much as an increased channel area.Type: GrantFiled: July 23, 2010Date of Patent: December 28, 2010Assignee: Hynix Semiconductor Inc.Inventor: Dae Sik Kim
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Patent number: 7858989Abstract: A graphene-based device is formed with a substrate having a trench therein, a device structure on the substrate and within the trench, a graphene layer over the device structure, and a protective layer over the graphene layer. Fabrication techniques include forming a trench in a substrate, forming a device structure within the trench, forming a graphene layer over the device structure, and forming a protective layer over the graphene layer.Type: GrantFiled: August 29, 2008Date of Patent: December 28, 2010Assignee: GLOBALFOUNDRIES Inc.Inventors: An Chen, Zoran Krivokapic
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Patent number: 7855404Abstract: A complementary BiCMOS semiconductor device comprises a substrate of a first conductivity type and a number of active regions which are provided therein and which are delimited in the lateral direction by shallow field insulation regions, in which vertical npn-bipolar transistors with an epitaxial base are arranged in a first subnumber of the active regions and vertical pnp-bipolar transistors with an epitaxial base are arranged in a second subnumber of the active regions, wherein either one transistor type or both transistor types have both a collector region and also a collector contact region in one and the same respective active region. To improve the high-frequency properties exclusively in a first transistor type in which the conductivity type of the substrate is identical to that of the collector region, an insulation doping region is provided between the collector region and the substrate.Type: GrantFiled: December 1, 2004Date of Patent: December 21, 2010Assignee: IHP GmbH—Innovations for High Performance Microelectronics/Leibniz-Instituit fur Innovative MikroelektronikInventors: Bernd Heinenman, Jürgen Drews, Steffen Marschmayer, Holger Rücker
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Patent number: 7855121Abstract: Provided are a method of forming an organic semiconductor thin film and a method of manufacturing a semiconductor device using the. According to example embodiments, a method of forming an organic semiconductor thin film at least may include exposing a lower substrate coated with an organic semiconductor solution using a method of generating a shearing stress to the portion of the lower substrate coated with the organic semiconductor solution. A guide structure may be formed adjacent to the organic semiconductor solution.Type: GrantFiled: March 27, 2009Date of Patent: December 21, 2010Assignees: Samsung Electronics Co., Ltd., The Board of Trustees of the Laland Stanford Junior UniversityInventors: Do Hwan Kim, Sangyoon Lee, Hector Alejandro Becerril Garcia, Mark Roberts, Zhenan Bao, Zihong Liu
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Patent number: 7838353Abstract: Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.Type: GrantFiled: August 12, 2008Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Patent number: 7838402Abstract: A method of manufacturing an electronic apparatus having a resist pattern provided over a substrate provided with a thin film transistor, the method includes the steps of forming by application a resist film over the substrate in the state of covering the thin film transistor, forming a resist pattern by subjecting the resist film to exposure to light and a developing treatment, and irradiating the resist pattern with at least one of ultraviolet light and visible light in a dry atmosphere in the condition where a channel part of the thin film transistor is prevented from being irradiated with light having a wavelength of shorter than 260 nm, wherein a step of heat curing the resist pattern is conducted after the irradiation with at least one of ultraviolet light and visible light.Type: GrantFiled: November 21, 2008Date of Patent: November 23, 2010Assignee: Sony CorporationInventors: Koichi Nagasawa, Takashi Yamaguchi, Nobutaka Ozaki, Yasuhiro Kanaya, Hirohisa Takeda, Yasuo Mikami, Yoshifumi Mutoh
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Patent number: 7838410Abstract: A method of electrically connecting an element to wiring includes the steps of forming a conductive fixing member precursor layer at least on wiring provided on a base; and arranging an element having a connecting portion on the wiring such that the connecting portion contacts the conductive fixing member precursor layer, and then heating the conductive fixing member precursor layer to form a conductive fixing member latter, thereby fixing the connecting portion of the element to the wiring, with the conductive fixing member layer therebetween, wherein the conductive fixing member precursor layer is composed of a solution-tape conductive material.Type: GrantFiled: June 27, 2008Date of Patent: November 23, 2010Assignee: Sony CorporationInventors: Naoki Hirao, Yasunobu Iwakoshi, Katsuhiro Tomoda, Huy Sam
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Publication number: 20100289030Abstract: In a conventional diamond semiconductor element, because of high density of crystal defects, it is impossible to reflect the natural physical properties peculiar to a diamond, such as high thermal conductivity, high breakdown field strength, high-frequency characteristics and the like, in the transistor characteristics. By slightly shifting surface orientation of a diamond substrate in a [001] direction, a significant reduction in crystal defects peculiar to a diamond is possible. The equivalent effects are also provided by shifting surface orientation of a single-crystal diamond thin-film or channel slightly from a [001] direction. It is possible to obtain a significantly high transconductance gm as compared with that in a transistor produced using conventional surface orientation.Type: ApplicationFiled: June 20, 2006Publication date: November 18, 2010Applicant: Nippon Telegraph and Telephone CorporationInventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
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Patent number: 7833845Abstract: An object is to provide a manufacturing method of a microcrystalline semiconductor film with favorable quality over a large-area substrate. After forming a gate insulating film over a gate electrode, in order to improve quality of a microcrystalline semiconductor film formed in an initial stage, glow discharge plasma is generated by supplying high-frequency powers with different frequencies, and a lower part of the film near an interface with the gate insulating film is formed under a first film formation condition, which is low in film formation rate but results in a good quality film. Thereafter, an upper part of the film is deposited under a second film formation condition with higher film formation rate, and further, a buffer layer is stacked on the microcrystalline semiconductor film.Type: GrantFiled: August 12, 2008Date of Patent: November 16, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Sachiaki Teduka, Satoshi Toriumi, Makoto Furuno, Yasuhiro Jinbo, Koji Dairiki, Hideaki Kuwabara
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Patent number: 7833887Abstract: A method of forming a notched-base spacer profile for non-planar transistors includes providing a semiconductor fin having a channel region on a substrate and forming a gate electrode adjacent to sidewalls of the channel region and on a top surface of the channel region, the gate electrode having on a top surface a hard mask. a spacer layer is deposited over the gate and the fin using a enhanced chemical vapor deposition (PE-CVD) process. A multi-etch process is applied to the spacer layer to form a pair of notches on laterally opposite sides of the gate electrode, wherein each notch is located adjacent to sidewalls of the fin and on the top surface of the fin.Type: GrantFiled: June 24, 2008Date of Patent: November 16, 2010Assignee: Intel CorporationInventors: Willy Rachmady, Jack Kavalieros
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Patent number: 7833871Abstract: A laser annealing method for executing laser annealing by irradiating a semiconductor film formed on a surface of a substrate with a laser beam, the method including the steps of, generating a linearly polarized rectangular laser beam whose cross section perpendicular to an advancing direction is a rectangle with an electric field directed toward a long-side direction of the rectangle or an elliptically polarized rectangular laser beam having a major axis directed toward a long-side direction, causing the rectangular laser beam to be introduced to the surface of the substrate, and setting a wavelength of the rectangular laser beam to a length which is about a desired size of a crystal grain in a standing wave direction.Type: GrantFiled: September 12, 2006Date of Patent: November 16, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Ryusuke Kawakami, Kenichirou Nishida, Norihito Kawaguchi, Miyuki Masaki, Atsushi Yoshinouchi
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Patent number: 7829402Abstract: A MOSFET device and a method for fabricating MOSFET devices are disclosed. The method includes providing a semiconductor device structure including a semiconductor device layer of a first conductivity type, and ion implanting a well structure of a second conductivity type in the semiconductor device layer, where the ion implanting includes providing a dopant concentration profile in a single mask implant sequence.Type: GrantFiled: February 10, 2009Date of Patent: November 9, 2010Assignee: General Electric CompanyInventors: Kevin Sean Matocha, Stephen Daley Arthur, Ramakrishna Rao, Peter Almern Losee, Zachary Matthew Stum
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Patent number: 7829474Abstract: A method for arraying nano material includes preparing a substrate coated with a dispersion solution where nano materials are dispersed and arraying the nano materials in the dispersion solution, in a uniform direction using a charged body.Type: GrantFiled: May 4, 2006Date of Patent: November 9, 2010Assignee: LG. Display Co., Ltd.Inventor: Gee Sung Chae