Passivating Silicon Carbide Surface (epo) Patents (Class 257/E21.055)
  • Patent number: 11145735
    Abstract: Forming an ohmic contact sealing layer disposed at an intersection between a sidewall of an ohmic contact and a surface of a semiconductor; forming an ohmic contact sealing layer on the intersection between a sidewall of the ohmic contact and the surface of the semiconductor; and subjecting the semiconductor with the ohmic contact to a chemical etchant.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: October 12, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: Paul J. Duval, John P. Bettencourt, James W. McClymonds, Paul M. Alcorn, Philip C. Balas, II, Michael S. Davis
  • Patent number: 10541307
    Abstract: A semiconductor device according to an embodiment includes a p-type SiC layer and a contact electrode electrically connected to the SiC layer. The contact electrode includes metal. And a region is provided in the SiC layer adjacent to the contact electrode. The region having an oxygen concentration not lower than 1×1016 cm?3 and not higher than 1×1021 cm?3.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: January 21, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Patent number: 10049956
    Abstract: A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chi Chuang, Hsuan-Hui Hung, Kun-Ming Huang, Ming-Yi Lin
  • Patent number: 10002958
    Abstract: Systems and method are provided for depositing metal on GaN transistors after gate formation using a metal nitride Schottky gate. Embodiments of the present disclosure use a “diamond last” process using thermally stable metal nitride gate electrodes to enable thicker heat spreading films and facilitate process integration. In an embodiment, the “diamond last” process with high thermal conductivity diamond is enabled by the integration of thermally stable metal-nitride gate electrodes.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 19, 2018
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Virginia D. Wheeler, Andrew D. Koehler, Karl D. Hobart
  • Patent number: 9040345
    Abstract: A method of laser ablation for electrical contact to a buried electrically conducting layer in diamond comprising polishing a single crystal diamond substrate having a first carbon surface, implanting the diamond with a beam of 180 KeV followed by 150 KeV C+ ions at fluencies of 4×1015 ions/cm2 and 5×1015 ions/cm2 respectively, forming an electrically conducting carbon layer beneath the first carbon surface, and ablating the single crystal diamond which lies between the electrically conducting layer and the first carbon surface.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 26, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Bradford B. Pate, Matthew P. Ray, Jeffrey W. Baldwin
  • Patent number: 9000448
    Abstract: A MOSFET having a high mobility may be obtained by introducing nitrogen to the channel region or the interface between the gate dielectric film and the SiC substrate of the SiC MOSFET, but there is a problem that a normally-on MOSFET is obtained. For realizing both a high mobility and normally-off, and for providing a SiC MOSFET having further high reliability, nitrogen is introduced to the channel region of the SiC substrate or the interface between the gate dielectric film and the SiC substrate, and furthermore a metal oxide film having a thickness of 10%, or less of the total thickness of the gate dielectric film is inserted in the gate dielectric film.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: April 7, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Hirotaka Hamamura, Yasuhiro Shimamoto, Hiroyuki Okino
  • Patent number: 8940639
    Abstract: A MEMS device with movable MEMS structure and electrodes is produced by fabricating electrodes and shielding the electrodes with diamond buttons during subsequent fabrication steps, such as the etching of sacrificial oxide using vapor HF. In some embodiments, the diamond buttons are removed after the movable MEMS structure is released.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 27, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Fang Liu, Kuang L. Yang
  • Patent number: 8916474
    Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor package having a first semiconductor die, which is disposed in a first encapsulant. An opening is disposed in the first encapsulant. A second semiconductor package including a second semiconductor die is disposed in a second encapsulant. The second semiconductor package is disposed at least partially within the opening in the first encapsulant.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: December 23, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef H•glauer
  • Patent number: 8765617
    Abstract: A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon nitride on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including a nitrogen atom.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Inc.
    Inventor: Takeyoshi Masuda
  • Patent number: 8536066
    Abstract: Methods of forming an oxide layer on silicon carbide include thermally growing an oxide layer on a layer of silicon carbide, and annealing the oxide layer in an environment containing NO at a temperature greater than 1175° C. The oxide layer may be annealed in NO in a silicon carbide tube that may be coated with silicon carbide. To form the oxide layer, a preliminary oxide layer may be thermally grown on a silicon carbide layer in dry O2, and the preliminary oxide layer may be re-oxidized in wet O2.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: September 17, 2013
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Brett Hull, Sumi Krishnaswami
  • Patent number: 8450750
    Abstract: A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface with a trench having a sidewall formed of a crystal plane tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the sidewall of the trench. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the sidewall of the trench and the insulating film is not less than 1×1021 cm?3, and the semiconductor device has a channel direction in a range of ±10° relative to the direction orthogonal to the <?2110> direction in the sidewall of the trench. A method of manufacturing the silicon carbide semiconductor device is also provided.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: May 28, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Misako Honaga, Shin Harada
  • Patent number: 8324704
    Abstract: A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: December 4, 2012
    Assignees: DENSO CORPORATION, Toyota Jidosha Kabushiki Kaisha
    Inventors: Takeo Yamamoto, Takeshi Endo, Eiichi Okuno, Hirokazu Fujiwara, Masaki Konishi, Takashi Katsuno, Yukihiko Watanabe
  • Patent number: 8183573
    Abstract: An embodiment of a process for forming an interface between a silicon carbide (SiC) layer and a silicon oxide (SiO2) layer of a structure designed to conduct current is disclosed. A first epitaxial layer having a first doping level is homo-epitaxially grown on a substrate. The homo-epitaxial growth is preceded by growing, on the first epitaxial layer, a second epitaxial layer having a second doping level higher than the first doping level. Finally, the second epitaxial layer is oxidized so as to be totally removed. Thereby, a silicon oxide layer of high quality is formed, and the interface between the second epitaxial layer and silicon oxide has a low trap density.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: May 22, 2012
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giovanni Abagnale, Dario Salinas, Sebastiano Ravesi
  • Patent number: 8119539
    Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: February 21, 2012
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
  • Patent number: 7960256
    Abstract: In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: June 14, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Zhiyuan Ye, Yihwan Kim, Xiaowei Li, Ali Zojaji, Nicholas C. Dalida, Jinsong Tang, Xiao Chen, Arkadii V. Samoilov
  • Patent number: 7888256
    Abstract: An embodiment of a process for forming an interface between a silicon carbide (SiC) layer and a silicon oxide (SiO2) layer of a structure designed to conduct current is disclosed. A first epitaxial layer having a first doping level is homo-epitaxially grown on a substrate. The homo-epitaxial growth is preceded by growing, on the first epitaxial layer, a second epitaxial layer having a second doping level higher than the first doping level. Finally, the second epitaxial layer is oxidized so as to be totally removed. Thereby, a silicon oxide layer of high quality is formed, and the interface between the second epitaxial layer and silicon oxide has a low trap density.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: February 15, 2011
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Giovanni Abagnale, Dario Salinas, Sebastiano Ravesi
  • Patent number: 7820534
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes ion-implanting an impurity in a surface of a silicon carbide wafer, and forming a carbon protection film of a predetermined thickness over all surfaces of the silicon carbide wafer, which has been ion-implanted with the impurity, by a chemical vapor deposition method that deposits a film by pyrolyzing a hydrocarbon gas. The method also includes annealing the silicon carbide wafer after the forming the carbon protection film.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: October 26, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takao Sawada, Tomokatsu Watanabe
  • Publication number: 20100244049
    Abstract: A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.
    Type: Application
    Filed: March 23, 2010
    Publication date: September 30, 2010
    Applicants: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takeo Yamamoto, Takeshi Endo, Eiichi Okuno, Hirokazu Fujiwara, Masaki Konishi, Takashi Katsuno, Yukihiko Watanabe
  • Publication number: 20100221924
    Abstract: Methods of forming an oxide layer on silicon carbide include thermally growing an oxide layer on a layer of silicon carbide, and annealing the oxide layer in an environment containing NO at a temperature greater than 1175° C. The oxide layer may be annealed in NO in a silicon carbide tube that may be coated with silicon carbide. To form the oxide layer, a preliminary oxide layer may be thermally grown on a silicon carbide layer in dry O2, and the preliminary oxide layer may be re-oxidized in wet O2.
    Type: Application
    Filed: May 10, 2010
    Publication date: September 2, 2010
    Inventors: Mrinal K. Das, Brett Hull, Sumi Krishnaswami
  • Patent number: 7763543
    Abstract: A method for manufacturing a silicon carbide semiconductor apparatus is disclosed. According to the method, an element structure is formed on a front surface side of a semiconductor substrate. A rear surface of the semiconductor substrate is grinded or polished in a direction parallel to a flat surface of a table. A front surface of the semiconductor substrate is grinded and polished in a direction parallel to the rear surface after the rear surface of the semiconductor substrate is grinded or polished.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: July 27, 2010
    Assignee: DENSO CORPORATION
    Inventors: Masatake Nagaya, Yuuichi Takeuchi, Katsuhiro Nagata
  • Patent number: 7727904
    Abstract: Methods of forming an oxide layer on silicon carbide include thermally growing an oxide layer on a layer of silicon carbide, and annealing the oxide layer in an environment containing NO at a temperature greater than 1175° C. The oxide layer may be annealed in NO in a silicon carbide tube that may be coated with silicon carbide. To form the oxide layer, a preliminary oxide layer may be thermally grown on a silicon carbide layer in dry O2, and the preliminary oxide layer may be re-oxidized in wet O2.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: June 1, 2010
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Brett Hull, Sumi Krishnaswami
  • Patent number: 7675068
    Abstract: A silicon carbide structure is disclosed that is suitable for use as a substrate in the manufacture of electronic devices such as light emitting diodes. The structure includes a silicon carbide wafer having a first and second surface and having a predetermined conductivity type and an initial carrier concentration; a region of implanted dopant atoms extending from the first surface into the silicon carbide wafer to a predetermined depth, with the region having a higher carrier concentration than the initial carrier concentration in the remainder of the wafer; and an epitaxial layer on the first surface of the silicon carbide wafer.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: March 9, 2010
    Assignee: Cree, Inc.
    Inventors: Davis Andrew McClure, Alexander Suvorov, John Adam Edmond, David Beardsley Slater, Jr.
  • Publication number: 20090269908
    Abstract: A manufacturing method of a semiconductor device comprises a process of doping conductive impurities in a silicon carbide substrate, a process of forming a cap layer on a surface of the silicon carbide substrate, a process of activating the conductive impurities doped in the silicon carbide substrate, a process of oxidizing the cap layer after a first annealing process, and a process of removing the oxidized cap layer. It is preferred that the cap layer is formed from material that includes metal carbide. Since the oxidation onset temperature of metal carbide is comparatively low, the oxidization of the cap layer becomes easy if metal carbide is included in the cap layer. Specifically, it is preferred that the cap layer is formed from metal carbide that has an oxidation onset temperature of 1000 degrees Celsius or below, such as tantalum carbide.
    Type: Application
    Filed: April 20, 2009
    Publication date: October 29, 2009
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hirokazu Fujiwara, Masaki Konishi, Takeo Yamamoto, Eiichi Okuno, Yukihiko Watanabe, Takashi Katsuno
  • Patent number: 7598576
    Abstract: An improved termination structure for high field semiconductor devices in silicon carbide is disclosed. The termination structure includes a silicon carbide-based device for high-field operation, an active region in the device, an edge termination passivation for the active region, in which the edge termination passivation includes, an oxide layer on at least some of the silicon carbide portions of the device for satisfying surface states and lowering interface density, a non-stoichiometric layer of silicon nitride on the oxide layer for avoiding the incorporation of hydrogen and for reducing parasitic capacitance and minimizing trapping, and, a stoichiometric layer of silicon nitride on the nonstoichiometric layer for encapsulating the nonstoichiometric layer and the oxide layer.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: October 6, 2009
    Assignee: Cree, Inc.
    Inventors: Allan Ward, III, Jason Patrick Henning
  • Patent number: 7572741
    Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500 ° C. to about 1300 ° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: August 11, 2009
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
  • Patent number: 7550336
    Abstract: A method for fabricating an NMOS transistor is disclosed. First, a substrate having a gate structure thereon is provided. A carbon implantation process is performed thereafter by implanting carbon atoms into the substrate for forming a silicon carbide region in the substrate. Subsequently, a source/drain region is formed surrounding the gate structure. By conducting a carbon implantation process into the substrate and a corresponding amorphorized implantation process before or after the carbon implantation process is completed, the present invention eliminates the need of forming a recess for accommodating an epitaxial layer composed of silicon carbide while facilitates the formation of silicon carbide from the combination of both implantation processes.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: June 23, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Fu Hsiao, Po-Yuan Chen, Jung-Chin Chen
  • Patent number: 7534729
    Abstract: Compositions and methods are provided herein that include modifications to at least one surface of a silicon-based semiconductor material. Modifications occur in a liquid and comprise alterations of surface states, passivation, cleaning and/or etching of the surface, thereby providing an improved surface to the semiconductor material. Modifications of surface states include reduction or elimination of an electrically active state of the surface, wherein, at the atomic level, the surface binding characteristics are changed. Passivation includes the termination of dangling bonds on the surface of the semiconductor material.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: May 19, 2009
    Assignee: Board of Regents, The University of Texas System
    Inventors: Meng Tao, Muhammad Y. Ali
  • Publication number: 20090004883
    Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.
    Type: Application
    Filed: September 16, 2005
    Publication date: January 1, 2009
    Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
  • Publication number: 20080290348
    Abstract: In the present invention, a vertical MOSFET is formed by growing epitaxial Si on a SiC substrate and forming a Si oxide layer on the Si. In particular, a semiconductor device according to the present invention includes a SiC substrate, and an epitaxial Si layer formed on a surface of the SiC substrate, and a Si oxide layer formed on the epitaxial Si layer, and a gate electrode formed on the Si oxide layer, and a source region formed in the epitaxial Si layer, and a drain electrode connected to the SiC substrate.
    Type: Application
    Filed: April 23, 2008
    Publication date: November 27, 2008
    Inventor: Toru Yoshie
  • Publication number: 20080203441
    Abstract: A SiC semiconductor device having a MOS structure includes: a SiC substrate; a channel region providing a current path; first and second impurity regions on upstream and downstream sides of the current path, respectively; and a gate on the channel region through the gate insulating film. The channel region for flowing current between the first and second impurity regions is controlled by a voltage applied to the gate. An interface between the channel region and the gate insulating film has a hydrogen concentration equal to or greater than 4.7×1020 cm?3. The interface provides a channel surface having a (000-1)-orientation surface.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 28, 2008
    Applicant: DENSO CORPORATION
    Inventor: Takeshi Endo
  • Patent number: 7345309
    Abstract: A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: March 18, 2008
    Assignee: Lockheed Martin Corporation
    Inventors: An-Ping Zhang, Larry B. Rowland, James W. Kretchmer, Jesse Tucker, Edmund B. Kaminsky